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From: Andre Przywara <andre.przywara@arm.com>
To: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: "Jernej Škrabec" <jernej.skrabec@gmail.com>,
	"Vasily Khoruzhick" <anarsoul@gmail.com>,
	"Yangtao Li" <tiny.windzz@gmail.com>,
	"Chen-Yu Tsai" <wens@csie.org>,
	"Samuel Holland" <samuel@sholland.org>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	"Zhang Rui" <rui.zhang@intel.com>,
	"Lukasz Luba" <lukasz.luba@arm.com>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Martin Botka" <martin.botka@somainline.org>,
	"Maksim Kiselev" <bigunclemax@gmail.com>,
	"Bob McChesney" <bob@electricworry.net>,
	linux-pm@vger.kernel.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-sunxi@lists.linux.dev
Subject: Re: [PATCH v5 1/7] soc: sunxi: sram: export register 0 for THS on H616
Date: Fri, 23 Feb 2024 17:25:51 +0000	[thread overview]
Message-ID: <20240223172551.57b7e066@donnerap.manchester.arm.com> (raw)
In-Reply-To: <469e83f3-57ef-492b-8f27-5a052b064106@linaro.org>

On Fri, 23 Feb 2024 18:00:51 +0100
Daniel Lezcano <daniel.lezcano@linaro.org> wrote:

Hi Daniel,

> On 23/02/2024 17:02, Andre Przywara wrote:
> > On Thu, 22 Feb 2024 19:44:12 +0100
> > Daniel Lezcano <daniel.lezcano@linaro.org> wrote:
> > 
> > Hi Daniel,
> >   
> >> On 22/02/2024 19:26, Jernej Škrabec wrote:  
> >>> Dne ponedeljek, 19. februar 2024 ob 16:36:33 CET je Andre Przywara napisal(a):  
> >>>> The Allwinner H616 SoC contains a mysterious bit at register offset 0x0
> >>>> in the SRAM control block. If bit 16 is set (the reset value), the
> >>>> temperature readings of the THS are way off, leading to reports about
> >>>> 200C, at normal ambient temperatures. Clearing this bits brings the
> >>>> reported values down to the expected values.
> >>>> The BSP code clears this bit in firmware (U-Boot), and has an explicit
> >>>> comment about this, but offers no real explanation.
> >>>>
> >>>> Experiments in U-Boot show that register 0x0 has no effect on the SRAM C
> >>>> visibility: all tested bit settings still allow full read and write
> >>>> access by the CPU to the whole of SRAM C. Only bit 24 of the register at
> >>>> offset 0x4 makes all of SRAM C inaccessible by the CPU. So modelling
> >>>> the THS switch functionality as an SRAM region would not reflect reality.
> >>>>
> >>>> Since we should not rely on firmware settings, allow other code (the THS
> >>>> driver) to access this register, by exporting it through the already
> >>>> existing regmap. This mimics what we already do for the LDO control and
> >>>> the EMAC register.
> >>>>
> >>>> To avoid concurrent accesses to the same register at the same time, by
> >>>> the SRAM switch code and the regmap code, use the same lock to protect
> >>>> the access. The regmap subsystem allows to use an existing lock, so we
> >>>> just need to hook in there.
> >>>>
> >>>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>  
> >>>
> >>> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
> >>>
> >>> I guess this one goes through sunxi tree, right?  
> >>
> >> I'll pick this patch along with the patch 2-6, so through the thermal
> >> tree. The patch 7/7 will go indeed via the sunxi tree  
> > 
> > many thanks for picking those up! I see them in your bleeding-edge branch,
> > but are they on route for 6.9, so will you put them in -next soon? Or are
> > you waiting for more ACKs?  
> 
> I've enough ack. The bleeding-edge is merged with the linux-pm tree. If 
> everything is going well, I will move it to the linux-next branch 
> probably today or Monday

thanks for the quick reply, that's great to hear. All fine then!

Thanks,
Andre


  reply	other threads:[~2024-02-23 17:25 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-19 15:36 [PATCH v5 0/7] add support for H616 thermal system Andre Przywara
2024-02-19 15:36 ` [PATCH v5 1/7] soc: sunxi: sram: export register 0 for THS on H616 Andre Przywara
2024-02-22 18:26   ` Jernej Škrabec
2024-02-22 18:44     ` Daniel Lezcano
2024-02-22 19:15       ` Jernej Škrabec
2024-02-23 16:02       ` Andre Przywara
2024-02-23 17:00         ` Daniel Lezcano
2024-02-23 17:25           ` Andre Przywara [this message]
2024-02-19 15:36 ` [PATCH v5 2/7] dt-bindings: thermal: sun8i: Add H616 THS controller Andre Przywara
2024-02-19 15:36 ` [PATCH v5 3/7] thermal: sun8i: explain unknown H6 register value Andre Przywara
2024-02-19 15:36 ` [PATCH v5 4/7] thermal: sun8i: extend H6 calibration to support 4 sensors Andre Przywara
2024-02-19 15:36 ` [PATCH v5 5/7] thermal: sun8i: add SRAM register access code Andre Przywara
2024-02-19 15:36 ` [PATCH v5 6/7] thermal: sun8i: add support for H616 THS controller Andre Przywara
2024-02-19 15:36 ` [PATCH v5 7/7] arm64: dts: allwinner: h616: Add thermal sensor and zones Andre Przywara
2024-02-22 18:27   ` Jernej Škrabec
2024-02-23 19:59   ` Jernej Škrabec
2024-02-23 20:41     ` Jernej Škrabec
2024-02-21 13:42 ` [PATCH v5 0/7] add support for H616 thermal system Daniel Lezcano
2024-02-21 21:53   ` Vasily Khoruzhick

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