* [PATCH 0/2] amd-pstate: Better handling for systems without an MSR @ 2024-09-01 5:00 Mario Limonciello 2024-09-01 5:00 ` [PATCH 1/2] cpufreq/amd-pstate: Add an early param to disable MSR mode Mario Limonciello 2024-09-01 5:00 ` [PATCH 2/2] cpufreq/amd-pstate: Catch failures for amd_pstate_epp_update_limit() Mario Limonciello 0 siblings, 2 replies; 5+ messages in thread From: Mario Limonciello @ 2024-09-01 5:00 UTC (permalink / raw) To: Gautham R . Shenoy, Perry Yuan Cc: open list:X86 ARCHITECTURE (32-BIT AND 64-BIT), open list:CPU FREQUENCY SCALING FRAMEWORK, Mario Limonciello From: Mario Limonciello <mario.limonciello@amd.com> Since the policy changed for amd-pstate to enable on systems with shared memory designs by default too some users have reported that software like power-profiles-daemon fails with an error -524. This happens because error codes from the CPPC API are ignored during the initial setup so all the sysfs files are created but don't work. This series does two things: 1. Add a debugging early param to force going into shared memory mode even on a system with a dedicated MSR. This will aid in debugging reported issues. 2. Catch errors in amd_pstate_epp_update_limit() and pass them up. If any errors occurred with CPPC API then amd-pstate won't be setup. Mario Limonciello (2): cpufreq/amd-pstate: Add an early param to disable MSR mode cpufreq/amd-pstate: Catch failures for amd_pstate_epp_update_limit() .../admin-guide/kernel-parameters.txt | 5 ++- Documentation/admin-guide/pm/amd-pstate.rst | 5 +++ drivers/cpufreq/amd-pstate.c | 43 +++++++++++++------ 3 files changed, 38 insertions(+), 15 deletions(-) -- 2.43.0 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/2] cpufreq/amd-pstate: Add an early param to disable MSR mode 2024-09-01 5:00 [PATCH 0/2] amd-pstate: Better handling for systems without an MSR Mario Limonciello @ 2024-09-01 5:00 ` Mario Limonciello 2024-09-03 13:14 ` Mario Limonciello 2024-09-01 5:00 ` [PATCH 2/2] cpufreq/amd-pstate: Catch failures for amd_pstate_epp_update_limit() Mario Limonciello 1 sibling, 1 reply; 5+ messages in thread From: Mario Limonciello @ 2024-09-01 5:00 UTC (permalink / raw) To: Gautham R . Shenoy, Perry Yuan Cc: open list:X86 ARCHITECTURE (32-BIT AND 64-BIT), open list:CPU FREQUENCY SCALING FRAMEWORK, Mario Limonciello From: Mario Limonciello <mario.limonciello@amd.com> This lets a system that supports the MSR run in shared memory mode instead to help replicate and debug issues. Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> --- .../admin-guide/kernel-parameters.txt | 5 +++ Documentation/admin-guide/pm/amd-pstate.rst | 5 +++ drivers/cpufreq/amd-pstate.c | 32 +++++++++++++------ 3 files changed, 32 insertions(+), 10 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 09126bb8cc9ff..041c609ed50ea 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -383,6 +383,11 @@ disable Disable amd-pstate preferred core. + amd_pstate_msr= + [X86] + disable + Disable amd-pstate CPPC MSR (force shared memory). + amijoy.map= [HW,JOY] Amiga joystick support Map of devices attached to JOY0DAT and JOY1DAT Format: <a>,<b> diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index d0324d44f5482..b06632556102e 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -411,6 +411,11 @@ For systems that support ``amd-pstate`` preferred core, the core rankings will always be advertised by the platform. But OS can choose to ignore that via the kernel parameter ``amd_prefcore=disable``. +``amd_pstate_msr=disable`` + +For systems that support a dedicated CPPC MSR, ignore it's use and run +with shared memory instead. + User Space Interface in ``sysfs`` - General =========================================== diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 93adde45bebce..89438a3654002 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -88,6 +88,7 @@ static struct cpufreq_driver amd_pstate_epp_driver; static int cppc_state = AMD_PSTATE_UNDEFINED; static bool cppc_enabled; static bool amd_pstate_prefcore = true; +static bool amd_pstate_msr = true; static struct quirk_entry *quirks; /* @@ -187,7 +188,7 @@ static s16 amd_pstate_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached) u64 epp; int ret; - if (cpu_feature_enabled(X86_FEATURE_CPPC)) { + if (amd_pstate_msr) { if (!cppc_req_cached) { epp = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &cppc_req_cached); @@ -260,7 +261,7 @@ static int amd_pstate_set_epp(struct amd_cpudata *cpudata, u32 epp) int ret; struct cppc_perf_ctrls perf_ctrls; - if (cpu_feature_enabled(X86_FEATURE_CPPC)) { + if (amd_pstate_msr) { u64 value = READ_ONCE(cpudata->cppc_req_cached); value &= ~GENMASK_ULL(31, 24); @@ -813,7 +814,7 @@ static int amd_pstate_get_highest_perf(int cpu, u32 *highest_perf) { int ret; - if (cpu_feature_enabled(X86_FEATURE_CPPC)) { + if (amd_pstate_msr) { u64 cap1; ret = rdmsrl_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1, &cap1); @@ -1058,7 +1059,7 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) /* It will be updated by governor */ policy->cur = policy->cpuinfo.min_freq; - if (cpu_feature_enabled(X86_FEATURE_CPPC)) + if (amd_pstate_msr) policy->fast_switch_possible = true; ret = freq_qos_add_request(&policy->constraints, &cpudata->req[0], @@ -1288,7 +1289,7 @@ static int amd_pstate_change_mode_without_dvr_change(int mode) cppc_state = mode; - if (cpu_feature_enabled(X86_FEATURE_CPPC) || cppc_state == AMD_PSTATE_ACTIVE) + if (amd_pstate_msr || cppc_state == AMD_PSTATE_ACTIVE) return 0; for_each_present_cpu(cpu) { @@ -1524,7 +1525,7 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) else policy->policy = CPUFREQ_POLICY_POWERSAVE; - if (cpu_feature_enabled(X86_FEATURE_CPPC)) { + if (amd_pstate_msr) { ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value); if (ret) return ret; @@ -1612,7 +1613,7 @@ static void amd_pstate_epp_update_limit(struct cpufreq_policy *policy) epp = 0; /* Set initial EPP value */ - if (cpu_feature_enabled(X86_FEATURE_CPPC)) { + if (amd_pstate_msr) { value &= ~GENMASK_ULL(31, 24); value |= (u64)epp << 24; } @@ -1657,7 +1658,7 @@ static void amd_pstate_epp_reenable(struct amd_cpudata *cpudata) value = READ_ONCE(cpudata->cppc_req_cached); max_perf = READ_ONCE(cpudata->highest_perf); - if (cpu_feature_enabled(X86_FEATURE_CPPC)) { + if (amd_pstate_msr) { wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); } else { perf_ctrls.max_perf = max_perf; @@ -1691,7 +1692,7 @@ static void amd_pstate_epp_offline(struct cpufreq_policy *policy) value = READ_ONCE(cpudata->cppc_req_cached); mutex_lock(&amd_pstate_limits_lock); - if (cpu_feature_enabled(X86_FEATURE_CPPC)) { + if (amd_pstate_msr) { cpudata->epp_policy = CPUFREQ_POLICY_UNKNOWN; /* Set max perf same as min perf */ @@ -1936,7 +1937,9 @@ static int __init amd_pstate_init(void) } /* capability check */ - if (cpu_feature_enabled(X86_FEATURE_CPPC)) { + if (amd_pstate_msr) + amd_pstate_msr = cpu_feature_enabled(X86_FEATURE_CPPC); + if (amd_pstate_msr) { pr_debug("AMD CPPC MSR based functionality is supported\n"); if (cppc_state != AMD_PSTATE_ACTIVE) current_pstate_driver->adjust_perf = amd_pstate_adjust_perf; @@ -2002,8 +2005,17 @@ static int __init amd_prefcore_param(char *str) return 0; } +static int __init amd_msr_param(char *str) +{ + if (!strcmp(str, "disable")) + amd_pstate_msr = false; + + return 0; +} + early_param("amd_pstate", amd_pstate_param); early_param("amd_prefcore", amd_prefcore_param); +early_param("amd_pstate_msr", amd_msr_param); MODULE_AUTHOR("Huang Rui <ray.huang@amd.com>"); MODULE_DESCRIPTION("AMD Processor P-state Frequency Driver"); -- 2.43.0 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] cpufreq/amd-pstate: Add an early param to disable MSR mode 2024-09-01 5:00 ` [PATCH 1/2] cpufreq/amd-pstate: Add an early param to disable MSR mode Mario Limonciello @ 2024-09-03 13:14 ` Mario Limonciello 0 siblings, 0 replies; 5+ messages in thread From: Mario Limonciello @ 2024-09-03 13:14 UTC (permalink / raw) To: Mario Limonciello, Gautham R . Shenoy, Perry Yuan Cc: open list:X86 ARCHITECTURE (32-BIT AND 64-BIT), open list:CPU FREQUENCY SCALING FRAMEWORK On 9/1/2024 00:00, Mario Limonciello wrote: > From: Mario Limonciello <mario.limonciello@amd.com> > > This lets a system that supports the MSR run in shared memory mode > instead to help replicate and debug issues. > > Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> After some offline discussion, will drop this patch. Second patch will remain and I will queue it up for -next. > --- > .../admin-guide/kernel-parameters.txt | 5 +++ > Documentation/admin-guide/pm/amd-pstate.rst | 5 +++ > drivers/cpufreq/amd-pstate.c | 32 +++++++++++++------ > 3 files changed, 32 insertions(+), 10 deletions(-) > > diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt > index 09126bb8cc9ff..041c609ed50ea 100644 > --- a/Documentation/admin-guide/kernel-parameters.txt > +++ b/Documentation/admin-guide/kernel-parameters.txt > @@ -383,6 +383,11 @@ > disable > Disable amd-pstate preferred core. > > + amd_pstate_msr= > + [X86] > + disable > + Disable amd-pstate CPPC MSR (force shared memory). > + > amijoy.map= [HW,JOY] Amiga joystick support > Map of devices attached to JOY0DAT and JOY1DAT > Format: <a>,<b> > diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst > index d0324d44f5482..b06632556102e 100644 > --- a/Documentation/admin-guide/pm/amd-pstate.rst > +++ b/Documentation/admin-guide/pm/amd-pstate.rst > @@ -411,6 +411,11 @@ For systems that support ``amd-pstate`` preferred core, the core rankings will > always be advertised by the platform. But OS can choose to ignore that via the > kernel parameter ``amd_prefcore=disable``. > > +``amd_pstate_msr=disable`` > + > +For systems that support a dedicated CPPC MSR, ignore it's use and run > +with shared memory instead. > + > User Space Interface in ``sysfs`` - General > =========================================== > > diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c > index 93adde45bebce..89438a3654002 100644 > --- a/drivers/cpufreq/amd-pstate.c > +++ b/drivers/cpufreq/amd-pstate.c > @@ -88,6 +88,7 @@ static struct cpufreq_driver amd_pstate_epp_driver; > static int cppc_state = AMD_PSTATE_UNDEFINED; > static bool cppc_enabled; > static bool amd_pstate_prefcore = true; > +static bool amd_pstate_msr = true; > static struct quirk_entry *quirks; > > /* > @@ -187,7 +188,7 @@ static s16 amd_pstate_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached) > u64 epp; > int ret; > > - if (cpu_feature_enabled(X86_FEATURE_CPPC)) { > + if (amd_pstate_msr) { > if (!cppc_req_cached) { > epp = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, > &cppc_req_cached); > @@ -260,7 +261,7 @@ static int amd_pstate_set_epp(struct amd_cpudata *cpudata, u32 epp) > int ret; > struct cppc_perf_ctrls perf_ctrls; > > - if (cpu_feature_enabled(X86_FEATURE_CPPC)) { > + if (amd_pstate_msr) { > u64 value = READ_ONCE(cpudata->cppc_req_cached); > > value &= ~GENMASK_ULL(31, 24); > @@ -813,7 +814,7 @@ static int amd_pstate_get_highest_perf(int cpu, u32 *highest_perf) > { > int ret; > > - if (cpu_feature_enabled(X86_FEATURE_CPPC)) { > + if (amd_pstate_msr) { > u64 cap1; > > ret = rdmsrl_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1, &cap1); > @@ -1058,7 +1059,7 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) > /* It will be updated by governor */ > policy->cur = policy->cpuinfo.min_freq; > > - if (cpu_feature_enabled(X86_FEATURE_CPPC)) > + if (amd_pstate_msr) > policy->fast_switch_possible = true; > > ret = freq_qos_add_request(&policy->constraints, &cpudata->req[0], > @@ -1288,7 +1289,7 @@ static int amd_pstate_change_mode_without_dvr_change(int mode) > > cppc_state = mode; > > - if (cpu_feature_enabled(X86_FEATURE_CPPC) || cppc_state == AMD_PSTATE_ACTIVE) > + if (amd_pstate_msr || cppc_state == AMD_PSTATE_ACTIVE) > return 0; > > for_each_present_cpu(cpu) { > @@ -1524,7 +1525,7 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) > else > policy->policy = CPUFREQ_POLICY_POWERSAVE; > > - if (cpu_feature_enabled(X86_FEATURE_CPPC)) { > + if (amd_pstate_msr) { > ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value); > if (ret) > return ret; > @@ -1612,7 +1613,7 @@ static void amd_pstate_epp_update_limit(struct cpufreq_policy *policy) > epp = 0; > > /* Set initial EPP value */ > - if (cpu_feature_enabled(X86_FEATURE_CPPC)) { > + if (amd_pstate_msr) { > value &= ~GENMASK_ULL(31, 24); > value |= (u64)epp << 24; > } > @@ -1657,7 +1658,7 @@ static void amd_pstate_epp_reenable(struct amd_cpudata *cpudata) > value = READ_ONCE(cpudata->cppc_req_cached); > max_perf = READ_ONCE(cpudata->highest_perf); > > - if (cpu_feature_enabled(X86_FEATURE_CPPC)) { > + if (amd_pstate_msr) { > wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); > } else { > perf_ctrls.max_perf = max_perf; > @@ -1691,7 +1692,7 @@ static void amd_pstate_epp_offline(struct cpufreq_policy *policy) > value = READ_ONCE(cpudata->cppc_req_cached); > > mutex_lock(&amd_pstate_limits_lock); > - if (cpu_feature_enabled(X86_FEATURE_CPPC)) { > + if (amd_pstate_msr) { > cpudata->epp_policy = CPUFREQ_POLICY_UNKNOWN; > > /* Set max perf same as min perf */ > @@ -1936,7 +1937,9 @@ static int __init amd_pstate_init(void) > } > > /* capability check */ > - if (cpu_feature_enabled(X86_FEATURE_CPPC)) { > + if (amd_pstate_msr) > + amd_pstate_msr = cpu_feature_enabled(X86_FEATURE_CPPC); > + if (amd_pstate_msr) { > pr_debug("AMD CPPC MSR based functionality is supported\n"); > if (cppc_state != AMD_PSTATE_ACTIVE) > current_pstate_driver->adjust_perf = amd_pstate_adjust_perf; > @@ -2002,8 +2005,17 @@ static int __init amd_prefcore_param(char *str) > return 0; > } > > +static int __init amd_msr_param(char *str) > +{ > + if (!strcmp(str, "disable")) > + amd_pstate_msr = false; > + > + return 0; > +} > + > early_param("amd_pstate", amd_pstate_param); > early_param("amd_prefcore", amd_prefcore_param); > +early_param("amd_pstate_msr", amd_msr_param); > > MODULE_AUTHOR("Huang Rui <ray.huang@amd.com>"); > MODULE_DESCRIPTION("AMD Processor P-state Frequency Driver"); ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 2/2] cpufreq/amd-pstate: Catch failures for amd_pstate_epp_update_limit() 2024-09-01 5:00 [PATCH 0/2] amd-pstate: Better handling for systems without an MSR Mario Limonciello 2024-09-01 5:00 ` [PATCH 1/2] cpufreq/amd-pstate: Add an early param to disable MSR mode Mario Limonciello @ 2024-09-01 5:00 ` Mario Limonciello 2024-09-02 9:24 ` Yuan, Perry 1 sibling, 1 reply; 5+ messages in thread From: Mario Limonciello @ 2024-09-01 5:00 UTC (permalink / raw) To: Gautham R . Shenoy, Perry Yuan Cc: open list:X86 ARCHITECTURE (32-BIT AND 64-BIT), open list:CPU FREQUENCY SCALING FRAMEWORK, Mario Limonciello From: Mario Limonciello <mario.limonciello@amd.com> amd_pstate_set_epp() calls cppc_set_epp_perf() which can fail for a variety of reasons but this is ignored. Change the return flow to allow failures. Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> --- drivers/cpufreq/amd-pstate.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 89438a3654002..b07be4d945e4d 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1556,7 +1556,7 @@ static void amd_pstate_epp_cpu_exit(struct cpufreq_policy *policy) pr_debug("CPU %d exiting\n", policy->cpu); } -static void amd_pstate_epp_update_limit(struct cpufreq_policy *policy) +static int amd_pstate_epp_update_limit(struct cpufreq_policy *policy) { struct amd_cpudata *cpudata = policy->driver_data; u32 max_perf, min_perf, min_limit_perf, max_limit_perf; @@ -1606,7 +1606,7 @@ static void amd_pstate_epp_update_limit(struct cpufreq_policy *policy) * This return value can only be negative for shared_memory * systems where EPP register read/write not supported. */ - return; + return epp; } if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) @@ -1619,12 +1619,13 @@ static void amd_pstate_epp_update_limit(struct cpufreq_policy *policy) } WRITE_ONCE(cpudata->cppc_req_cached, value); - amd_pstate_set_epp(cpudata, epp); + return amd_pstate_set_epp(cpudata, epp); } static int amd_pstate_epp_set_policy(struct cpufreq_policy *policy) { struct amd_cpudata *cpudata = policy->driver_data; + int ret; if (!policy->cpuinfo.max_freq) return -ENODEV; @@ -1634,7 +1635,9 @@ static int amd_pstate_epp_set_policy(struct cpufreq_policy *policy) cpudata->policy = policy->policy; - amd_pstate_epp_update_limit(policy); + ret = amd_pstate_epp_update_limit(policy); + if (ret) + return ret; /* * policy->cur is never updated with the amd_pstate_epp driver, but it -- 2.43.0 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* RE: [PATCH 2/2] cpufreq/amd-pstate: Catch failures for amd_pstate_epp_update_limit() 2024-09-01 5:00 ` [PATCH 2/2] cpufreq/amd-pstate: Catch failures for amd_pstate_epp_update_limit() Mario Limonciello @ 2024-09-02 9:24 ` Yuan, Perry 0 siblings, 0 replies; 5+ messages in thread From: Yuan, Perry @ 2024-09-02 9:24 UTC (permalink / raw) To: Mario Limonciello, Shenoy, Gautham Ranjal Cc: open list:X86 ARCHITECTURE (32-BIT AND 64-BIT), open list:CPU FREQUENCY SCALING FRAMEWORK, Limonciello, Mario [AMD Official Use Only - AMD Internal Distribution Only] > -----Original Message----- > From: Mario Limonciello <superm1@kernel.org> > Sent: Sunday, September 1, 2024 1:01 PM > To: Shenoy, Gautham Ranjal <gautham.shenoy@amd.com>; Yuan, Perry > <Perry.Yuan@amd.com> > Cc: open list:X86 ARCHITECTURE (32-BIT AND 64-BIT) <linux- > kernel@vger.kernel.org>; open list:CPU FREQUENCY SCALING FRAMEWORK > <linux-pm@vger.kernel.org>; Limonciello, Mario > <Mario.Limonciello@amd.com> > Subject: [PATCH 2/2] cpufreq/amd-pstate: Catch failures for > amd_pstate_epp_update_limit() > > From: Mario Limonciello <mario.limonciello@amd.com> > > amd_pstate_set_epp() calls cppc_set_epp_perf() which can fail for a variety of > reasons but this is ignored. Change the return flow to allow failures. > > Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> LGTM, Reviewed-by: Perry Yuan <perry.yuan@amd.com> > --- > drivers/cpufreq/amd-pstate.c | 11 +++++++---- > 1 file changed, 7 insertions(+), 4 deletions(-) > > diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c > index 89438a3654002..b07be4d945e4d 100644 > --- a/drivers/cpufreq/amd-pstate.c > +++ b/drivers/cpufreq/amd-pstate.c > @@ -1556,7 +1556,7 @@ static void amd_pstate_epp_cpu_exit(struct > cpufreq_policy *policy) > pr_debug("CPU %d exiting\n", policy->cpu); } > > -static void amd_pstate_epp_update_limit(struct cpufreq_policy *policy) > +static int amd_pstate_epp_update_limit(struct cpufreq_policy *policy) > { > struct amd_cpudata *cpudata = policy->driver_data; > u32 max_perf, min_perf, min_limit_perf, max_limit_perf; @@ -1606,7 > +1606,7 @@ static void amd_pstate_epp_update_limit(struct cpufreq_policy > *policy) > * This return value can only be negative for shared_memory > * systems where EPP register read/write not supported. > */ > - return; > + return epp; > } > > if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) @@ - > 1619,12 +1619,13 @@ static void amd_pstate_epp_update_limit(struct > cpufreq_policy *policy) > } > > WRITE_ONCE(cpudata->cppc_req_cached, value); > - amd_pstate_set_epp(cpudata, epp); > + return amd_pstate_set_epp(cpudata, epp); > } > > static int amd_pstate_epp_set_policy(struct cpufreq_policy *policy) { > struct amd_cpudata *cpudata = policy->driver_data; > + int ret; > > if (!policy->cpuinfo.max_freq) > return -ENODEV; > @@ -1634,7 +1635,9 @@ static int amd_pstate_epp_set_policy(struct > cpufreq_policy *policy) > > cpudata->policy = policy->policy; > > - amd_pstate_epp_update_limit(policy); > + ret = amd_pstate_epp_update_limit(policy); > + if (ret) > + return ret; > > /* > * policy->cur is never updated with the amd_pstate_epp driver, but it > -- > 2.43.0 ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2024-09-03 13:14 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-09-01 5:00 [PATCH 0/2] amd-pstate: Better handling for systems without an MSR Mario Limonciello 2024-09-01 5:00 ` [PATCH 1/2] cpufreq/amd-pstate: Add an early param to disable MSR mode Mario Limonciello 2024-09-03 13:14 ` Mario Limonciello 2024-09-01 5:00 ` [PATCH 2/2] cpufreq/amd-pstate: Catch failures for amd_pstate_epp_update_limit() Mario Limonciello 2024-09-02 9:24 ` Yuan, Perry
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).