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From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
Cc: linux-pci@vger.kernel.org, "Bjorn Helgaas" <bhelgaas@google.com>,
	"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Maciej W. Rozycki" <macro@orcam.me.uk>,
	"Lukas Wunner" <lukas@wunner.de>,
	"Alexandru Gagniuc" <mr.nuke.me@gmail.com>,
	"Krishna chaitanya chundru" <quic_krichai@quicinc.com>,
	"Srinivas Pandruvada" <srinivas.pandruvada@linux.intel.com>,
	"Rafael J. Wysocki" <rafael@kernel.org>,
	linux-pm@vger.kernel.org,
	"Smita Koralahalli" <Smita.KoralahalliChannabasappa@amd.com>,
	linux-kernel@vger.kernel.org,
	"Daniel Lezcano" <daniel.lezcano@linaro.org>,
	"Amit Kucheria" <amitk@kernel.org>,
	"Zhang Rui" <rui.zhang@intel.com>,
	"Christophe JAILLET" <christophe.jaillet@wanadoo.fr>
Subject: Re: [PATCH v8 2/8] PCI: Store all PCIe Supported Link Speeds
Date: Thu, 17 Oct 2024 11:25:11 +0100	[thread overview]
Message-ID: <20241017112511.0000503b@Huawei.com> (raw)
In-Reply-To: <20241009095223.7093-3-ilpo.jarvinen@linux.intel.com>

On Wed,  9 Oct 2024 12:52:17 +0300
Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> wrote:


> 
> supported_speeds field keeps the extra reserved zero at the least
> significant bit to match the Link Capabilities 2 Register layouting.
layout.

> 
> An attempt was made to store supported_speeds field into the struct
> pci_bus as an intersection of the both ends of the Link, however, the
> subordinate struct pci_bus is not available early enough. The Target
> Speed quirk (in pcie_failed_link_retrain()) can run either during
> initial scan or later requiring it to use the API PCIe bandwidth
> controller provides to set the Target Link Speed in order to co-exist
> with the bandwidth controller. When the Target Speed quirk is calling
> the bandwidth controller during initial scan, the struct pci_bus is not
> yet initialized. As such, storing supported_speeds into the struct
> pci_bus is not viable.

Excellent detailed description!

> 
> Suggested-by: Lukas Wunner <lukas@wunner.de>
> Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
One trivial request inline.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

> ---
>  drivers/pci/pci.c             | 58 ++++++++++++++++++++++++-----------
>  drivers/pci/probe.c           |  3 ++
>  include/linux/pci.h           | 11 ++++++-
>  include/uapi/linux/pci_regs.h |  1 +
>  4 files changed, 54 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index 7d85c04fbba2..b28ab4761b18 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c

> -enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
> +u8 pcie_get_supported_speeds(struct pci_dev *dev)
>  {
>  	u32 lnkcap2, lnkcap;
> +	u8 speeds;
>  
> -	/*
> -	 * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18.  The
> -	 * implementation note there recommends using the Supported Link
> -	 * Speeds Vector in Link Capabilities 2 when supported.
> -	 *
> -	 * Without Link Capabilities 2, i.e., prior to PCIe r3.0, software
> -	 * should use the Supported Link Speeds field in Link Capabilities,
> -	 * where only 2.5 GT/s and 5.0 GT/s speeds were defined.
> -	 */
>  	pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
> +	speeds = lnkcap2 & PCI_EXP_LNKCAP2_SLS;

I'd be tempted to leave a breadcrumb here in the form of a comment
to stop the obviously 'correct' but totally wrong FIELD_GET()
being used to replace this because of that LSB 0.
You have it well commented elsewhere but anyone editing this
code might not look at where it is written to.

(I'd written that feedback before realizing my error ;)
>  


  reply	other threads:[~2024-10-17 10:25 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-09  9:52 [PATCH v8 0/8] PCI: Add PCIe bandwidth controller Ilpo Järvinen
2024-10-09  9:52 ` [PATCH v8 1/8] PCI: Protect Link Control 2 Register with RMW locking Ilpo Järvinen
2024-10-17 10:12   ` Jonathan Cameron
2024-10-17 10:30     ` Ilpo Järvinen
2024-10-09  9:52 ` [PATCH v8 2/8] PCI: Store all PCIe Supported Link Speeds Ilpo Järvinen
2024-10-17 10:25   ` Jonathan Cameron [this message]
2024-10-09  9:52 ` [PATCH v8 3/8] PCI: Refactor pcie_update_link_speed() Ilpo Järvinen
2024-10-17 10:26   ` Jonathan Cameron
2024-10-09  9:52 ` [PATCH v8 4/8] PCI/quirks: Abstract LBMS seen check into own function Ilpo Järvinen
2024-10-17 10:29   ` Jonathan Cameron
2024-10-09  9:52 ` [PATCH v8 5/8] PCI/bwctrl: Re-add BW notification portdrv as PCIe BW controller Ilpo Järvinen
2024-10-17 10:48   ` Jonathan Cameron
2024-10-09  9:52 ` [PATCH v8 6/8] PCI/bwctrl: Add API to set PCIe Link Speed Ilpo Järvinen
2024-10-17 11:02   ` Jonathan Cameron
2024-10-17 13:16     ` Ilpo Järvinen
2024-10-09  9:52 ` [PATCH v8 7/8] thermal: Add PCIe cooling driver Ilpo Järvinen
2024-10-17 11:04   ` Jonathan Cameron
2024-10-17 12:16     ` Ilpo Järvinen
2024-10-17 12:58       ` Rafael J. Wysocki
2024-10-17 13:02         ` Ilpo Järvinen
2024-10-17 13:28           ` Jonathan Cameron
2024-10-09  9:52 ` [PATCH v8 8/8] selftests/pcie_bwctrl: Create selftests Ilpo Järvinen
2024-10-17 11:08   ` Jonathan Cameron

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