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From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
Cc: "Rafael J. Wysocki" <rafael@kernel.org>,
	linux-pci@vger.kernel.org, "Bjorn Helgaas" <bhelgaas@google.com>,
	"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Maciej W. Rozycki" <macro@orcam.me.uk>,
	"Lukas Wunner" <lukas@wunner.de>,
	"Alexandru Gagniuc" <mr.nuke.me@gmail.com>,
	"Krishna chaitanya chundru" <quic_krichai@quicinc.com>,
	"Srinivas Pandruvada" <srinivas.pandruvada@linux.intel.com>,
	linux-pm@vger.kernel.org,
	"Smita Koralahalli" <Smita.KoralahalliChannabasappa@amd.com>,
	"Daniel Lezcano" <daniel.lezcano@linaro.org>,
	"Zhang Rui" <rui.zhang@intel.com>,
	"Lukasz Luba" <lukasz.luba@arm.com>,
	LKML <linux-kernel@vger.kernel.org>,
	"Amit Kucheria" <amitk@kernel.org>,
	"Christophe JAILLET" <christophe.jaillet@wanadoo.fr>
Subject: Re: [PATCH v8 7/8] thermal: Add PCIe cooling driver
Date: Thu, 17 Oct 2024 14:28:08 +0100	[thread overview]
Message-ID: <20241017142808.00002753@Huawei.com> (raw)
In-Reply-To: <47da33ac-4959-b30e-5ca6-52d30650b353@linux.intel.com>

On Thu, 17 Oct 2024 16:02:34 +0300 (EEST)
Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> wrote:

> On Thu, 17 Oct 2024, Rafael J. Wysocki wrote:
> 
> > On Thu, Oct 17, 2024 at 2:16 PM Ilpo Järvinen
> > <ilpo.jarvinen@linux.intel.com> wrote:  
> > >
> > > On Thu, 17 Oct 2024, Jonathan Cameron wrote:
> > >  
> > > > On Wed,  9 Oct 2024 12:52:22 +0300
> > > > Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> wrote:
> > > >  
> > > > > Add a thermal cooling driver to provide path to access PCIe bandwidth
> > > > > controller using the usual thermal interfaces.
> > > > >
> > > > > A cooling device is instantiated for controllable PCIe Ports from the
> > > > > bwctrl service driver.
> > > > >
> > > > > If registering the cooling device fails, allow bwctrl's probe to
> > > > > succeed regardless. As cdev in that case contains IS_ERR() pseudo
> > > > > "pointer", clean that up inside the probe function so the remove side
> > > > > doesn't need to suddenly make an odd looking IS_ERR() check.
> > > > >
> > > > > The thermal side state 0 means no throttling, i.e., maximum supported
> > > > > PCIe Link Speed.
> > > > >
> > > > > Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
> > > > > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > > > > Acked-by: Rafael J. Wysocki <rafael@kernel.org> # From the cooling device interface perspective  
> > > >
> > > > Trivial thing noticed on a reread.
> > > >
> > > >  
> > > > > diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
> > > > > index 61e7ae524b1f..d3f9686e26e7 100644
> > > > > --- a/drivers/thermal/Kconfig
> > > > > +++ b/drivers/thermal/Kconfig
> > > > > @@ -220,6 +220,15 @@ config DEVFREQ_THERMAL
> > > > >
> > > > >       If you want this support, you should say Y here.
> > > > >
> > > > > +config PCIE_THERMAL
> > > > > +   bool "PCIe cooling support"
> > > > > +   depends on PCIEPORTBUS
> > > > > +   help
> > > > > +     This implements PCIe cooling mechanism through bandwidth reduction
> > > > > +     for PCIe devices.  
> > > >
> > > > Technically links not devices, but don't think that matters much  
> > >
> > > That distinction would be splitting hairs beyond what seems useful from
> > > ordinary user's point of view. If there's no device attached, BW
> > > controller cannot do anything since the link is not going to train.
> > > The link speed reduction is going to impact the speed the device
> > > can communicate with even if it technically occurs on the link.  
> > 
> > From the Kconfig description perspective I think it's better to say
> > "devices" even though technically it is about links, because device
> > performance is what users will measure and notice any changes of.  
> 
> Yes, that's what I tried to explain above. I intend to keep it as 
> "devices" for this very reason.
> 
Fine by me to keep it as things stand. Been reading too many specs
recently so my immediate thought was why is there a bandwidth control
for the engines / memory in the EP :)

Jonathan


  reply	other threads:[~2024-10-17 13:28 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-09  9:52 [PATCH v8 0/8] PCI: Add PCIe bandwidth controller Ilpo Järvinen
2024-10-09  9:52 ` [PATCH v8 1/8] PCI: Protect Link Control 2 Register with RMW locking Ilpo Järvinen
2024-10-17 10:12   ` Jonathan Cameron
2024-10-17 10:30     ` Ilpo Järvinen
2024-10-09  9:52 ` [PATCH v8 2/8] PCI: Store all PCIe Supported Link Speeds Ilpo Järvinen
2024-10-17 10:25   ` Jonathan Cameron
2024-10-09  9:52 ` [PATCH v8 3/8] PCI: Refactor pcie_update_link_speed() Ilpo Järvinen
2024-10-17 10:26   ` Jonathan Cameron
2024-10-09  9:52 ` [PATCH v8 4/8] PCI/quirks: Abstract LBMS seen check into own function Ilpo Järvinen
2024-10-17 10:29   ` Jonathan Cameron
2024-10-09  9:52 ` [PATCH v8 5/8] PCI/bwctrl: Re-add BW notification portdrv as PCIe BW controller Ilpo Järvinen
2024-10-17 10:48   ` Jonathan Cameron
2024-10-09  9:52 ` [PATCH v8 6/8] PCI/bwctrl: Add API to set PCIe Link Speed Ilpo Järvinen
2024-10-17 11:02   ` Jonathan Cameron
2024-10-17 13:16     ` Ilpo Järvinen
2024-10-09  9:52 ` [PATCH v8 7/8] thermal: Add PCIe cooling driver Ilpo Järvinen
2024-10-17 11:04   ` Jonathan Cameron
2024-10-17 12:16     ` Ilpo Järvinen
2024-10-17 12:58       ` Rafael J. Wysocki
2024-10-17 13:02         ` Ilpo Järvinen
2024-10-17 13:28           ` Jonathan Cameron [this message]
2024-10-09  9:52 ` [PATCH v8 8/8] selftests/pcie_bwctrl: Create selftests Ilpo Järvinen
2024-10-17 11:08   ` Jonathan Cameron

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