From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: linux-pci@vger.kernel.org, "Bjorn Helgaas" <bhelgaas@google.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Maciej W . Rozycki" <macro@orcam.me.uk>,
"Jonathan Cameron" <Jonathan.Cameron@Huawei.com>,
"Lukas Wunner" <lukas@wunner.de>,
"Alexandru Gagniuc" <mr.nuke.me@gmail.com>,
"Krishna chaitanya chundru" <quic_krichai@quicinc.com>,
"Srinivas Pandruvada" <srinivas.pandruvada@linux.intel.com>,
"Rafael J . Wysocki" <rafael@kernel.org>,
linux-pm@vger.kernel.org,
"Smita Koralahalli" <Smita.KoralahalliChannabasappa@amd.com>,
"Jonathan Corbet" <corbet@lwn.net>,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: "Daniel Lezcano" <daniel.lezcano@linaro.org>,
"Amit Kucheria" <amitk@kernel.org>,
"Zhang Rui" <rui.zhang@intel.com>,
"Christophe JAILLET" <christophe.jaillet@wanadoo.fr>,
"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
"Jonathan Cameron" <Jonathan.Cameron@huawei.com>
Subject: [PATCH v9 1/9] Documentation PCI: Reformat RMW ops documentation
Date: Fri, 18 Oct 2024 17:47:47 +0300 [thread overview]
Message-ID: <20241018144755.7875-2-ilpo.jarvinen@linux.intel.com> (raw)
In-Reply-To: <20241018144755.7875-1-ilpo.jarvinen@linux.intel.com>
Extract the list of RMW protected PCIe Capability registers into a
bullet list to make them easier to pick up on a glance. An upcoming
change is going to add one more register among them so it will be much
cleaner to have them as bullets.
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Reviewed-by: Lukas Wunner <lukas@wunner.de>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
Documentation/PCI/pciebus-howto.rst | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/Documentation/PCI/pciebus-howto.rst b/Documentation/PCI/pciebus-howto.rst
index f344452651e1..e48d01422efc 100644
--- a/Documentation/PCI/pciebus-howto.rst
+++ b/Documentation/PCI/pciebus-howto.rst
@@ -217,8 +217,11 @@ capability structure except the PCI Express capability structure,
that is shared between many drivers including the service drivers.
RMW Capability accessors (pcie_capability_clear_and_set_word(),
pcie_capability_set_word(), and pcie_capability_clear_word()) protect
-a selected set of PCI Express Capability Registers (Link Control
-Register and Root Control Register). Any change to those registers
-should be performed using RMW accessors to avoid problems due to
-concurrent updates. For the up-to-date list of protected registers,
-see pcie_capability_clear_and_set_word().
+a selected set of PCI Express Capability Registers:
+
+* Link Control Register
+* Root Control Register
+
+Any change to those registers should be performed using RMW accessors to
+avoid problems due to concurrent updates. For the up-to-date list of
+protected registers, see pcie_capability_clear_and_set_word().
--
2.39.5
next prev parent reply other threads:[~2024-10-18 14:48 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-18 14:47 [PATCH v9 0/9] PCI: Add PCIe bandwidth controller Ilpo Järvinen
2024-10-18 14:47 ` Ilpo Järvinen [this message]
2024-10-18 14:47 ` [PATCH v9 2/9] PCI: Protect Link Control 2 Register with RMW locking Ilpo Järvinen
2024-10-18 14:47 ` [PATCH v9 3/9] PCI: Store all PCIe Supported Link Speeds Ilpo Järvinen
2024-11-11 13:23 ` Lukas Wunner
2024-11-11 20:30 ` Bjorn Helgaas
2024-11-12 9:20 ` Ilpo Järvinen
2024-10-18 14:47 ` [PATCH v9 4/9] PCI: Refactor pcie_update_link_speed() Ilpo Järvinen
2024-10-18 14:47 ` [PATCH v9 5/9] PCI/quirks: Abstract LBMS seen check into own function Ilpo Järvinen
2024-10-18 14:47 ` [PATCH v9 6/9] PCI/bwctrl: Re-add BW notification portdrv as PCIe BW controller Ilpo Järvinen
2024-12-06 18:12 ` Niklas Schnelle
2024-12-06 19:31 ` Niklas Schnelle
2024-12-06 20:07 ` Niklas Schnelle
2024-12-06 23:06 ` Niklas Schnelle
2024-12-07 16:31 ` Lukas Wunner
2024-12-07 18:18 ` Niklas Schnelle
2025-01-02 21:30 ` Lukas Wunner
2024-10-18 14:47 ` [PATCH v9 7/9] PCI/bwctrl: Add API to set PCIe Link Speed Ilpo Järvinen
2024-11-12 15:47 ` Lukas Wunner
2024-11-12 16:01 ` Ilpo Järvinen
2024-11-18 13:03 ` Jonathan Cameron
2024-11-18 13:17 ` Ilpo Järvinen
2024-11-20 15:36 ` Jonathan Cameron
2024-11-12 20:43 ` Bjorn Helgaas
2025-01-02 10:38 ` Lukas Wunner
2025-01-05 16:43 ` Ilpo Järvinen
2024-10-18 14:47 ` [PATCH v9 8/9] thermal: Add PCIe cooling driver Ilpo Järvinen
2024-11-13 8:44 ` Lukas Wunner
2024-11-15 17:28 ` Bjorn Helgaas
2024-10-18 14:47 ` [PATCH v9 9/9] selftests/pcie_bwctrl: Create selftests Ilpo Järvinen
2024-10-23 22:19 ` [PATCH v9 0/9] PCI: Add PCIe bandwidth controller Bjorn Helgaas
2024-11-13 21:48 ` Bjorn Helgaas
2024-11-14 8:46 ` Bartosz Golaszewski
2024-11-14 12:32 ` Ilpo Järvinen
2024-11-14 17:36 ` Krzysztof Wilczyński
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20241018144755.7875-2-ilpo.jarvinen@linux.intel.com \
--to=ilpo.jarvinen@linux.intel.com \
--cc=Jonathan.Cameron@Huawei.com \
--cc=Smita.KoralahalliChannabasappa@amd.com \
--cc=amitk@kernel.org \
--cc=bhelgaas@google.com \
--cc=christophe.jaillet@wanadoo.fr \
--cc=corbet@lwn.net \
--cc=daniel.lezcano@linaro.org \
--cc=kw@linux.com \
--cc=linux-doc@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-pm@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=lukas@wunner.de \
--cc=macro@orcam.me.uk \
--cc=mr.nuke.me@gmail.com \
--cc=quic_krichai@quicinc.com \
--cc=rafael@kernel.org \
--cc=robh@kernel.org \
--cc=rui.zhang@intel.com \
--cc=srinivas.pandruvada@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).