From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: linux-pci@vger.kernel.org, "Bjorn Helgaas" <bhelgaas@google.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Maciej W . Rozycki" <macro@orcam.me.uk>,
"Jonathan Cameron" <Jonathan.Cameron@Huawei.com>,
"Lukas Wunner" <lukas@wunner.de>,
"Alexandru Gagniuc" <mr.nuke.me@gmail.com>,
"Krishna chaitanya chundru" <quic_krichai@quicinc.com>,
"Srinivas Pandruvada" <srinivas.pandruvada@linux.intel.com>,
"Rafael J . Wysocki" <rafael@kernel.org>,
linux-pm@vger.kernel.org,
"Smita Koralahalli" <Smita.KoralahalliChannabasappa@amd.com>,
linux-kernel@vger.kernel.org
Cc: "Daniel Lezcano" <daniel.lezcano@linaro.org>,
"Amit Kucheria" <amitk@kernel.org>,
"Zhang Rui" <rui.zhang@intel.com>,
"Christophe JAILLET" <christophe.jaillet@wanadoo.fr>,
"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
"Jonathan Cameron" <Jonathan.Cameron@huawei.com>
Subject: [PATCH v9 4/9] PCI: Refactor pcie_update_link_speed()
Date: Fri, 18 Oct 2024 17:47:50 +0300 [thread overview]
Message-ID: <20241018144755.7875-5-ilpo.jarvinen@linux.intel.com> (raw)
In-Reply-To: <20241018144755.7875-1-ilpo.jarvinen@linux.intel.com>
pcie_update_link_speed() is passed the Link Status register but not all
callers have that value at hand nor need the value.
Refactor pcie_update_link_speed() to include reading the Link Status
register and create __pcie_update_link_speed() which can be used by the
hotplug code that has the register value at hand beforehand (and needs
the value for other purposes).
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
drivers/pci/hotplug/pciehp_hpc.c | 2 +-
drivers/pci/pci.h | 7 ++++++-
drivers/pci/probe.c | 12 +++++++-----
3 files changed, 14 insertions(+), 7 deletions(-)
diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c
index 736ad8baa2a5..bb5a8d9f03ad 100644
--- a/drivers/pci/hotplug/pciehp_hpc.c
+++ b/drivers/pci/hotplug/pciehp_hpc.c
@@ -319,7 +319,7 @@ int pciehp_check_link_status(struct controller *ctrl)
return -1;
}
- pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
+ __pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
if (!found) {
ctrl_info(ctrl, "Slot(%s): No device found\n",
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 14d00ce45bfa..6e827d47aa85 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -378,7 +378,12 @@ enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
void pcie_report_downtraining(struct pci_dev *dev);
-void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
+
+static inline void __pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
+{
+ bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
+}
+void pcie_update_link_speed(struct pci_bus *bus);
/* Single Root I/O Virtualization */
struct pci_sriov {
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index af153a8e8225..c138daf78961 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -742,9 +742,13 @@ const char *pci_speed_string(enum pci_bus_speed speed)
}
EXPORT_SYMBOL_GPL(pci_speed_string);
-void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
+void pcie_update_link_speed(struct pci_bus *bus)
{
- bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
+ struct pci_dev *bridge = bus->self;
+ u16 linksta;
+
+ pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
+ __pcie_update_link_speed(bus, linksta);
}
EXPORT_SYMBOL_GPL(pcie_update_link_speed);
@@ -827,13 +831,11 @@ static void pci_set_bus_speed(struct pci_bus *bus)
if (pci_is_pcie(bridge)) {
u32 linkcap;
- u16 linksta;
pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
- pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
- pcie_update_link_speed(bus, linksta);
+ pcie_update_link_speed(bus);
}
}
--
2.39.5
next prev parent reply other threads:[~2024-10-18 14:49 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-18 14:47 [PATCH v9 0/9] PCI: Add PCIe bandwidth controller Ilpo Järvinen
2024-10-18 14:47 ` [PATCH v9 1/9] Documentation PCI: Reformat RMW ops documentation Ilpo Järvinen
2024-10-18 14:47 ` [PATCH v9 2/9] PCI: Protect Link Control 2 Register with RMW locking Ilpo Järvinen
2024-10-18 14:47 ` [PATCH v9 3/9] PCI: Store all PCIe Supported Link Speeds Ilpo Järvinen
2024-11-11 13:23 ` Lukas Wunner
2024-11-11 20:30 ` Bjorn Helgaas
2024-11-12 9:20 ` Ilpo Järvinen
2024-10-18 14:47 ` Ilpo Järvinen [this message]
2024-10-18 14:47 ` [PATCH v9 5/9] PCI/quirks: Abstract LBMS seen check into own function Ilpo Järvinen
2024-10-18 14:47 ` [PATCH v9 6/9] PCI/bwctrl: Re-add BW notification portdrv as PCIe BW controller Ilpo Järvinen
2024-12-06 18:12 ` Niklas Schnelle
2024-12-06 19:31 ` Niklas Schnelle
2024-12-06 20:07 ` Niklas Schnelle
2024-12-06 23:06 ` Niklas Schnelle
2024-12-07 16:31 ` Lukas Wunner
2024-12-07 18:18 ` Niklas Schnelle
2025-01-02 21:30 ` Lukas Wunner
2024-10-18 14:47 ` [PATCH v9 7/9] PCI/bwctrl: Add API to set PCIe Link Speed Ilpo Järvinen
2024-11-12 15:47 ` Lukas Wunner
2024-11-12 16:01 ` Ilpo Järvinen
2024-11-18 13:03 ` Jonathan Cameron
2024-11-18 13:17 ` Ilpo Järvinen
2024-11-20 15:36 ` Jonathan Cameron
2024-11-12 20:43 ` Bjorn Helgaas
2025-01-02 10:38 ` Lukas Wunner
2025-01-05 16:43 ` Ilpo Järvinen
2024-10-18 14:47 ` [PATCH v9 8/9] thermal: Add PCIe cooling driver Ilpo Järvinen
2024-11-13 8:44 ` Lukas Wunner
2024-11-15 17:28 ` Bjorn Helgaas
2024-10-18 14:47 ` [PATCH v9 9/9] selftests/pcie_bwctrl: Create selftests Ilpo Järvinen
2024-10-23 22:19 ` [PATCH v9 0/9] PCI: Add PCIe bandwidth controller Bjorn Helgaas
2024-11-13 21:48 ` Bjorn Helgaas
2024-11-14 8:46 ` Bartosz Golaszewski
2024-11-14 12:32 ` Ilpo Järvinen
2024-11-14 17:36 ` Krzysztof Wilczyński
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