From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B07A21A08AF; Tue, 3 Jun 2025 13:20:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748956845; cv=none; b=hR6XDoWy1aX5rjm2ruwRVZPAVIkRkOHdI3grkjWxxL1G9LFndK7qlWMpON7COcNBj9iuzkHXGGD0RSYDY9nDPgB4Jaj/yWdfuBTwdua6lI6Rv2/6XKALPfNykFjdwcIL+8gW3CgK8NOB/iNpjrasRxHpuDATW3SeiXWjUhuKEYc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748956845; c=relaxed/simple; bh=RLET0vNHW12fPEu2WD0/7IfHIEMQvJ29hvwt3raNVWc=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=VzzRqfHeIWkTpaMXlWDMRmXWnqfR+u8T6P4Rr5K137/u7+Ly6GjnuNBh1gm3SGGwzUlHTK/dL0Qs+EQmEE9aVcvAfJ+sfDUylXcjbe+NJyQI7dohd72a6/kMNbE7XHUaV24gvXbwXtPyhOFjeb8scW+DKlbmWwDVbprADT/E1oo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=T0ReAnAt; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="T0ReAnAt" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 62F34C4CEED; Tue, 3 Jun 2025 13:20:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1748956844; bh=RLET0vNHW12fPEu2WD0/7IfHIEMQvJ29hvwt3raNVWc=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=T0ReAnAt9ELewq8mhN1MKu8QAhUBd75lgYpwe/y0CJrqDw6NT+FXDbtF9D5Urf8+R cekywChSI4uLND1SK0Bn5LKBsmUdSS4y9xooQ7sbIx3t2UFvuhYAetxGCfRiWyarSw lpxtLwTHqkGlISZNDoK76o5Vyma7W6+nyM83Oc/lw55lo8umALKXhAERYZ6daDB54F idE2D7diFj8XpVZD1B8ScJiRh/wByJt2+wAFDq9xdFPySNqJzdiycQs17Z+3URIQus HxbKBuAXer5DK+Psal5gAlH0jurXXkKKNylzOyRRnplJRWgdg27xzMHqt69B0Mfwzd GMuFGku2QmpwQ== Date: Tue, 3 Jun 2025 15:20:36 +0200 From: Krzysztof Kozlowski To: Michal Wilczynski Cc: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Matt Coster , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org Subject: Re: [PATCH v3 5/8] riscv: dts: thead: th1520: Add missing reset controller header include Message-ID: <20250603-tactful-valiant-mackerel-bfb6be@kuoka> References: <20250530-apr_14_for_sending-v3-0-83d5744d997c@samsung.com> <20250530-apr_14_for_sending-v3-5-83d5744d997c@samsung.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20250530-apr_14_for_sending-v3-5-83d5744d997c@samsung.com> On Fri, May 30, 2025 at 12:23:52AM GMT, Michal Wilczynski wrote: > TH1520_RESET_ID_GPU_CLKGEN and TH1520_RESET_ID_GPU are required for GPU > power sequencing to work. To make these symbols available, add the > necessary include for the T-HEAD TH1520 reset controller bindings. How would it compile/build without it? If there are no users, then do not add unused header just to add it. Best regards, Krzysztof