* [PATCH v2 1/5] soc: tegra: fuse: add Tegra114 nvmem cells and fuse lookups
2025-07-14 8:22 [PATCH v2 0/5] thermal: tegra: add SOCTHERM support for Tegra114 Svyatoslav Ryhel
@ 2025-07-14 8:22 ` Svyatoslav Ryhel
2025-07-14 8:22 ` [PATCH v2 2/5] dt-bindings: thermal: Document Tegra114 SOCTHERM Thermal Management System Svyatoslav Ryhel
` (3 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Svyatoslav Ryhel @ 2025-07-14 8:22 UTC (permalink / raw)
To: Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Thierry Reding, Thierry Reding, Jonathan Hunter, Svyatoslav Ryhel
Cc: linux-pm, devicetree, linux-tegra, linux-kernel
Add missing Tegra114 nvmem cells and fuse lookups which were added for
Tegra124+ but omitted for Tegra114.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
drivers/soc/tegra/fuse/fuse-tegra30.c | 122 ++++++++++++++++++++++++++
1 file changed, 122 insertions(+)
diff --git a/drivers/soc/tegra/fuse/fuse-tegra30.c b/drivers/soc/tegra/fuse/fuse-tegra30.c
index e24ab5f7d2bf..524fa1b0cd3d 100644
--- a/drivers/soc/tegra/fuse/fuse-tegra30.c
+++ b/drivers/soc/tegra/fuse/fuse-tegra30.c
@@ -117,6 +117,124 @@ const struct tegra_fuse_soc tegra30_fuse_soc = {
#endif
#ifdef CONFIG_ARCH_TEGRA_114_SOC
+static const struct nvmem_cell_info tegra114_fuse_cells[] = {
+ {
+ .name = "tsensor-cpu1",
+ .offset = 0x084,
+ .bytes = 4,
+ .bit_offset = 0,
+ .nbits = 32,
+ }, {
+ .name = "tsensor-cpu2",
+ .offset = 0x088,
+ .bytes = 4,
+ .bit_offset = 0,
+ .nbits = 32,
+ }, {
+ .name = "tsensor-common",
+ .offset = 0x08c,
+ .bytes = 4,
+ .bit_offset = 0,
+ .nbits = 32,
+ }, {
+ .name = "tsensor-cpu0",
+ .offset = 0x098,
+ .bytes = 4,
+ .bit_offset = 0,
+ .nbits = 32,
+ }, {
+ .name = "xusb-pad-calibration",
+ .offset = 0x0f0,
+ .bytes = 4,
+ .bit_offset = 0,
+ .nbits = 32,
+ }, {
+ .name = "tsensor-cpu3",
+ .offset = 0x12c,
+ .bytes = 4,
+ .bit_offset = 0,
+ .nbits = 32,
+ }, {
+ .name = "tsensor-gpu",
+ .offset = 0x154,
+ .bytes = 4,
+ .bit_offset = 0,
+ .nbits = 32,
+ }, {
+ .name = "tsensor-mem0",
+ .offset = 0x158,
+ .bytes = 4,
+ .bit_offset = 0,
+ .nbits = 32,
+ }, {
+ .name = "tsensor-mem1",
+ .offset = 0x15c,
+ .bytes = 4,
+ .bit_offset = 0,
+ .nbits = 32,
+ }, {
+ .name = "tsensor-pllx",
+ .offset = 0x160,
+ .bytes = 4,
+ .bit_offset = 0,
+ .nbits = 32,
+ },
+};
+
+static const struct nvmem_cell_lookup tegra114_fuse_lookups[] = {
+ {
+ .nvmem_name = "fuse",
+ .cell_name = "xusb-pad-calibration",
+ .dev_id = "7009f000.padctl",
+ .con_id = "calibration",
+ }, {
+ .nvmem_name = "fuse",
+ .cell_name = "tsensor-common",
+ .dev_id = "700e2000.thermal-sensor",
+ .con_id = "common",
+ }, {
+ .nvmem_name = "fuse",
+ .cell_name = "tsensor-cpu0",
+ .dev_id = "700e2000.thermal-sensor",
+ .con_id = "cpu0",
+ }, {
+ .nvmem_name = "fuse",
+ .cell_name = "tsensor-cpu1",
+ .dev_id = "700e2000.thermal-sensor",
+ .con_id = "cpu1",
+ }, {
+ .nvmem_name = "fuse",
+ .cell_name = "tsensor-cpu2",
+ .dev_id = "700e2000.thermal-sensor",
+ .con_id = "cpu2",
+ }, {
+ .nvmem_name = "fuse",
+ .cell_name = "tsensor-cpu3",
+ .dev_id = "700e2000.thermal-sensor",
+ .con_id = "cpu3",
+ }, {
+ .nvmem_name = "fuse",
+ .cell_name = "tsensor-mem0",
+ .dev_id = "700e2000.thermal-sensor",
+ .con_id = "mem0",
+ }, {
+ .nvmem_name = "fuse",
+ .cell_name = "tsensor-mem1",
+ .dev_id = "700e2000.thermal-sensor",
+ .con_id = "mem1",
+ }, {
+ .nvmem_name = "fuse",
+ .cell_name = "tsensor-gpu",
+ .dev_id = "700e2000.thermal-sensor",
+ .con_id = "gpu",
+ }, {
+ .nvmem_name = "fuse",
+ .cell_name = "tsensor-pllx",
+ .dev_id = "700e2000.thermal-sensor",
+ .con_id = "pllx",
+ },
+};
+
static const struct tegra_fuse_info tegra114_fuse_info = {
.read = tegra30_fuse_read,
.size = 0x2a0,
@@ -127,6 +245,10 @@ const struct tegra_fuse_soc tegra114_fuse_soc = {
.init = tegra30_fuse_init,
.speedo_init = tegra114_init_speedo_data,
.info = &tegra114_fuse_info,
+ .lookups = tegra114_fuse_lookups,
+ .num_lookups = ARRAY_SIZE(tegra114_fuse_lookups),
+ .cells = tegra114_fuse_cells,
+ .num_cells = ARRAY_SIZE(tegra114_fuse_cells),
.soc_attr_group = &tegra_soc_attr_group,
.clk_suspend_on = false,
};
--
2.48.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v2 2/5] dt-bindings: thermal: Document Tegra114 SOCTHERM Thermal Management System
2025-07-14 8:22 [PATCH v2 0/5] thermal: tegra: add SOCTHERM support for Tegra114 Svyatoslav Ryhel
2025-07-14 8:22 ` [PATCH v2 1/5] soc: tegra: fuse: add Tegra114 nvmem cells and fuse lookups Svyatoslav Ryhel
@ 2025-07-14 8:22 ` Svyatoslav Ryhel
2025-07-14 8:22 ` [PATCH v2 3/5] thermal: tegra: soctherm-fuse: parametrize configuration further Svyatoslav Ryhel
` (2 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Svyatoslav Ryhel @ 2025-07-14 8:22 UTC (permalink / raw)
To: Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Thierry Reding, Thierry Reding, Jonathan Hunter, Svyatoslav Ryhel
Cc: linux-pm, devicetree, linux-tegra, linux-kernel
Document SOCTHERM Thermal Management System found in the Tegra 4 SoC.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
---
.../devicetree/bindings/thermal/nvidia,tegra124-soctherm.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.yaml b/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.yaml
index 19bb1f324183..2fd493fcca63 100644
--- a/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.yaml
+++ b/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.yaml
@@ -18,6 +18,7 @@ description: The SOCTHERM IP block contains thermal sensors, support for
properties:
compatible:
enum:
+ - nvidia,tegra114-soctherm
- nvidia,tegra124-soctherm
- nvidia,tegra132-soctherm
- nvidia,tegra210-soctherm
@@ -205,6 +206,7 @@ allOf:
compatible:
contains:
enum:
+ - nvidia,tegra114-soctherm
- nvidia,tegra124-soctherm
- nvidia,tegra210-soctherm
then:
--
2.48.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v2 3/5] thermal: tegra: soctherm-fuse: parametrize configuration further
2025-07-14 8:22 [PATCH v2 0/5] thermal: tegra: add SOCTHERM support for Tegra114 Svyatoslav Ryhel
2025-07-14 8:22 ` [PATCH v2 1/5] soc: tegra: fuse: add Tegra114 nvmem cells and fuse lookups Svyatoslav Ryhel
2025-07-14 8:22 ` [PATCH v2 2/5] dt-bindings: thermal: Document Tegra114 SOCTHERM Thermal Management System Svyatoslav Ryhel
@ 2025-07-14 8:22 ` Svyatoslav Ryhel
2025-08-20 4:35 ` Mikko Perttunen
2025-07-14 8:22 ` [PATCH v2 4/5] thermal: tegra: add Tegra114 specific SOCTHERM driver Svyatoslav Ryhel
2025-07-14 8:22 ` [PATCH v2 5/5] ARM: tegra: Add SOCTHERM support on Tegra114 Svyatoslav Ryhel
4 siblings, 1 reply; 8+ messages in thread
From: Svyatoslav Ryhel @ 2025-07-14 8:22 UTC (permalink / raw)
To: Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Thierry Reding, Thierry Reding, Jonathan Hunter, Svyatoslav Ryhel
Cc: linux-pm, devicetree, linux-tegra, linux-kernel
Prepare soctherm fuse calibration for Tegra114 support.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
drivers/thermal/tegra/soctherm-fuse.c | 33 ++++++++++++++++-------
drivers/thermal/tegra/soctherm.h | 13 ++++++++-
drivers/thermal/tegra/tegra124-soctherm.c | 8 ++++++
drivers/thermal/tegra/tegra132-soctherm.c | 8 ++++++
drivers/thermal/tegra/tegra210-soctherm.c | 8 ++++++
5 files changed, 59 insertions(+), 11 deletions(-)
diff --git a/drivers/thermal/tegra/soctherm-fuse.c b/drivers/thermal/tegra/soctherm-fuse.c
index 190f95280e0b..3b808c4521b8 100644
--- a/drivers/thermal/tegra/soctherm-fuse.c
+++ b/drivers/thermal/tegra/soctherm-fuse.c
@@ -9,15 +9,10 @@
#include "soctherm.h"
-#define NOMINAL_CALIB_FT 105
-#define NOMINAL_CALIB_CP 25
-
#define FUSE_TSENSOR_CALIB_CP_TS_BASE_MASK 0x1fff
#define FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK (0x1fff << 13)
#define FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT 13
-#define FUSE_TSENSOR_COMMON 0x180
-
/*
* Tegra210: Layout of bits in FUSE_TSENSOR_COMMON:
* 3 2 1 0
@@ -44,6 +39,13 @@
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* |---------------------------------------------------| SHIFT_CP |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ *
+ * Tegra11x: Layout of bits in FUSE_TSENSOR_COMMON aka FUSE_VSENSOR_CALIB:
+ * 3 2 1 0
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | SHFT_FT | BASE_FT | SHIFT_CP | BASE_CP |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define CALIB_COEFFICIENT 1000000LL
@@ -77,7 +79,7 @@ int tegra_calc_shared_calib(const struct tegra_soctherm_fuse *tfuse,
s32 shifted_cp, shifted_ft;
int err;
- err = tegra_fuse_readl(FUSE_TSENSOR_COMMON, &val);
+ err = tegra_fuse_readl(tfuse->fuse_common_reg, &val);
if (err)
return err;
@@ -88,7 +90,7 @@ int tegra_calc_shared_calib(const struct tegra_soctherm_fuse *tfuse,
shifted_ft = (val & tfuse->fuse_shift_ft_mask) >>
tfuse->fuse_shift_ft_shift;
- shifted_ft = sign_extend32(shifted_ft, 4);
+ shifted_ft = sign_extend32(shifted_ft, tfuse->fuse_shift_ft_bits);
if (tfuse->fuse_spare_realignment) {
err = tegra_fuse_readl(tfuse->fuse_spare_realignment, &val);
@@ -96,10 +98,21 @@ int tegra_calc_shared_calib(const struct tegra_soctherm_fuse *tfuse,
return err;
}
- shifted_cp = sign_extend32(val, 5);
+ shifted_cp = (val & tfuse->fuse_shift_cp_mask) >>
+ tfuse->fuse_shift_cp_shift;
+ shifted_cp = sign_extend32(val, tfuse->fuse_shift_cp_bits);
- shared->actual_temp_cp = 2 * NOMINAL_CALIB_CP + shifted_cp;
- shared->actual_temp_ft = 2 * NOMINAL_CALIB_FT + shifted_ft;
+ shared->actual_temp_cp = 2 * tfuse->nominal_calib_cp + shifted_cp;
+ shared->actual_temp_ft = 2 * tfuse->nominal_calib_ft + shifted_ft;
+
+ /*
+ * Tegra114 provides fuse thermal corrections in 0.5C while expected
+ * precision should be 1C
+ */
+ if (tfuse->lower_precision) {
+ shared->actual_temp_cp /= 2;
+ shared->actual_temp_ft /= 2;
+ }
return 0;
}
diff --git a/drivers/thermal/tegra/soctherm.h b/drivers/thermal/tegra/soctherm.h
index 70501e73d586..6c0e0cc594a5 100644
--- a/drivers/thermal/tegra/soctherm.h
+++ b/drivers/thermal/tegra/soctherm.h
@@ -56,6 +56,13 @@
#define SENSOR_TEMP2_MEM_TEMP_MASK (0xffff << 16)
#define SENSOR_TEMP2_PLLX_TEMP_MASK 0xffff
+#define NOMINAL_CALIB_FT 105
+#define T114X_CALIB_FT 90
+#define NOMINAL_CALIB_CP 25
+
+#define FUSE_VSENSOR_CALIB 0x08c
+#define FUSE_TSENSOR_COMMON 0x180
+
/**
* struct tegra_tsensor_group - SOC_THERM sensor group data
* @name: short name of the temperature sensor group
@@ -109,9 +116,13 @@ struct tsensor_group_thermtrips {
struct tegra_soctherm_fuse {
u32 fuse_base_cp_mask, fuse_base_cp_shift;
+ u32 fuse_shift_cp_mask, fuse_shift_cp_shift;
u32 fuse_base_ft_mask, fuse_base_ft_shift;
u32 fuse_shift_ft_mask, fuse_shift_ft_shift;
- u32 fuse_spare_realignment;
+ u32 fuse_shift_cp_bits, fuse_shift_ft_bits;
+ u32 fuse_common_reg, fuse_spare_realignment;
+ u32 nominal_calib_cp, nominal_calib_ft;
+ bool lower_precision;
};
struct tsensor_shared_calib {
diff --git a/drivers/thermal/tegra/tegra124-soctherm.c b/drivers/thermal/tegra/tegra124-soctherm.c
index 20ad27f4d1a1..dd4dd7e9014d 100644
--- a/drivers/thermal/tegra/tegra124-soctherm.c
+++ b/drivers/thermal/tegra/tegra124-soctherm.c
@@ -200,11 +200,19 @@ static const struct tegra_tsensor tegra124_tsensors[] = {
static const struct tegra_soctherm_fuse tegra124_soctherm_fuse = {
.fuse_base_cp_mask = 0x3ff,
.fuse_base_cp_shift = 0,
+ .fuse_shift_cp_mask = 0x1f,
+ .fuse_shift_cp_shift = 0,
.fuse_base_ft_mask = 0x7ff << 10,
.fuse_base_ft_shift = 10,
.fuse_shift_ft_mask = 0x1f << 21,
.fuse_shift_ft_shift = 21,
+ .fuse_shift_cp_bits = 5,
+ .fuse_shift_ft_bits = 4,
+ .fuse_common_reg = FUSE_TSENSOR_COMMON,
.fuse_spare_realignment = 0x1fc,
+ .nominal_calib_cp = NOMINAL_CALIB_CP,
+ .nominal_calib_ft = NOMINAL_CALIB_FT,
+ .lower_precision = false,
};
const struct tegra_soctherm_soc tegra124_soctherm = {
diff --git a/drivers/thermal/tegra/tegra132-soctherm.c b/drivers/thermal/tegra/tegra132-soctherm.c
index b76308fdad9e..926836426688 100644
--- a/drivers/thermal/tegra/tegra132-soctherm.c
+++ b/drivers/thermal/tegra/tegra132-soctherm.c
@@ -200,11 +200,19 @@ static struct tegra_tsensor tegra132_tsensors[] = {
static const struct tegra_soctherm_fuse tegra132_soctherm_fuse = {
.fuse_base_cp_mask = 0x3ff,
.fuse_base_cp_shift = 0,
+ .fuse_shift_cp_mask = 0x1f,
+ .fuse_shift_cp_shift = 0,
.fuse_base_ft_mask = 0x7ff << 10,
.fuse_base_ft_shift = 10,
.fuse_shift_ft_mask = 0x1f << 21,
.fuse_shift_ft_shift = 21,
+ .fuse_shift_cp_bits = 5,
+ .fuse_shift_ft_bits = 4,
+ .fuse_common_reg = FUSE_TSENSOR_COMMON,
.fuse_spare_realignment = 0x1fc,
+ .nominal_calib_cp = NOMINAL_CALIB_CP,
+ .nominal_calib_ft = NOMINAL_CALIB_FT,
+ .lower_precision = false,
};
const struct tegra_soctherm_soc tegra132_soctherm = {
diff --git a/drivers/thermal/tegra/tegra210-soctherm.c b/drivers/thermal/tegra/tegra210-soctherm.c
index d0ff793f18c5..2877a7b43f2a 100644
--- a/drivers/thermal/tegra/tegra210-soctherm.c
+++ b/drivers/thermal/tegra/tegra210-soctherm.c
@@ -201,11 +201,19 @@ static const struct tegra_tsensor tegra210_tsensors[] = {
static const struct tegra_soctherm_fuse tegra210_soctherm_fuse = {
.fuse_base_cp_mask = 0x3ff << 11,
.fuse_base_cp_shift = 11,
+ .fuse_shift_cp_mask = 0x1f,
+ .fuse_shift_cp_shift = 0,
.fuse_base_ft_mask = 0x7ff << 21,
.fuse_base_ft_shift = 21,
.fuse_shift_ft_mask = 0x1f << 6,
.fuse_shift_ft_shift = 6,
+ .fuse_shift_cp_bits = 5,
+ .fuse_shift_ft_bits = 4,
+ .fuse_common_reg = FUSE_TSENSOR_COMMON,
.fuse_spare_realignment = 0,
+ .nominal_calib_cp = NOMINAL_CALIB_CP,
+ .nominal_calib_ft = NOMINAL_CALIB_FT,
+ .lower_precision = false,
};
static struct tsensor_group_thermtrips tegra210_tsensor_thermtrips[] = {
--
2.48.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v2 3/5] thermal: tegra: soctherm-fuse: parametrize configuration further
2025-07-14 8:22 ` [PATCH v2 3/5] thermal: tegra: soctherm-fuse: parametrize configuration further Svyatoslav Ryhel
@ 2025-08-20 4:35 ` Mikko Perttunen
2025-08-20 5:17 ` Svyatoslav Ryhel
0 siblings, 1 reply; 8+ messages in thread
From: Mikko Perttunen @ 2025-08-20 4:35 UTC (permalink / raw)
To: Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Thierry Reding, Thierry Reding, Jonathan Hunter, Svyatoslav Ryhel,
Svyatoslav Ryhel
Cc: linux-pm, devicetree, linux-tegra, linux-kernel
On Monday, July 14, 2025 5:22 PM Svyatoslav Ryhel wrote:
> Prepare soctherm fuse calibration for Tegra114 support.
Please describe the changes that are needed for Tegra114 in the commit
message.
>
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
> drivers/thermal/tegra/soctherm-fuse.c | 33 ++++++++++++++++-------
> drivers/thermal/tegra/soctherm.h | 13 ++++++++-
> drivers/thermal/tegra/tegra124-soctherm.c | 8 ++++++
> drivers/thermal/tegra/tegra132-soctherm.c | 8 ++++++
> drivers/thermal/tegra/tegra210-soctherm.c | 8 ++++++
> 5 files changed, 59 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/thermal/tegra/soctherm-fuse.c
> b/drivers/thermal/tegra/soctherm-fuse.c index 190f95280e0b..3b808c4521b8
> 100644
> --- a/drivers/thermal/tegra/soctherm-fuse.c
> +++ b/drivers/thermal/tegra/soctherm-fuse.c
> @@ -9,15 +9,10 @@
>
> #include "soctherm.h"
>
> -#define NOMINAL_CALIB_FT 105
> -#define NOMINAL_CALIB_CP 25
> -
> #define FUSE_TSENSOR_CALIB_CP_TS_BASE_MASK 0x1fff
> #define FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK (0x1fff << 13)
> #define FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT 13
>
> -#define FUSE_TSENSOR_COMMON 0x180
> -
> /*
> * Tegra210: Layout of bits in FUSE_TSENSOR_COMMON:
> * 3 2 1 0
> @@ -44,6 +39,13 @@
> * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
> * |---------------------------------------------------| SHIFT_CP |
> * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
> + *
> + * Tegra11x: Layout of bits in FUSE_TSENSOR_COMMON aka FUSE_VSENSOR_CALIB:
Let's just call it Tegra114. I see 'Tegra12x' is used above. You can change
that to 'Tegra124/Tegra132' while at it. The 'NNx' numbering is something
leaking from (old) downstream code that we're trying to avoid.
> + * 3 2 1 0
> + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
> + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
> + * | SHFT_FT | BASE_FT | SHIFT_CP | BASE_CP |
> + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
> */
Based on these diagrams, the size of e.g. SHIFT_FT has not changed between the
chip generations. I checked old downstream code, where
#define FUSE_SHIFT_FT_BITS 5
Below, we have
shifted_ft = sign_extend32(shifted_ft, 4);
However, sign_extend32 calculates as '31 - x' whereas the downstream code does
'32 - x'. So it appears to me that the size hasn't changed between the chips
and hence we don't need the added parameterization? Same might apply to other
fields in the calibration data.
>
> #define CALIB_COEFFICIENT 1000000LL
> @@ -77,7 +79,7 @@ int tegra_calc_shared_calib(const struct
> tegra_soctherm_fuse *tfuse, s32 shifted_cp, shifted_ft;
> int err;
>
> - err = tegra_fuse_readl(FUSE_TSENSOR_COMMON, &val);
> + err = tegra_fuse_readl(tfuse->fuse_common_reg, &val);
> if (err)
> return err;
>
> @@ -88,7 +90,7 @@ int tegra_calc_shared_calib(const struct
> tegra_soctherm_fuse *tfuse,
>
> shifted_ft = (val & tfuse->fuse_shift_ft_mask) >>
> tfuse->fuse_shift_ft_shift;
> - shifted_ft = sign_extend32(shifted_ft, 4);
> + shifted_ft = sign_extend32(shifted_ft, tfuse->fuse_shift_ft_bits);
>
> if (tfuse->fuse_spare_realignment) {
> err = tegra_fuse_readl(tfuse->fuse_spare_realignment, &val);
> @@ -96,10 +98,21 @@ int tegra_calc_shared_calib(const struct
> tegra_soctherm_fuse *tfuse, return err;
> }
>
> - shifted_cp = sign_extend32(val, 5);
> + shifted_cp = (val & tfuse->fuse_shift_cp_mask) >>
> + tfuse->fuse_shift_cp_shift;
> + shifted_cp = sign_extend32(val, tfuse->fuse_shift_cp_bits);
>
> - shared->actual_temp_cp = 2 * NOMINAL_CALIB_CP + shifted_cp;
> - shared->actual_temp_ft = 2 * NOMINAL_CALIB_FT + shifted_ft;
> + shared->actual_temp_cp = 2 * tfuse->nominal_calib_cp + shifted_cp;
> + shared->actual_temp_ft = 2 * tfuse->nominal_calib_ft + shifted_ft;
> +
> + /*
> + * Tegra114 provides fuse thermal corrections in 0.5C while expected
> + * precision should be 1C
> + */
If Tegra114 is lower precision, should this say it provides corrections in 1C
while newer chips are 0.5C?
> + if (tfuse->lower_precision) {
> + shared->actual_temp_cp /= 2;
> + shared->actual_temp_ft /= 2;
> + }
>
> return 0;
> }
> diff --git a/drivers/thermal/tegra/soctherm.h
> b/drivers/thermal/tegra/soctherm.h index 70501e73d586..6c0e0cc594a5 100644
> --- a/drivers/thermal/tegra/soctherm.h
> +++ b/drivers/thermal/tegra/soctherm.h
> @@ -56,6 +56,13 @@
> #define SENSOR_TEMP2_MEM_TEMP_MASK (0xffff << 16)
> #define SENSOR_TEMP2_PLLX_TEMP_MASK 0xffff
>
> +#define NOMINAL_CALIB_FT 105
> +#define T114X_CALIB_FT 90
> +#define NOMINAL_CALIB_CP 25
I would either just hardcode these values in the chip-specific files, or
#define TEGRA114_NOMINAL_CALIB_FT ...
#define TEGRA124_NOMINAL_CALIB_FT ...
#define TEGRA114_NOMINAL_CALIB_CP ...
> +
> +#define FUSE_VSENSOR_CALIB 0x08c
> +#define FUSE_TSENSOR_COMMON 0x180
> +
> /**
> * struct tegra_tsensor_group - SOC_THERM sensor group data
> * @name: short name of the temperature sensor group
> @@ -109,9 +116,13 @@ struct tsensor_group_thermtrips {
>
> struct tegra_soctherm_fuse {
> u32 fuse_base_cp_mask, fuse_base_cp_shift;
> + u32 fuse_shift_cp_mask, fuse_shift_cp_shift;
> u32 fuse_base_ft_mask, fuse_base_ft_shift;
> u32 fuse_shift_ft_mask, fuse_shift_ft_shift;
> - u32 fuse_spare_realignment;
> + u32 fuse_shift_cp_bits, fuse_shift_ft_bits;
> + u32 fuse_common_reg, fuse_spare_realignment;
> + u32 nominal_calib_cp, nominal_calib_ft;
> + bool lower_precision;
> };
>
> struct tsensor_shared_calib {
> diff --git a/drivers/thermal/tegra/tegra124-soctherm.c
> b/drivers/thermal/tegra/tegra124-soctherm.c index
> 20ad27f4d1a1..dd4dd7e9014d 100644
> --- a/drivers/thermal/tegra/tegra124-soctherm.c
> +++ b/drivers/thermal/tegra/tegra124-soctherm.c
> @@ -200,11 +200,19 @@ static const struct tegra_tsensor tegra124_tsensors[]
> = { static const struct tegra_soctherm_fuse tegra124_soctherm_fuse = {
> .fuse_base_cp_mask = 0x3ff,
> .fuse_base_cp_shift = 0,
> + .fuse_shift_cp_mask = 0x1f,
> + .fuse_shift_cp_shift = 0,
> .fuse_base_ft_mask = 0x7ff << 10,
> .fuse_base_ft_shift = 10,
> .fuse_shift_ft_mask = 0x1f << 21,
> .fuse_shift_ft_shift = 21,
> + .fuse_shift_cp_bits = 5,
> + .fuse_shift_ft_bits = 4,
> + .fuse_common_reg = FUSE_TSENSOR_COMMON,
> .fuse_spare_realignment = 0x1fc,
> + .nominal_calib_cp = NOMINAL_CALIB_CP,
> + .nominal_calib_ft = NOMINAL_CALIB_FT,
> + .lower_precision = false,
> };
>
> const struct tegra_soctherm_soc tegra124_soctherm = {
> diff --git a/drivers/thermal/tegra/tegra132-soctherm.c
> b/drivers/thermal/tegra/tegra132-soctherm.c index
> b76308fdad9e..926836426688 100644
> --- a/drivers/thermal/tegra/tegra132-soctherm.c
> +++ b/drivers/thermal/tegra/tegra132-soctherm.c
> @@ -200,11 +200,19 @@ static struct tegra_tsensor tegra132_tsensors[] = {
> static const struct tegra_soctherm_fuse tegra132_soctherm_fuse = {
> .fuse_base_cp_mask = 0x3ff,
> .fuse_base_cp_shift = 0,
> + .fuse_shift_cp_mask = 0x1f,
> + .fuse_shift_cp_shift = 0,
> .fuse_base_ft_mask = 0x7ff << 10,
> .fuse_base_ft_shift = 10,
> .fuse_shift_ft_mask = 0x1f << 21,
> .fuse_shift_ft_shift = 21,
> + .fuse_shift_cp_bits = 5,
> + .fuse_shift_ft_bits = 4,
> + .fuse_common_reg = FUSE_TSENSOR_COMMON,
> .fuse_spare_realignment = 0x1fc,
> + .nominal_calib_cp = NOMINAL_CALIB_CP,
> + .nominal_calib_ft = NOMINAL_CALIB_FT,
> + .lower_precision = false,
> };
>
> const struct tegra_soctherm_soc tegra132_soctherm = {
> diff --git a/drivers/thermal/tegra/tegra210-soctherm.c
> b/drivers/thermal/tegra/tegra210-soctherm.c index
> d0ff793f18c5..2877a7b43f2a 100644
> --- a/drivers/thermal/tegra/tegra210-soctherm.c
> +++ b/drivers/thermal/tegra/tegra210-soctherm.c
> @@ -201,11 +201,19 @@ static const struct tegra_tsensor tegra210_tsensors[]
> = { static const struct tegra_soctherm_fuse tegra210_soctherm_fuse = {
> .fuse_base_cp_mask = 0x3ff << 11,
> .fuse_base_cp_shift = 11,
> + .fuse_shift_cp_mask = 0x1f,
> + .fuse_shift_cp_shift = 0,
> .fuse_base_ft_mask = 0x7ff << 21,
> .fuse_base_ft_shift = 21,
> .fuse_shift_ft_mask = 0x1f << 6,
> .fuse_shift_ft_shift = 6,
> + .fuse_shift_cp_bits = 5,
> + .fuse_shift_ft_bits = 4,
> + .fuse_common_reg = FUSE_TSENSOR_COMMON,
> .fuse_spare_realignment = 0,
> + .nominal_calib_cp = NOMINAL_CALIB_CP,
> + .nominal_calib_ft = NOMINAL_CALIB_FT,
> + .lower_precision = false,
> };
>
> static struct tsensor_group_thermtrips tegra210_tsensor_thermtrips[] = {
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v2 3/5] thermal: tegra: soctherm-fuse: parametrize configuration further
2025-08-20 4:35 ` Mikko Perttunen
@ 2025-08-20 5:17 ` Svyatoslav Ryhel
0 siblings, 0 replies; 8+ messages in thread
From: Svyatoslav Ryhel @ 2025-08-20 5:17 UTC (permalink / raw)
To: Mikko Perttunen
Cc: Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Thierry Reding, Thierry Reding, Jonathan Hunter, linux-pm,
devicetree, linux-tegra, linux-kernel
ср, 20 серп. 2025 р. о 07:35 Mikko Perttunen <mperttunen@nvidia.com> пише:
>
> On Monday, July 14, 2025 5:22 PM Svyatoslav Ryhel wrote:
> > Prepare soctherm fuse calibration for Tegra114 support.
>
> Please describe the changes that are needed for Tegra114 in the commit
> message.
>
All changes are mostly related to different calibration register layout.
> >
> > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> > ---
> > drivers/thermal/tegra/soctherm-fuse.c | 33 ++++++++++++++++-------
> > drivers/thermal/tegra/soctherm.h | 13 ++++++++-
> > drivers/thermal/tegra/tegra124-soctherm.c | 8 ++++++
> > drivers/thermal/tegra/tegra132-soctherm.c | 8 ++++++
> > drivers/thermal/tegra/tegra210-soctherm.c | 8 ++++++
> > 5 files changed, 59 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/thermal/tegra/soctherm-fuse.c
> > b/drivers/thermal/tegra/soctherm-fuse.c index 190f95280e0b..3b808c4521b8
> > 100644
> > --- a/drivers/thermal/tegra/soctherm-fuse.c
> > +++ b/drivers/thermal/tegra/soctherm-fuse.c
> > @@ -9,15 +9,10 @@
> >
> > #include "soctherm.h"
> >
> > -#define NOMINAL_CALIB_FT 105
> > -#define NOMINAL_CALIB_CP 25
> > -
> > #define FUSE_TSENSOR_CALIB_CP_TS_BASE_MASK 0x1fff
> > #define FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK (0x1fff << 13)
> > #define FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT 13
> >
> > -#define FUSE_TSENSOR_COMMON 0x180
> > -
> > /*
> > * Tegra210: Layout of bits in FUSE_TSENSOR_COMMON:
> > * 3 2 1 0
> > @@ -44,6 +39,13 @@
> > * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
> > * |---------------------------------------------------| SHIFT_CP |
> > * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
> > + *
> > + * Tegra11x: Layout of bits in FUSE_TSENSOR_COMMON aka FUSE_VSENSOR_CALIB:
>
> Let's just call it Tegra114. I see 'Tegra12x' is used above. You can change
> that to 'Tegra124/Tegra132' while at it. The 'NNx' numbering is something
> leaking from (old) downstream code that we're trying to avoid.
>
> > + * 3 2 1 0
> > + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
> > + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
> > + * | SHFT_FT | BASE_FT | SHIFT_CP | BASE_CP |
> > + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
> > */
>
> Based on these diagrams, the size of e.g. SHIFT_FT has not changed between the
> chip generations. I checked old downstream code, where
>
> #define FUSE_SHIFT_FT_BITS 5
>
> Below, we have
>
> shifted_ft = sign_extend32(shifted_ft, 4);
>
> However, sign_extend32 calculates as '31 - x' whereas the downstream code does
> '32 - x'. So it appears to me that the size hasn't changed between the chips
> and hence we don't need the added parameterization? Same might apply to other
> fields in the calibration data.
>
It seems you are correct regarding FUSE_SHIFT_FT_BITS and
FUSE_SHIFT_CP_BITS I will adjust that. Thank you
> >
> > #define CALIB_COEFFICIENT 1000000LL
> > @@ -77,7 +79,7 @@ int tegra_calc_shared_calib(const struct
> > tegra_soctherm_fuse *tfuse, s32 shifted_cp, shifted_ft;
> > int err;
> >
> > - err = tegra_fuse_readl(FUSE_TSENSOR_COMMON, &val);
> > + err = tegra_fuse_readl(tfuse->fuse_common_reg, &val);
> > if (err)
> > return err;
> >
> > @@ -88,7 +90,7 @@ int tegra_calc_shared_calib(const struct
> > tegra_soctherm_fuse *tfuse,
> >
> > shifted_ft = (val & tfuse->fuse_shift_ft_mask) >>
> > tfuse->fuse_shift_ft_shift;
> > - shifted_ft = sign_extend32(shifted_ft, 4);
> > + shifted_ft = sign_extend32(shifted_ft, tfuse->fuse_shift_ft_bits);
> >
> > if (tfuse->fuse_spare_realignment) {
> > err = tegra_fuse_readl(tfuse->fuse_spare_realignment, &val);
> > @@ -96,10 +98,21 @@ int tegra_calc_shared_calib(const struct
> > tegra_soctherm_fuse *tfuse, return err;
> > }
> >
> > - shifted_cp = sign_extend32(val, 5);
> > + shifted_cp = (val & tfuse->fuse_shift_cp_mask) >>
> > + tfuse->fuse_shift_cp_shift;
> > + shifted_cp = sign_extend32(val, tfuse->fuse_shift_cp_bits);
> >
> > - shared->actual_temp_cp = 2 * NOMINAL_CALIB_CP + shifted_cp;
> > - shared->actual_temp_ft = 2 * NOMINAL_CALIB_FT + shifted_ft;
> > + shared->actual_temp_cp = 2 * tfuse->nominal_calib_cp + shifted_cp;
> > + shared->actual_temp_ft = 2 * tfuse->nominal_calib_ft + shifted_ft;
> > +
> > + /*
> > + * Tegra114 provides fuse thermal corrections in 0.5C while expected
> > + * precision should be 1C
> > + */
>
> If Tegra114 is lower precision, should this say it provides corrections in 1C
> while newer chips are 0.5C?
>
lower_precision is an action not a statement (took that from
downstream iirc). Comment is correct, T114 provides output in 0.5C
while newer gens in 1C
> > + if (tfuse->lower_precision) {
> > + shared->actual_temp_cp /= 2;
> > + shared->actual_temp_ft /= 2;
> > + }
> >
> > return 0;
> > }
> > diff --git a/drivers/thermal/tegra/soctherm.h
> > b/drivers/thermal/tegra/soctherm.h index 70501e73d586..6c0e0cc594a5 100644
> > --- a/drivers/thermal/tegra/soctherm.h
> > +++ b/drivers/thermal/tegra/soctherm.h
> > @@ -56,6 +56,13 @@
> > #define SENSOR_TEMP2_MEM_TEMP_MASK (0xffff << 16)
> > #define SENSOR_TEMP2_PLLX_TEMP_MASK 0xffff
> >
> > +#define NOMINAL_CALIB_FT 105
> > +#define T114X_CALIB_FT 90
> > +#define NOMINAL_CALIB_CP 25
>
> I would either just hardcode these values in the chip-specific files, or
>
> #define TEGRA114_NOMINAL_CALIB_FT ...
> #define TEGRA124_NOMINAL_CALIB_FT ...
> #define TEGRA114_NOMINAL_CALIB_CP ...
>
> > +
> > +#define FUSE_VSENSOR_CALIB 0x08c
> > +#define FUSE_TSENSOR_COMMON 0x180
> > +
> > /**
> > * struct tegra_tsensor_group - SOC_THERM sensor group data
> > * @name: short name of the temperature sensor group
> > @@ -109,9 +116,13 @@ struct tsensor_group_thermtrips {
> >
> > struct tegra_soctherm_fuse {
> > u32 fuse_base_cp_mask, fuse_base_cp_shift;
> > + u32 fuse_shift_cp_mask, fuse_shift_cp_shift;
> > u32 fuse_base_ft_mask, fuse_base_ft_shift;
> > u32 fuse_shift_ft_mask, fuse_shift_ft_shift;
> > - u32 fuse_spare_realignment;
> > + u32 fuse_shift_cp_bits, fuse_shift_ft_bits;
> > + u32 fuse_common_reg, fuse_spare_realignment;
> > + u32 nominal_calib_cp, nominal_calib_ft;
> > + bool lower_precision;
> > };
> >
> > struct tsensor_shared_calib {
> > diff --git a/drivers/thermal/tegra/tegra124-soctherm.c
> > b/drivers/thermal/tegra/tegra124-soctherm.c index
> > 20ad27f4d1a1..dd4dd7e9014d 100644
> > --- a/drivers/thermal/tegra/tegra124-soctherm.c
> > +++ b/drivers/thermal/tegra/tegra124-soctherm.c
> > @@ -200,11 +200,19 @@ static const struct tegra_tsensor tegra124_tsensors[]
> > = { static const struct tegra_soctherm_fuse tegra124_soctherm_fuse = {
> > .fuse_base_cp_mask = 0x3ff,
> > .fuse_base_cp_shift = 0,
> > + .fuse_shift_cp_mask = 0x1f,
> > + .fuse_shift_cp_shift = 0,
> > .fuse_base_ft_mask = 0x7ff << 10,
> > .fuse_base_ft_shift = 10,
> > .fuse_shift_ft_mask = 0x1f << 21,
> > .fuse_shift_ft_shift = 21,
> > + .fuse_shift_cp_bits = 5,
> > + .fuse_shift_ft_bits = 4,
> > + .fuse_common_reg = FUSE_TSENSOR_COMMON,
> > .fuse_spare_realignment = 0x1fc,
> > + .nominal_calib_cp = NOMINAL_CALIB_CP,
> > + .nominal_calib_ft = NOMINAL_CALIB_FT,
> > + .lower_precision = false,
> > };
> >
> > const struct tegra_soctherm_soc tegra124_soctherm = {
> > diff --git a/drivers/thermal/tegra/tegra132-soctherm.c
> > b/drivers/thermal/tegra/tegra132-soctherm.c index
> > b76308fdad9e..926836426688 100644
> > --- a/drivers/thermal/tegra/tegra132-soctherm.c
> > +++ b/drivers/thermal/tegra/tegra132-soctherm.c
> > @@ -200,11 +200,19 @@ static struct tegra_tsensor tegra132_tsensors[] = {
> > static const struct tegra_soctherm_fuse tegra132_soctherm_fuse = {
> > .fuse_base_cp_mask = 0x3ff,
> > .fuse_base_cp_shift = 0,
> > + .fuse_shift_cp_mask = 0x1f,
> > + .fuse_shift_cp_shift = 0,
> > .fuse_base_ft_mask = 0x7ff << 10,
> > .fuse_base_ft_shift = 10,
> > .fuse_shift_ft_mask = 0x1f << 21,
> > .fuse_shift_ft_shift = 21,
> > + .fuse_shift_cp_bits = 5,
> > + .fuse_shift_ft_bits = 4,
> > + .fuse_common_reg = FUSE_TSENSOR_COMMON,
> > .fuse_spare_realignment = 0x1fc,
> > + .nominal_calib_cp = NOMINAL_CALIB_CP,
> > + .nominal_calib_ft = NOMINAL_CALIB_FT,
> > + .lower_precision = false,
> > };
> >
> > const struct tegra_soctherm_soc tegra132_soctherm = {
> > diff --git a/drivers/thermal/tegra/tegra210-soctherm.c
> > b/drivers/thermal/tegra/tegra210-soctherm.c index
> > d0ff793f18c5..2877a7b43f2a 100644
> > --- a/drivers/thermal/tegra/tegra210-soctherm.c
> > +++ b/drivers/thermal/tegra/tegra210-soctherm.c
> > @@ -201,11 +201,19 @@ static const struct tegra_tsensor tegra210_tsensors[]
> > = { static const struct tegra_soctherm_fuse tegra210_soctherm_fuse = {
> > .fuse_base_cp_mask = 0x3ff << 11,
> > .fuse_base_cp_shift = 11,
> > + .fuse_shift_cp_mask = 0x1f,
> > + .fuse_shift_cp_shift = 0,
> > .fuse_base_ft_mask = 0x7ff << 21,
> > .fuse_base_ft_shift = 21,
> > .fuse_shift_ft_mask = 0x1f << 6,
> > .fuse_shift_ft_shift = 6,
> > + .fuse_shift_cp_bits = 5,
> > + .fuse_shift_ft_bits = 4,
> > + .fuse_common_reg = FUSE_TSENSOR_COMMON,
> > .fuse_spare_realignment = 0,
> > + .nominal_calib_cp = NOMINAL_CALIB_CP,
> > + .nominal_calib_ft = NOMINAL_CALIB_FT,
> > + .lower_precision = false,
> > };
> >
> > static struct tsensor_group_thermtrips tegra210_tsensor_thermtrips[] = {
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 4/5] thermal: tegra: add Tegra114 specific SOCTHERM driver
2025-07-14 8:22 [PATCH v2 0/5] thermal: tegra: add SOCTHERM support for Tegra114 Svyatoslav Ryhel
` (2 preceding siblings ...)
2025-07-14 8:22 ` [PATCH v2 3/5] thermal: tegra: soctherm-fuse: parametrize configuration further Svyatoslav Ryhel
@ 2025-07-14 8:22 ` Svyatoslav Ryhel
2025-07-14 8:22 ` [PATCH v2 5/5] ARM: tegra: Add SOCTHERM support on Tegra114 Svyatoslav Ryhel
4 siblings, 0 replies; 8+ messages in thread
From: Svyatoslav Ryhel @ 2025-07-14 8:22 UTC (permalink / raw)
To: Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Thierry Reding, Thierry Reding, Jonathan Hunter, Svyatoslav Ryhel
Cc: linux-pm, devicetree, linux-tegra, linux-kernel
Add Tegra114 specific SOCTHERM driver.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
drivers/thermal/tegra/Makefile | 1 +
drivers/thermal/tegra/soctherm.c | 6 +
drivers/thermal/tegra/soctherm.h | 4 +
drivers/thermal/tegra/tegra114-soctherm.c | 213 ++++++++++++++++++++++
4 files changed, 224 insertions(+)
create mode 100644 drivers/thermal/tegra/tegra114-soctherm.c
diff --git a/drivers/thermal/tegra/Makefile b/drivers/thermal/tegra/Makefile
index eb27d194c583..9b3e91f7fb97 100644
--- a/drivers/thermal/tegra/Makefile
+++ b/drivers/thermal/tegra/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_TEGRA_BPMP_THERMAL) += tegra-bpmp-thermal.o
obj-$(CONFIG_TEGRA30_TSENSOR) += tegra30-tsensor.o
tegra-soctherm-y := soctherm.o soctherm-fuse.o
+tegra-soctherm-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114-soctherm.o
tegra-soctherm-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124-soctherm.o
tegra-soctherm-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra132-soctherm.o
tegra-soctherm-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-soctherm.o
diff --git a/drivers/thermal/tegra/soctherm.c b/drivers/thermal/tegra/soctherm.c
index 2c5ddf0db40c..7bdab2add7af 100644
--- a/drivers/thermal/tegra/soctherm.c
+++ b/drivers/thermal/tegra/soctherm.c
@@ -2048,6 +2048,12 @@ static void soctherm_init(struct platform_device *pdev)
}
static const struct of_device_id tegra_soctherm_of_match[] = {
+#ifdef CONFIG_ARCH_TEGRA_114_SOC
+ {
+ .compatible = "nvidia,tegra114-soctherm",
+ .data = &tegra114_soctherm,
+ },
+#endif
#ifdef CONFIG_ARCH_TEGRA_124_SOC
{
.compatible = "nvidia,tegra124-soctherm",
diff --git a/drivers/thermal/tegra/soctherm.h b/drivers/thermal/tegra/soctherm.h
index 6c0e0cc594a5..75ee2a520886 100644
--- a/drivers/thermal/tegra/soctherm.h
+++ b/drivers/thermal/tegra/soctherm.h
@@ -148,6 +148,10 @@ int tegra_calc_tsensor_calib(const struct tegra_tsensor *sensor,
const struct tsensor_shared_calib *shared,
u32 *calib);
+#ifdef CONFIG_ARCH_TEGRA_114_SOC
+extern const struct tegra_soctherm_soc tegra114_soctherm;
+#endif
+
#ifdef CONFIG_ARCH_TEGRA_124_SOC
extern const struct tegra_soctherm_soc tegra124_soctherm;
#endif
diff --git a/drivers/thermal/tegra/tegra114-soctherm.c b/drivers/thermal/tegra/tegra114-soctherm.c
new file mode 100644
index 000000000000..eca65ec6f8c1
--- /dev/null
+++ b/drivers/thermal/tegra/tegra114-soctherm.c
@@ -0,0 +1,213 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2024, Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/thermal/tegra124-soctherm.h>
+
+#include "soctherm.h"
+
+#define TEGRA114_THERMTRIP_ANY_EN_MASK (0x1 << 28)
+#define TEGRA114_THERMTRIP_MEM_EN_MASK (0x1 << 27)
+#define TEGRA114_THERMTRIP_GPU_EN_MASK (0x1 << 26)
+#define TEGRA114_THERMTRIP_CPU_EN_MASK (0x1 << 25)
+#define TEGRA114_THERMTRIP_TSENSE_EN_MASK (0x1 << 24)
+#define TEGRA114_THERMTRIP_GPUMEM_THRESH_MASK (0xff << 16)
+#define TEGRA114_THERMTRIP_CPU_THRESH_MASK (0xff << 8)
+#define TEGRA114_THERMTRIP_TSENSE_THRESH_MASK 0xff
+
+#define TEGRA114_THERMCTL_LVL0_UP_THRESH_MASK (0xff << 17)
+#define TEGRA114_THERMCTL_LVL0_DN_THRESH_MASK (0xff << 9)
+
+#define TEGRA114_THRESH_GRAIN 1000
+#define TEGRA114_BPTT 8
+
+static const struct tegra_tsensor_configuration tegra114_tsensor_config = {
+ .tall = 16300,
+ .tiddq_en = 1,
+ .ten_count = 1,
+ .tsample = 163,
+ .tsample_ate = 655,
+};
+
+static const struct tegra_tsensor_group tegra114_tsensor_group_cpu = {
+ .id = TEGRA124_SOCTHERM_SENSOR_CPU,
+ .name = "cpu",
+ .sensor_temp_offset = SENSOR_TEMP1,
+ .sensor_temp_mask = SENSOR_TEMP1_CPU_TEMP_MASK,
+ .pdiv = 10,
+ .pdiv_ate = 10,
+ .pdiv_mask = SENSOR_PDIV_CPU_MASK,
+ .pllx_hotspot_diff = 10,
+ .pllx_hotspot_mask = SENSOR_HOTSPOT_CPU_MASK,
+ .thermtrip_any_en_mask = TEGRA114_THERMTRIP_ANY_EN_MASK,
+ .thermtrip_enable_mask = TEGRA114_THERMTRIP_CPU_EN_MASK,
+ .thermtrip_threshold_mask = TEGRA114_THERMTRIP_CPU_THRESH_MASK,
+ .thermctl_isr_mask = THERM_IRQ_CPU_MASK,
+ .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_CPU,
+ .thermctl_lvl0_up_thresh_mask = TEGRA114_THERMCTL_LVL0_UP_THRESH_MASK,
+ .thermctl_lvl0_dn_thresh_mask = TEGRA114_THERMCTL_LVL0_DN_THRESH_MASK,
+};
+
+static const struct tegra_tsensor_group tegra114_tsensor_group_gpu = {
+ .id = TEGRA124_SOCTHERM_SENSOR_GPU,
+ .name = "gpu",
+ .sensor_temp_offset = SENSOR_TEMP1,
+ .sensor_temp_mask = SENSOR_TEMP1_GPU_TEMP_MASK,
+ .pdiv = 10,
+ .pdiv_ate = 10,
+ .pdiv_mask = SENSOR_PDIV_GPU_MASK,
+ .pllx_hotspot_diff = 5,
+ .pllx_hotspot_mask = SENSOR_HOTSPOT_GPU_MASK,
+ .thermtrip_any_en_mask = TEGRA114_THERMTRIP_ANY_EN_MASK,
+ .thermtrip_enable_mask = TEGRA114_THERMTRIP_GPU_EN_MASK,
+ .thermtrip_threshold_mask = TEGRA114_THERMTRIP_GPUMEM_THRESH_MASK,
+ .thermctl_isr_mask = THERM_IRQ_GPU_MASK,
+ .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_GPU,
+ .thermctl_lvl0_up_thresh_mask = TEGRA114_THERMCTL_LVL0_UP_THRESH_MASK,
+ .thermctl_lvl0_dn_thresh_mask = TEGRA114_THERMCTL_LVL0_DN_THRESH_MASK,
+};
+
+static const struct tegra_tsensor_group tegra114_tsensor_group_pll = {
+ .id = TEGRA124_SOCTHERM_SENSOR_PLLX,
+ .name = "pll",
+ .sensor_temp_offset = SENSOR_TEMP2,
+ .sensor_temp_mask = SENSOR_TEMP2_PLLX_TEMP_MASK,
+ .pdiv = 10,
+ .pdiv_ate = 10,
+ .pdiv_mask = SENSOR_PDIV_PLLX_MASK,
+ .thermtrip_any_en_mask = TEGRA114_THERMTRIP_ANY_EN_MASK,
+ .thermtrip_enable_mask = TEGRA114_THERMTRIP_TSENSE_EN_MASK,
+ .thermtrip_threshold_mask = TEGRA114_THERMTRIP_TSENSE_THRESH_MASK,
+ .thermctl_isr_mask = THERM_IRQ_TSENSE_MASK,
+ .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_TSENSE,
+ .thermctl_lvl0_up_thresh_mask = TEGRA114_THERMCTL_LVL0_UP_THRESH_MASK,
+ .thermctl_lvl0_dn_thresh_mask = TEGRA114_THERMCTL_LVL0_DN_THRESH_MASK,
+};
+
+static const struct tegra_tsensor_group tegra114_tsensor_group_mem = {
+ .id = TEGRA124_SOCTHERM_SENSOR_MEM,
+ .name = "mem",
+ .sensor_temp_offset = SENSOR_TEMP2,
+ .sensor_temp_mask = SENSOR_TEMP2_MEM_TEMP_MASK,
+ .pdiv = 10,
+ .pdiv_ate = 10,
+ .pdiv_mask = SENSOR_PDIV_MEM_MASK,
+ .pllx_hotspot_diff = 0,
+ .pllx_hotspot_mask = SENSOR_HOTSPOT_MEM_MASK,
+ .thermtrip_any_en_mask = TEGRA114_THERMTRIP_ANY_EN_MASK,
+ .thermtrip_enable_mask = TEGRA114_THERMTRIP_MEM_EN_MASK,
+ .thermtrip_threshold_mask = TEGRA114_THERMTRIP_GPUMEM_THRESH_MASK,
+ .thermctl_isr_mask = THERM_IRQ_MEM_MASK,
+ .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_MEM,
+ .thermctl_lvl0_up_thresh_mask = TEGRA114_THERMCTL_LVL0_UP_THRESH_MASK,
+ .thermctl_lvl0_dn_thresh_mask = TEGRA114_THERMCTL_LVL0_DN_THRESH_MASK,
+};
+
+static const struct tegra_tsensor_group *tegra114_tsensor_groups[] = {
+ &tegra114_tsensor_group_cpu,
+ &tegra114_tsensor_group_gpu,
+ &tegra114_tsensor_group_pll,
+ &tegra114_tsensor_group_mem,
+};
+
+static const struct tegra_tsensor tegra114_tsensors[] = {
+ {
+ .name = "cpu0",
+ .base = 0xc0,
+ .config = &tegra114_tsensor_config,
+ .calib_fuse_offset = 0x098,
+ .fuse_corr_alpha = 1196400,
+ .fuse_corr_beta = -13600000,
+ .group = &tegra114_tsensor_group_cpu,
+ }, {
+ .name = "cpu1",
+ .base = 0xe0,
+ .config = &tegra114_tsensor_config,
+ .calib_fuse_offset = 0x084,
+ .fuse_corr_alpha = 1196400,
+ .fuse_corr_beta = -13600000,
+ .group = &tegra114_tsensor_group_cpu,
+ }, {
+ .name = "cpu2",
+ .base = 0x100,
+ .config = &tegra114_tsensor_config,
+ .calib_fuse_offset = 0x088,
+ .fuse_corr_alpha = 1196400,
+ .fuse_corr_beta = -13600000,
+ .group = &tegra114_tsensor_group_cpu,
+ }, {
+ .name = "cpu3",
+ .base = 0x120,
+ .config = &tegra114_tsensor_config,
+ .calib_fuse_offset = 0x12c,
+ .fuse_corr_alpha = 1196400,
+ .fuse_corr_beta = -13600000,
+ .group = &tegra114_tsensor_group_cpu,
+ }, {
+ .name = "mem0",
+ .base = 0x140,
+ .config = &tegra114_tsensor_config,
+ .calib_fuse_offset = 0x158,
+ .fuse_corr_alpha = 1000000,
+ .fuse_corr_beta = 0,
+ .group = &tegra114_tsensor_group_mem,
+ }, {
+ .name = "mem1",
+ .base = 0x160,
+ .config = &tegra114_tsensor_config,
+ .calib_fuse_offset = 0x15c,
+ .fuse_corr_alpha = 1000000,
+ .fuse_corr_beta = 0,
+ .group = &tegra114_tsensor_group_mem,
+ }, {
+ .name = "gpu",
+ .base = 0x180,
+ .config = &tegra114_tsensor_config,
+ .calib_fuse_offset = 0x154,
+ .fuse_corr_alpha = 1124500,
+ .fuse_corr_beta = -9793100,
+ .group = &tegra114_tsensor_group_gpu,
+ }, {
+ .name = "pllx",
+ .base = 0x1a0,
+ .config = &tegra114_tsensor_config,
+ .calib_fuse_offset = 0x160,
+ .fuse_corr_alpha = 1224200,
+ .fuse_corr_beta = -14665000,
+ .group = &tegra114_tsensor_group_pll,
+ },
+};
+
+static const struct tegra_soctherm_fuse tegra114_soctherm_fuse = {
+ .fuse_base_cp_mask = 0x3ff,
+ .fuse_base_cp_shift = 0,
+ .fuse_shift_cp_mask = 0x3f << 10,
+ .fuse_shift_cp_shift = 10,
+ .fuse_base_ft_mask = 0x7ff << 16,
+ .fuse_base_ft_shift = 16,
+ .fuse_shift_ft_mask = 0x1f << 27,
+ .fuse_shift_ft_shift = 27,
+ .fuse_shift_cp_bits = 6,
+ .fuse_shift_ft_bits = 5,
+ .fuse_common_reg = FUSE_VSENSOR_CALIB,
+ .fuse_spare_realignment = 0,
+ .nominal_calib_cp = NOMINAL_CALIB_CP,
+ .nominal_calib_ft = T114X_CALIB_FT,
+ .lower_precision = true,
+};
+
+const struct tegra_soctherm_soc tegra114_soctherm = {
+ .tsensors = tegra114_tsensors,
+ .num_tsensors = ARRAY_SIZE(tegra114_tsensors),
+ .ttgs = tegra114_tsensor_groups,
+ .num_ttgs = ARRAY_SIZE(tegra114_tsensor_groups),
+ .tfuse = &tegra114_soctherm_fuse,
+ .thresh_grain = TEGRA114_THRESH_GRAIN,
+ .bptt = TEGRA114_BPTT,
+ .use_ccroc = false,
+};
--
2.48.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v2 5/5] ARM: tegra: Add SOCTHERM support on Tegra114
2025-07-14 8:22 [PATCH v2 0/5] thermal: tegra: add SOCTHERM support for Tegra114 Svyatoslav Ryhel
` (3 preceding siblings ...)
2025-07-14 8:22 ` [PATCH v2 4/5] thermal: tegra: add Tegra114 specific SOCTHERM driver Svyatoslav Ryhel
@ 2025-07-14 8:22 ` Svyatoslav Ryhel
4 siblings, 0 replies; 8+ messages in thread
From: Svyatoslav Ryhel @ 2025-07-14 8:22 UTC (permalink / raw)
To: Rafael J. Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Thierry Reding, Thierry Reding, Jonathan Hunter, Svyatoslav Ryhel
Cc: linux-pm, devicetree, linux-tegra, linux-kernel
Add SOCTHERM and thermal zones nodes into common Tegra 4 device tree.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
arch/arm/boot/dts/nvidia/tegra114.dtsi | 197 +++++++++++++++++++++++++
1 file changed, 197 insertions(+)
diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvidia/tegra114.dtsi
index 3ee51d7f3935..cb30a7948e19 100644
--- a/arch/arm/boot/dts/nvidia/tegra114.dtsi
+++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/tegra114-car.h>
+#include <dt-bindings/thermal/tegra124-soctherm.h>
#include <dt-bindings/soc/tegra-pmc.h>
/ {
@@ -694,6 +695,46 @@ mipi: mipi@700e3000 {
#nvidia,mipi-calibrate-cells = <1>;
};
+ soctherm: thermal-sensor@700e2000 {
+ compatible = "nvidia,tegra114-soctherm";
+ reg = <0x700e2000 0x600>, /* SOC_THERM reg_base */
+ <0x60006000 0x400>; /* CAR reg_base */
+ reg-names = "soctherm-reg", "car-reg";
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "thermal", "edp";
+ clocks = <&tegra_car TEGRA114_CLK_TSENSOR>,
+ <&tegra_car TEGRA114_CLK_SOC_THERM>;
+ clock-names = "tsensor", "soctherm";
+ resets = <&tegra_car 78>;
+ reset-names = "soctherm";
+
+ assigned-clocks = <&tegra_car TEGRA114_CLK_TSENSOR>,
+ <&tegra_car TEGRA114_CLK_SOC_THERM>;
+ assigned-clock-rates = <500000>, <51000000>;
+
+ assigned-clock-parents = <&tegra_car TEGRA114_CLK_CLK_M>,
+ <&tegra_car TEGRA114_CLK_PLL_P>;
+
+ #thermal-sensor-cells = <1>;
+
+ throttle-cfgs {
+ throttle_heavy: heavy {
+ nvidia,priority = <100>;
+ nvidia,cpu-throt-percent = <80>;
+ nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
+ #cooling-cells = <2>;
+ };
+
+ throttle_light: light {
+ nvidia,priority = <80>;
+ nvidia,cpu-throt-percent = <50>;
+ nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_MED>;
+ #cooling-cells = <2>;
+ };
+ };
+ };
+
dfll: clock@70110000 {
compatible = "nvidia,tegra114-dfll";
reg = <0x70110000 0x100>, /* DFLL control */
@@ -858,24 +899,28 @@ cpu0: cpu@0 {
clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
/* FIXME: what's the actual transition time? */
clock-latency = <300000>;
+ #cooling-cells = <2>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <1>;
+ #cooling-cells = <2>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <2>;
+ #cooling-cells = <2>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <3>;
+ #cooling-cells = <2>;
};
};
@@ -888,6 +933,158 @@ pmu {
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
+ thermal-zones {
+ cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <1000>;
+
+ thermal-sensors =
+ <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
+
+ trips {
+ cpu-shutdown-trip {
+ temperature = <102000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+
+ cpu_throttle_trip: cpu-throttle-trip {
+ temperature = <100000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ cpu_balanced_trip: cpu-balanced-trip {
+ temperature = <90000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_throttle_trip>;
+ cooling-device = <&throttle_heavy 1 1>;
+ };
+
+ map1 {
+ trip = <&cpu_balanced_trip>;
+ cooling-device = <&throttle_light 1 1>;
+ };
+ };
+ };
+
+ mem-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <1000>;
+
+ thermal-sensors =
+ <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
+
+ trips {
+ mem-shutdown-trip {
+ temperature = <102000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+
+ mem_throttle_trip: mem-throttle-trip {
+ temperature = <100000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ mem_balanced_trip: mem-balanced-trip {
+ temperature = <90000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ /*
+ * There are currently no cooling maps,
+ * because there are no cooling devices.
+ */
+ };
+ };
+
+ gpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <1000>;
+
+ thermal-sensors =
+ <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
+
+ trips {
+ gpu-shutdown-trip {
+ temperature = <102000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+
+ gpu_throttle_trip: gpu-throttle-trip {
+ temperature = <100000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ gpu_balanced_trip: gpu-balanced-trip {
+ temperature = <90000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&gpu_throttle_trip>;
+ cooling-device = <&throttle_heavy 1 1>;
+ };
+
+ map1 {
+ trip = <&gpu_balanced_trip>;
+ cooling-device = <&throttle_light 1 1>;
+ };
+ };
+ };
+
+ pllx-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <1000>;
+
+ thermal-sensors =
+ <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
+
+ trips {
+ pllx-shutdown-trip {
+ temperature = <102000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+
+ pllx_throttle_trip: pllx-throttle-trip {
+ temperature = <100000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ pllx_balanced_trip: pllx-balanced-trip {
+ temperature = <90000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ /*
+ * There are currently no cooling maps,
+ * because there are no cooling devices.
+ */
+ };
+ };
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts =
--
2.48.1
^ permalink raw reply related [flat|nested] 8+ messages in thread