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Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Alim Akhtar , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , linux-pm@vger.kernel.org (open list:SAMSUNG THERMAL DRIVER), linux-samsung-soc@vger.kernel.org (open list:SAMSUNG THERMAL DRIVER), linux-arm-kernel@lists.infradead.org (moderated list:ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES), linux-kernel@vger.kernel.org (open list), llvm@lists.linux.dev (open list:CLANG/LLVM BUILD SUPPORT:Keyword:\b(?i:clang|llvm)\b) Cc: Anand Moon , Mateusz Majewski Subject: [PATCH v7 6/7] thermal/drivers/exynos: Handle temperature threshold IRQs with SoC-specific mapping Date: Wed, 13 Aug 2025 18:39:50 +0530 Message-ID: <20250813131007.343402-7-linux.amoon@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250813131007.343402-1-linux.amoon@gmail.com> References: <20250813131007.343402-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The Exynos TMU interrupt handling mechanism has been refined to utilize SoC-specific mappings for interrupt clear registers, targeting rising and falling edge events. This change introduces a tmu_irq_map structure that defines these edge-specific interrupt bits, improving the accuracy of thermal event handling by ensuring that only relevant interrupts are acknowledged and cleared. The exynos4210_tmu_clear_irqs() function has been refactored to incorporate this mapping. Notably, for Exynos4210, a check has been added to prevent clearing unsupported falling edge interrupt bits. As per user manuals, specific mappings for interrupt status and clear registers include: Exynos4412: Falling edge bits at 20, 16, 12, and rising edge bits at 8, 4, 0. Exynos5422: Falling edge bits at 24, 20, 16, and rising edge bits at 8, 4, 0. Exynos5433: Falling edge bits at 23, 17, 16, and rising edge bits at 7, 1, 0. Cc: Mateusz Majewski Signed-off-by: Anand Moon --- v7: New patch in this series simpilfy the logic for set and clear rising and failling edges of the IRQ clear register. [0] https://lore.kernel.org/all/20250624075815.132207-1-m.majewski2@samsung.com/ --- drivers/thermal/samsung/exynos_tmu.c | 70 ++++++++++++++++++++++++---- 1 file changed, 60 insertions(+), 10 deletions(-) diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c index 146f29fadea9..5e581055e3f3 100644 --- a/drivers/thermal/samsung/exynos_tmu.c +++ b/drivers/thermal/samsung/exynos_tmu.c @@ -197,6 +197,12 @@ struct exynos_tmu_data { void (*tmu_clear_irqs)(struct exynos_tmu_data *data); }; +/* Map Rise and Falling edges for IRQ Clean */ +struct tmu_irq_map { + u32 fall[3]; + u32 rise[3]; +}; + /* * TMU treats temperature as a mapped temperature code. * The temperature is converted differently depending on the calibration type. @@ -765,8 +771,9 @@ static irqreturn_t exynos_tmu_threaded_irq(int irq, void *id) static void exynos4210_tmu_clear_irqs(struct exynos_tmu_data *data) { - unsigned int val_irq; + unsigned int val_irq, clear_irq = 0; u32 tmu_intstat, tmu_intclear; + struct tmu_irq_map irq_map = {0}; if (data->soc == SOC_ARCH_EXYNOS5260) { tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT; @@ -783,15 +790,58 @@ static void exynos4210_tmu_clear_irqs(struct exynos_tmu_data *data) } val_irq = readl(data->base + tmu_intstat); - /* - * Clear the interrupts. Please note that the documentation for - * Exynos3250, Exynos4412, Exynos5250 and Exynos5260 incorrectly - * states that INTCLEAR register has a different placing of bits - * responsible for FALL IRQs than INTSTAT register. Exynos5420 - * and Exynos5440 documentation is correct (Exynos4210 doesn't - * support FALL IRQs at all). - */ - writel(val_irq, data->base + tmu_intclear); + + /* Exynos4210 doesn't support FALL interrupts */ + if (data->soc == SOC_ARCH_EXYNOS4210) { + writel(val_irq, data->base + tmu_intclear); + return; + } + + /* Set SoC-specific interrupt bit mappings */ + switch (data->soc) { + case SOC_ARCH_EXYNOS3250: + case SOC_ARCH_EXYNOS4412: + case SOC_ARCH_EXYNOS5250: + case SOC_ARCH_EXYNOS5260: + irq_map.fall[2] = BIT(20); + irq_map.fall[1] = BIT(16); + irq_map.fall[0] = BIT(12); + irq_map.rise[2] = BIT(8); + irq_map.rise[1] = BIT(4); + irq_map.rise[0] = BIT(0); + break; + case SOC_ARCH_EXYNOS5420: + case SOC_ARCH_EXYNOS5420_TRIMINFO: + irq_map.fall[2] = BIT(24); + irq_map.fall[1] = BIT(20); + irq_map.fall[0] = BIT(16); + irq_map.rise[2] = BIT(8); + irq_map.rise[1] = BIT(4); + irq_map.rise[0] = BIT(0); + break; + case SOC_ARCH_EXYNOS5433: + case SOC_ARCH_EXYNOS7: + irq_map.fall[2] = BIT(23); + irq_map.fall[1] = BIT(17); + irq_map.fall[0] = BIT(16); + irq_map.rise[2] = BIT(7); + irq_map.rise[1] = BIT(1); + irq_map.rise[0] = BIT(0); + break; + default: + pr_warn("exynos-tmu: Unknown SoC type %d, using fallback IRQ mapping\n", soc); + break; + + /* Map active INTSTAT bits to INTCLEAR */ + for (int i = 0; i < 3; i++) { + if (val_irq & irq_map.fall[i]) + clear_irq |= irq_map.fall[i]; + if (val_irq & irq_map.rise[i]) + clear_irq |= irq_map.rise[i]; + } + + if (clear_irq) + writel(clear_irq, data->base + tmu_intclear); } static const struct of_device_id exynos_tmu_match[] = { -- 2.50.1