From: Xi Pardee <xi.pardee@linux.intel.com>
To: xi.pardee@linux.intel.com, irenic.rajneesh@gmail.com,
david.e.box@linux.intel.com, hdegoede@redhat.com,
ilpo.jarvinen@linux.intel.com,
platform-driver-x86@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org
Subject: [PATCH v3 6/6] platform/x86:intel/pmc: Enable SSRAM support for Panther Lake
Date: Fri, 15 Aug 2025 15:46:04 -0700 [thread overview]
Message-ID: <20250815224611.2460255-7-xi.pardee@linux.intel.com> (raw)
In-Reply-To: <20250815224611.2460255-1-xi.pardee@linux.intel.com>
Enable Panther Lake platforms to achieve PMC information from
Intel PMC SSRAM Telemetry driver and substate requirements data
from telemetry region.
Signed-off-by: Xi Pardee <xi.pardee@linux.intel.com>
---
drivers/platform/x86/intel/pmc/core.h | 4 ++++
drivers/platform/x86/intel/pmc/ptl.c | 33 +++++++++++++++++++++++++++
2 files changed, 37 insertions(+)
diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h
index 6ff2d171dc2ba..381755aaeafaf 100644
--- a/drivers/platform/x86/intel/pmc/core.h
+++ b/drivers/platform/x86/intel/pmc/core.h
@@ -297,6 +297,10 @@ enum ppfear_regs {
#define PTL_PMC_LTR_CUR_ASLT 0x1C28
#define PTL_PMC_LTR_CUR_PLT 0x1C2C
#define PTL_PCD_PMC_MMIO_REG_LEN 0x31A8
+#define PTL_NUM_S0IX_BLOCKER 106
+#define PTL_BLK_REQ_OFFSET 55
+#define PTL_BDF_OFFSET 0x0
+#define PTL_BDF_TABLE_SIZE 54
/* SSRAM PMC Device ID */
/* LNL */
diff --git a/drivers/platform/x86/intel/pmc/ptl.c b/drivers/platform/x86/intel/pmc/ptl.c
index 394515af60d60..20c6dac7a6729 100644
--- a/drivers/platform/x86/intel/pmc/ptl.c
+++ b/drivers/platform/x86/intel/pmc/ptl.c
@@ -10,6 +10,17 @@
#include "core.h"
+/* PMC SSRAM PMT Telemetry GUIDS */
+#define PCDP_LPM_REQ_GUID 0x47179370
+
+/*
+ * Die Mapping to Product.
+ * Product PCDDie
+ * PTL-H PCD-H
+ * PTL-P PCD-P
+ * PTL-U PCD-P
+ */
+
static const struct pmc_bit_map ptl_pcdp_pfear_map[] = {
{"PMC_0", BIT(0)},
{"FUSE_OSSE", BIT(1)},
@@ -515,6 +526,24 @@ static const struct pmc_reg_map ptl_pcdp_reg_map = {
.lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,
.s0ix_blocker_maps = ptl_pcdp_blk_maps,
.s0ix_blocker_offset = LNL_S0IX_BLOCKER_OFFSET,
+ .num_s0ix_blocker = PTL_NUM_S0IX_BLOCKER,
+ .blocker_req_offset = PTL_BLK_REQ_OFFSET,
+ .bdf_offset = PTL_BDF_OFFSET,
+ .bdf_table_size = PTL_BDF_TABLE_SIZE,
+};
+
+static struct pmc_info ptl_pmc_info_list[] = {
+ {
+ .guid = PCDP_LPM_REQ_GUID,
+ .devid = PMC_DEVID_PTL_PCDH,
+ .map = &ptl_pcdp_reg_map,
+ },
+ {
+ .guid = PCDP_LPM_REQ_GUID,
+ .devid = PMC_DEVID_PTL_PCDP,
+ .map = &ptl_pcdp_reg_map,
+ },
+ {}
};
#define PTL_NPU_PCI_DEV 0xb03e
@@ -543,8 +572,12 @@ static int ptl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_in
}
struct pmc_dev_info ptl_pmc_dev = {
+ .pci_func = 2,
+ .regmap_list = ptl_pmc_info_list,
.map = &ptl_pcdp_reg_map,
+ .sub_req_show = &pmc_core_substate_blk_req_fops,
.suspend = cnl_suspend,
.resume = ptl_resume,
.init = ptl_core_init,
+ .sub_req = pmc_core_pmt_get_sub_req_bdf,
};
--
2.43.0
prev parent reply other threads:[~2025-08-15 22:46 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-15 22:45 [PATCH v3 0/6] Enable SSRAM support in PTL and LNL Xi Pardee
2025-08-15 22:45 ` [PATCH v3 1/6] platform/x86:intel/pmc: Enable SSRAM support for Lunar Lake Xi Pardee
2025-08-15 22:46 ` [PATCH v3 2/6] platform/x86:intel/pmc: Move telemetry endpoint register handling Xi Pardee
2025-08-15 22:46 ` [PATCH v3 3/6] platform/x86:intel/pmc: Improve function to show substate header Xi Pardee
2025-08-28 13:09 ` Ilpo Järvinen
2025-08-15 22:46 ` [PATCH v3 4/6] platform/x86:intel/pmc: Show substate requirement for S0ix blockers Xi Pardee
2025-08-28 13:06 ` Ilpo Järvinen
2025-09-01 23:52 ` Russell Haley
2025-08-15 22:46 ` [PATCH v3 5/6] platform/x86:intel/pmc: Show device and function number Xi Pardee
2025-08-28 13:56 ` Ilpo Järvinen
2025-08-15 22:46 ` Xi Pardee [this message]
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