From: Aaron Kling via B4 Relay <devnull+webgeek1234.gmail.com@kernel.org>
To: Krzysztof Kozlowski <krzk@kernel.org>,
Rob Herring <robh@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
"Rafael J. Wysocki" <rafael@kernel.org>,
Viresh Kumar <viresh.kumar@linaro.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org,
Aaron Kling <webgeek1234@gmail.com>
Subject: [PATCH 7/8] arm64: tegra: Add CPU OPP tables for Tegra186
Date: Sun, 31 Aug 2025 22:33:55 -0500 [thread overview]
Message-ID: <20250831-tegra186-icc-v1-7-607ddc53b507@gmail.com> (raw)
In-Reply-To: <20250831-tegra186-icc-v1-0-607ddc53b507@gmail.com>
From: Aaron Kling <webgeek1234@gmail.com>
Add OPP table and interconnects property to scale DDR frequency with
CPU frequency for better performance. Each operating point entry of
the OPP table has CPU freq to per MC channel bandwidth mapping. One
table is added for each cluster because the different cpu types have
different scaling curves.
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 317 +++++++++++++++++++++++++++++++
1 file changed, 317 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 5778c93af3e6e72f5f14a9fcee1e7abf80d2d2c5..d3f6a938a9b019a043ce2de7ec17bd00155b3eb2 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -1943,6 +1943,8 @@ cpus {
denver_0: cpu@0 {
compatible = "nvidia,tegra186-denver";
device_type = "cpu";
+ operating-points-v2 = <&dnv_opp_tbl>;
+ interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>;
i-cache-size = <0x20000>;
i-cache-line-size = <64>;
i-cache-sets = <512>;
@@ -1956,6 +1958,8 @@ denver_0: cpu@0 {
denver_1: cpu@1 {
compatible = "nvidia,tegra186-denver";
device_type = "cpu";
+ operating-points-v2 = <&dnv_opp_tbl>;
+ interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>;
i-cache-size = <0x20000>;
i-cache-line-size = <64>;
i-cache-sets = <512>;
@@ -1969,6 +1973,8 @@ denver_1: cpu@1 {
ca57_0: cpu@2 {
compatible = "arm,cortex-a57";
device_type = "cpu";
+ operating-points-v2 = <&a57_opp_tbl>;
+ interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>;
i-cache-size = <0xC000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@@ -1982,6 +1988,8 @@ ca57_0: cpu@2 {
ca57_1: cpu@3 {
compatible = "arm,cortex-a57";
device_type = "cpu";
+ operating-points-v2 = <&a57_opp_tbl>;
+ interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>;
i-cache-size = <0xC000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@@ -1995,6 +2003,8 @@ ca57_1: cpu@3 {
ca57_2: cpu@4 {
compatible = "arm,cortex-a57";
device_type = "cpu";
+ operating-points-v2 = <&a57_opp_tbl>;
+ interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>;
i-cache-size = <0xC000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@@ -2008,6 +2018,8 @@ ca57_2: cpu@4 {
ca57_3: cpu@5 {
compatible = "arm,cortex-a57";
device_type = "cpu";
+ operating-points-v2 = <&a57_opp_tbl>;
+ interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>;
i-cache-size = <0xC000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
@@ -2182,4 +2194,309 @@ timer {
interrupt-parent = <&gic>;
always-on;
};
+
+ dnv_opp_tbl: opp-table-cluster0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-998400000 {
+ opp-hz = /bits/ 64 <998400000>;
+ opp-peak-kBps = <816000>;
+ };
+
+ opp-1036800000 {
+ opp-hz = /bits/ 64 <1036800000>;
+ opp-peak-kBps = <816000>;
+ };
+
+ opp-1075200000 {
+ opp-hz = /bits/ 64 <1075200000>;
+ opp-peak-kBps = <816000>;
+ };
+
+ opp-1113600000 {
+ opp-hz = /bits/ 64 <1113600000>;
+ opp-peak-kBps = <1600000>;
+ };
+
+ opp-1152000000 {
+ opp-hz = /bits/ 64 <1152000000>;
+ opp-peak-kBps = <1600000>;
+ };
+
+ opp-1190400000 {
+ opp-hz = /bits/ 64 <1190400000>;
+ opp-peak-kBps = <1600000>;
+ };
+
+ opp-1228800000 {
+ opp-hz = /bits/ 64 <1228800000>;
+ opp-peak-kBps = <1600000>;
+ };
+
+ opp-1267200000 {
+ opp-hz = /bits/ 64 <1267200000>;
+ opp-peak-kBps = <1600000>;
+ };
+
+ opp-1305600000 {
+ opp-hz = /bits/ 64 <1305600000>;
+ opp-peak-kBps = <1600000>;
+ };
+
+ opp-1344000000 {
+ opp-hz = /bits/ 64 <1344000000>;
+ opp-peak-kBps = <1600000>;
+ };
+
+ opp-1382400000 {
+ opp-hz = /bits/ 64 <1382400000>;
+ opp-peak-kBps = <1600000>;
+ };
+
+ opp-1420800000 {
+ opp-hz = /bits/ 64 <1420800000>;
+ opp-peak-kBps = <1600000>;
+ };
+
+ opp-1459200000 {
+ opp-hz = /bits/ 64 <1459200000>;
+ opp-peak-kBps = <3200000>;
+ };
+
+ opp-1497600000 {
+ opp-hz = /bits/ 64 <1497600000>;
+ opp-peak-kBps = <3200000>;
+ };
+
+ opp-1536000000 {
+ opp-hz = /bits/ 64 <1536000000>;
+ opp-peak-kBps = <3200000>;
+ };
+
+ opp-1574400000 {
+ opp-hz = /bits/ 64 <1574400000>;
+ opp-peak-kBps = <3200000>;
+ };
+
+ opp-1612800000 {
+ opp-hz = /bits/ 64 <1612800000>;
+ opp-peak-kBps = <3200000>;
+ };
+
+ opp-1651200000 {
+ opp-hz = /bits/ 64 <1651200000>;
+ opp-peak-kBps = <3200000>;
+ };
+
+ opp-1689600000 {
+ opp-hz = /bits/ 64 <1689600000>;
+ opp-peak-kBps = <3200000>;
+ };
+
+ opp-1728000000 {
+ opp-hz = /bits/ 64 <1728000000>;
+ opp-peak-kBps = <3200000>;
+ };
+
+ opp-1766400000 {
+ opp-hz = /bits/ 64 <1766400000>;
+ opp-peak-kBps = <3200000>;
+ };
+
+ opp-1804800000 {
+ opp-hz = /bits/ 64 <1804800000>;
+ opp-peak-kBps = <3200000>;
+ };
+
+ opp-1843200000 {
+ opp-hz = /bits/ 64 <1843200000>;
+ opp-peak-kBps = <3200000>;
+ };
+
+ opp-1881600000 {
+ opp-hz = /bits/ 64 <1881600000>;
+ opp-peak-kBps = <3200000>;
+ };
+
+ opp-1920000000 {
+ opp-hz = /bits/ 64 <1920000000>;
+ opp-peak-kBps = <3200000>;
+ };
+
+ opp-1958400000 {
+ opp-hz = /bits/ 64 <1958400000>;
+ opp-peak-kBps = <3200000>;
+ };
+
+ opp-1996800000 {
+ opp-hz = /bits/ 64 <1996800000>;
+ opp-peak-kBps = <3732000>;
+ };
+
+ opp-2035200000 {
+ opp-hz = /bits/ 64 <2035200000>;
+ opp-peak-kBps = <3732000>;
+ };
+ };
+
+ a57_opp_tbl: opp-table-cluster1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-883200000 {
+ opp-hz = /bits/ 64 <883200000>;
+ opp-peak-kBps = <816000>;
+ };
+
+ opp-921600000 {
+ opp-hz = /bits/ 64 <921600000>;
+ opp-peak-kBps = <816000>;
+ };
+
+ opp-960000000 {
+ opp-hz = /bits/ 64 <960000000>;
+ opp-peak-kBps = <816000>;
+ };
+
+ opp-998400000 {
+ opp-hz = /bits/ 64 <998400000>;
+ opp-peak-kBps = <816000>;
+ };
+
+ opp-1036800000 {
+ opp-hz = /bits/ 64 <1036800000>;
+ opp-peak-kBps = <816000>;
+ };
+
+ opp-1075200000 {
+ opp-hz = /bits/ 64 <1075200000>;
+ opp-peak-kBps = <816000>;
+ };
+
+ opp-1113600000 {
+ opp-hz = /bits/ 64 <1113600000>;
+ opp-peak-kBps = <1600000>;
+ };
+
+ opp-1152000000 {
+ opp-hz = /bits/ 64 <1152000000>;
+ opp-peak-kBps = <1600000>;
+ };
+
+ opp-1190400000 {
+ opp-hz = /bits/ 64 <1190400000>;
+ opp-peak-kBps = <1600000>;
+ };
+
+ opp-1228800000 {
+ opp-hz = /bits/ 64 <1228800000>;
+ opp-peak-kBps = <1600000>;
+ };
+
+ opp-1267200000 {
+ opp-hz = /bits/ 64 <1267200000>;
+ opp-peak-kBps = <1600000>;
+ };
+
+ opp-1305600000 {
+ opp-hz = /bits/ 64 <1305600000>;
+ opp-peak-kBps = <1600000>;
+ };
+
+ opp-1344000000 {
+ opp-hz = /bits/ 64 <1344000000>;
+ opp-peak-kBps = <1600000>;
+ };
+
+ opp-1382400000 {
+ opp-hz = /bits/ 64 <1382400000>;
+ opp-peak-kBps = <1600000>;
+ };
+
+ opp-1420800000 {
+ opp-hz = /bits/ 64 <1420800000>;
+ opp-peak-kBps = <1600000>;
+ };
+
+ opp-1459200000 {
+ opp-hz = /bits/ 64 <1459200000>;
+ opp-peak-kBps = <3200000>;
+ };
+
+ opp-1497600000 {
+ opp-hz = /bits/ 64 <1497600000>;
+ opp-peak-kBps = <3200000>;
+ };
+
+ opp-1536000000 {
+ opp-hz = /bits/ 64 <1536000000>;
+ opp-peak-kBps = <3200000>;
+ };
+
+ opp-1574400000 {
+ opp-hz = /bits/ 64 <1574400000>;
+ opp-peak-kBps = <3200000>;
+ };
+
+ opp-1612800000 {
+ opp-hz = /bits/ 64 <1612800000>;
+ opp-peak-kBps = <3200000>;
+ };
+
+ opp-1651200000 {
+ opp-hz = /bits/ 64 <1651200000>;
+ opp-peak-kBps = <3200000>;
+ };
+
+ opp-1689600000 {
+ opp-hz = /bits/ 64 <1689600000>;
+ opp-peak-kBps = <3200000>;
+ };
+
+ opp-1728000000 {
+ opp-hz = /bits/ 64 <1728000000>;
+ opp-peak-kBps = <3200000>;
+ };
+
+ opp-1766400000 {
+ opp-hz = /bits/ 64 <1766400000>;
+ opp-peak-kBps = <3200000>;
+ };
+
+ opp-1804800000 {
+ opp-hz = /bits/ 64 <1804800000>;
+ opp-peak-kBps = <3200000>;
+ };
+
+ opp-1843200000 {
+ opp-hz = /bits/ 64 <1843200000>;
+ opp-peak-kBps = <3200000>;
+ };
+
+ opp-1881600000 {
+ opp-hz = /bits/ 64 <1881600000>;
+ opp-peak-kBps = <3200000>;
+ };
+
+ opp-1920000000 {
+ opp-hz = /bits/ 64 <1920000000>;
+ opp-peak-kBps = <3200000>;
+ };
+
+ opp-1958400000 {
+ opp-hz = /bits/ 64 <1958400000>;
+ opp-peak-kBps = <3200000>;
+ };
+
+ opp-1996800000 {
+ opp-hz = /bits/ 64 <1996800000>;
+ opp-peak-kBps = <3732000>;
+ };
+
+ opp-2035200000 {
+ opp-hz = /bits/ 64 <2035200000>;
+ opp-peak-kBps = <3732000>;
+ };
+ };
};
--
2.50.1
next prev parent reply other threads:[~2025-09-01 3:34 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-01 3:33 [PATCH 0/8] Support dynamic EMC frequency scaling on Tegra186/Tegra194 Aaron Kling via B4 Relay
2025-09-01 3:33 ` [PATCH 1/8] dt-bindings: tegra: Add ICC IDs for dummy memory clients for Tegra186 Aaron Kling via B4 Relay
2025-09-01 3:33 ` [PATCH 2/8] dt-bindings: tegra: Add ICC IDs for dummy memory clients for Tegra194 Aaron Kling via B4 Relay
2025-09-02 8:25 ` Krzysztof Kozlowski
2025-09-02 16:57 ` Aaron Kling
2025-09-01 3:33 ` [PATCH 3/8] cpufreq: tegra186: add OPP support and set bandwidth Aaron Kling via B4 Relay
2025-09-01 5:53 ` Viresh Kumar
2025-09-02 17:21 ` Aaron Kling
2025-09-03 5:01 ` Viresh Kumar
2025-09-04 11:19 ` Sumit Gupta
2025-09-09 5:43 ` Aaron Kling
2025-09-01 3:33 ` [PATCH 4/8] memory: tegra186-emc: Support non-bpmp icc scaling Aaron Kling via B4 Relay
2025-09-01 3:33 ` [PATCH 5/8] memory: tegra186: Support " Aaron Kling via B4 Relay
2025-09-01 3:33 ` [PATCH 6/8] memory: tegra194: " Aaron Kling via B4 Relay
2025-09-01 3:33 ` Aaron Kling via B4 Relay [this message]
2025-09-01 3:33 ` [PATCH 8/8] arm64: tegra: Add CPU OPP tables for Tegra194 Aaron Kling via B4 Relay
2025-09-02 8:23 ` [PATCH 0/8] Support dynamic EMC frequency scaling on Tegra186/Tegra194 Krzysztof Kozlowski
2025-09-02 16:51 ` Aaron Kling
2025-09-03 6:18 ` Krzysztof Kozlowski
2025-09-03 6:20 ` Krzysztof Kozlowski
2025-09-03 6:37 ` Aaron Kling
2025-09-04 8:19 ` Krzysztof Kozlowski
2025-09-04 17:49 ` Aaron Kling
2025-09-05 6:55 ` Krzysztof Kozlowski
2025-09-04 11:47 ` Sumit Gupta
2025-09-04 16:47 ` Aaron Kling
2025-09-05 13:37 ` Sumit Gupta
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