[PATCH RFC 00/10] MT8196 GPU Frequency/Power Control Support

Nicolas Frattaroli
2025-09-05T10:24:03Z

This series, currently an RFC, introduces two new drivers to accomplish
controlling the frequency and power of the Mali GPU on MediaTek MT8196
SoCs.

It's marked as an RFC as I want feedback on the general approach, and
because there is a clock series I need to send out first but that's
waiting for the other clock series to be accepted first in order to not
create needless confusion and conflicts.

The reason why it's not as straightforward as with other SoCs is that
the MT8196 has quite complex glue logic. There's an additional MCU
running a specialised firmware, which communicates with the application
processor through a mailbox and some SRAM, and is in charge of
controlling the regulators, the PLL clocks, and the power gating of the
GPU, all while also being in charge of any DVFS control.

This set of drivers is enough to communicate desired OPP index limits to
the aforementioned MCU, referred to as "GPUEB" from here on out. The
GPUEB is still free to lower the effective frequency if the GPU has no
jobs going on at all, even when a higher OPP is set. There's also
several more powerful OPPs it seemingly refuses to apply, possibly
because those are boost levels.

The frequency control driver lives in panthor's subdirectory, as it
registers a devfreq device for the panthor GPU device, and needs to
mingle with it somewhat closely. I've kept the tie-in parts generic
enough however to not make this a complete hack; mediatek_mfg (the
frequency control driver) registers itself as a "devfreq provider" with
panthor, and panthor picks it up during its probe function (or defers if
mediatek_mfg is not ready yet, after adding a device link first).

The mailbox driver is a fairly bog-standard common mailbox framework
driver, just specific to the firmware that runs on the GPUEB. Most of
its channels are not known, as they're either not really used apart from
debug references in downstream code, or have indecipherable downstream
code, and I lacked the necessary documentation.

Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
Nicolas Frattaroli (10):
dt-bindings: gpu: mali-valhall-csf: add mediatek,mt8196-mali variant
dt-bindings: devfreq: add mt8196-gpufreq binding
dt-bindings: sram: Add compatible for mediatek,mt8196-gpufreq-sram
dt-bindings: mailbox: Add MT8196 GPUEB Mailbox
mailbox: add MediaTek GPUEB IPI mailbox
drm/panthor: call into devfreq for current frequency
drm/panthor: move panthor_devfreq struct to header
drm/panthor: devfreq: expose get_dev_status and make it more generic
drm/panthor: devfreq: add pluggable devfreq providers
drm/panthor: add support for MediaTek MFlexGraphics

.../bindings/devfreq/mediatek,mt8196-gpufreq.yaml | 116 +++
.../bindings/gpu/arm,mali-valhall-csf.yaml | 36 +-
.../mailbox/mediatek,mt8196-gpueb-mbox.yaml | 64 ++
Documentation/devicetree/bindings/sram/sram.yaml | 1 +
drivers/gpu/drm/panthor/Kconfig | 13 +
drivers/gpu/drm/panthor/Makefile | 2 +
drivers/gpu/drm/panthor/mediatek_mfg.c | 1053 ++++++++++++++++++++
drivers/gpu/drm/panthor/panthor_devfreq.c | 136 ++-
drivers/gpu/drm/panthor/panthor_devfreq.h | 57 +-
drivers/gpu/drm/panthor/panthor_device.h | 3 -
drivers/gpu/drm/panthor/panthor_drv.c | 4 +-
drivers/mailbox/Kconfig | 10 +
drivers/mailbox/Makefile | 2 +
drivers/mailbox/mtk-gpueb-mailbox.c | 330 ++++++
14 files changed, 1788 insertions(+), 39 deletions(-)
---
base-commit: 87a9e300217e33b2388b9c1ffe99ec454eb6e983
change-id: 20250829-mt8196-gpufreq-a7645670d182
prerequisite-message-id: <20250829091913.131528-1-laura.nao@collabora.com>
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Best regards,
--
Nicolas Frattaroli <nicolas.frattaroli@collabora.com>