[PATCH v2 01/10] dt-bindings: gpu: mali-valhall-csf: add mediatek,mt8196-mali variant

Nicolas Frattaroli
2025-09-12T18:38:08Z

The Mali-based GPU on the MediaTek MT8196 SoC uses a separate MCU to
control the power and frequency of the GPU.

It lets us omit the OPP tables from the device tree, as those can now be
enumerated at runtime from the MCU.

Add the mediatek,mt8196-mali compatible, and a performance-domains
property which points to the MCU's device tree node in this case. It's
required on mt8196 devices.

Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
.../bindings/gpu/arm,mali-valhall-csf.yaml | 32 +++++++++++++++++++++-
1 file changed, 31 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
index a5b4e00217587c5d1f889094e2fff7b76e6148eb..163b4457f7f25dcdd509c558558a73694521c96d 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
@@ -19,6 +19,7 @@ properties:
- items:
- enum:
- rockchip,rk3588-mali
+ - mediatek,mt8196-mali
- const: arm,mali-valhall-csf # Mali Valhall GPU model/revision is fully discoverable

reg:
@@ -53,6 +54,9 @@ properties:
opp-table:
type: object

+ performance-domains:
+ maxItems: 1
+
power-domains:
minItems: 1
maxItems: 5
@@ -91,7 +95,6 @@ required:
- interrupts
- interrupt-names
- clocks
- - mali-supply

additionalProperties: false

@@ -105,9 +108,24 @@ allOf:
properties:
clocks:
minItems: 3
+ performance-domains: false
power-domains:
maxItems: 1
power-domain-names: false
+ required:
+ - mali-supply
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt8196-mali
+ then:
+ properties:
+ mali-supply: false
+ sram-supply: false
+ operating-points-v2: false
+ required:
+ - performance-domains

examples:
- |
@@ -143,5 +161,17 @@ examples:
};
};
};
+ - |
+ gpu@48000000 {
+ compatible = "mediatek,mt8196-mali", "arm,mali-valhall-csf";
+ reg = <0x48000000 0x480000>;
+ clocks = <&mfgpll 0>;
+ clock-names = "core";
+ interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "job", "mmu", "gpu";
+ performance-domains = <&gpufreq>;
+ };

...

--
2.51.0