From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 45E242F6594 for ; Thu, 6 Nov 2025 22:59:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.54 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762469982; cv=none; b=NaQxVETqP1AuYzphtUvh3n+4Nvjkgx8PBzQvfJM3SgZVmamrXf9GlC+eN1fODKfKH53sZRCAZAjEpktp955WF0iK7j4RPUeXQAvIp0XeyqkDCBp7TkbkBuorpLLmzK3vNtiKouFHDm0VBGw281b1oscJIXMtj0v6LfNcbVr7Zvg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762469982; c=relaxed/simple; bh=jPfKF8pnLyQ0CZOQltmMuX5kCAPhjPVB3UjoDZYqqDk=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Rk5h5dDfvT870fz50wOU1s97BpZfMU6xdJwNYwrYkWZYCfqzsQV5d1IPOXSpkAfq/7pg3eNo8QyTSkxyIDFx4ZXTK/ZAR1S9MADsWz6r9eHMk/4TSyBQLTmr4MiIYceKjcJMV1zjitSdttikVGidrYiIUcFZ1MXtim59OCbsiGI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=EPLT4HXQ; arc=none smtp.client-ip=209.85.128.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="EPLT4HXQ" Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-471191ac79dso1385015e9.3 for ; Thu, 06 Nov 2025 14:59:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1762469979; x=1763074779; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=DcNqxELVDSK7RhV1ekY6lA9dpVwVz2jR8jDfVBLjBqs=; b=EPLT4HXQQzKHxbiJ4oWgcMwA4lJHoK8M7RrHcCAbtTkvq2sXlWDTdmv09PYb43EeDL tQw6TNc35NEqdx5wxhgzEJhcwGYWaVZ0P2bojD4WCp0wB8ogXYlmjjq6IozvDFR0JEmx 4nUPqPkhYAi1xNukB0JFk/46Ru8JhCcbKBIhgYDym7G4+vMLW2U4ATHPbpLjWQojsNWL gRppItFjigSTYb4LfR65pU49WHn32mTfbf6CE/TBKvo+y3smiTR9lh6NxYP14p2f8rpj hFAXhMdVKdwvT7eGfGiCPmQFMhJNPyCTwOKIAXw03eVZYFkt3OgaQaHx51vzvHYUQoW0 uLog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1762469979; x=1763074779; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=DcNqxELVDSK7RhV1ekY6lA9dpVwVz2jR8jDfVBLjBqs=; b=p8t9/KZ8cULMdR4gl5zH6UcyrP4VBq4YRhUUxWDWZRE6Q9qFkdNwRBN3FM33gY7Kbd Au5XsqH21aBHfxSXEgCFFUpdFj55ZV4n+6FTtMaLMHOlTp/hyh2nxASL1Rlef362eLhA nk3HQ0kvcLmek8Te9/JilBaFzkycxRumYwuUxMPLG+hCevlMNPGNBXtlzOHXoY22FkMx zSyR9V2JKsioBCqlr6al0OvtzK6Bk8h0HAqoIxTnmEsgI0MVx78nk53e9KPUZ2mnohf+ BWs5Sjsmmh+w9N82LQ0/oxZ7d+gGTmw7MHTZNAZQMhCiRO+u4tBqeac3HCa7E+oDmmHg 9XyA== X-Forwarded-Encrypted: i=1; AJvYcCX0CJJ8RpZAooMWs4m8gxtv58jIztb9jcTePPMDsaseHYbpjAPkQszgYzDqDo9ZJTczk9TkarAItQ==@vger.kernel.org X-Gm-Message-State: AOJu0Ywvo7bjjMlUgFBCnaaQWIDfkBKdk2yUbRWIxCXHTO78oLUct9WJ d/TAvM701JHlhApwIeOZap/HJFj0I54w8ptAU0e6Fsw4OP0D7JBn5a0F X-Gm-Gg: ASbGncsd9QFTrlM2C57gezGlp1FSBYlFKr+Wfy+C9FRUVJ1mjTaqAmM5CM3AAiSJmdk SueBc4f0GNmMNCp8TKsK8HMhomExECzKSG7/G8QL6i4fJkZo+cHW3KUMuplZiM6f58QDwh26ZSQ NQxGxHOVrgwlXuce7Xsp5Dv+UAyBQMPPCb/6Kj/cMasWnlXusvtyFZd0jh28sWUEwEBu+siuQKO 8Zx84kPD0u63utGUh+1tYyIx0p1IC4IOcInDAr4+3iI75vZSxuHwgT3f2UsKW6UwiIPaR8ZEMER TRZQ/gxnsSDcT0t/g7czM7YtJBEmTA5TgVYwAFuy94vcTdT1SCGRqqRmtN1CWiCHT41ZQYzgZ54 qI8lp4WAKVB1JSY9rdXH45sG+bT4hQnRuTEQ85KVibQi2LVi7T/mOy2pptHWi3gjnW3H6qRSvHc qpDdLh8u/1A1wm9+lWttSk8mugMHjTSg== X-Google-Smtp-Source: AGHT+IF0RVDx0rGAdoRCaZtp3Ji9kzDVVQPOYw+EacR7N0DDTcC02D7/7z7qNkmWA+StqlM6DGi6Xw== X-Received: by 2002:a05:600c:b8d:b0:471:115e:624b with SMTP id 5b1f17b1804b1-4776bca4c9emr8667645e9.17.1762469978539; Thu, 06 Nov 2025 14:59:38 -0800 (PST) Received: from Ansuel-XPS24 (93-34-90-37.ip49.fastwebnet.it. [93.34.90.37]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-42ac6794f63sm1640000f8f.42.2025.11.06.14.59.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Nov 2025 14:59:38 -0800 (PST) From: Christian Marangi To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Christian Marangi , Lorenzo Bianconi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v3 1/5] thermal/drivers: airoha: Convert to regmap API Date: Thu, 6 Nov 2025 23:59:10 +0100 Message-ID: <20251106225929.1778398-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251106225929.1778398-1-ansuelsmth@gmail.com> References: <20251106225929.1778398-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In preparation for support of Airoha AN7583, convert the driver to regmap API. This is needed as Airoha AN7583 will be based on syscon regmap. Signed-off-by: Christian Marangi --- drivers/thermal/airoha_thermal.c | 72 +++++++++++++++++++------------- 1 file changed, 42 insertions(+), 30 deletions(-) diff --git a/drivers/thermal/airoha_thermal.c b/drivers/thermal/airoha_thermal.c index b9fd6bfc88e5..01ed49a4887e 100644 --- a/drivers/thermal/airoha_thermal.c +++ b/drivers/thermal/airoha_thermal.c @@ -194,7 +194,7 @@ #define AIROHA_MAX_SAMPLES 6 struct airoha_thermal_priv { - void __iomem *base; + struct regmap *map; struct regmap *chip_scu; struct resource scu_adc_res; @@ -265,8 +265,8 @@ static int airoha_thermal_set_trips(struct thermal_zone_device *tz, int low, RAW_TO_TEMP(priv, FIELD_MAX(EN7581_DOUT_TADC_MASK))); /* We offset the high temp of 1°C to trigger correct event */ - writel(TEMP_TO_RAW(priv, high) >> 4, - priv->base + EN7581_TEMPOFFSETH); + regmap_write(priv->map, EN7581_TEMPOFFSETH, + TEMP_TO_RAW(priv, high) >> 4); enable_monitor = true; } @@ -277,15 +277,15 @@ static int airoha_thermal_set_trips(struct thermal_zone_device *tz, int low, RAW_TO_TEMP(priv, FIELD_MAX(EN7581_DOUT_TADC_MASK))); /* We offset the low temp of 1°C to trigger correct event */ - writel(TEMP_TO_RAW(priv, low) >> 4, - priv->base + EN7581_TEMPOFFSETL); + regmap_write(priv->map, EN7581_TEMPOFFSETL, + TEMP_TO_RAW(priv, high) >> 4); enable_monitor = true; } /* Enable sensor 0 monitor after trip are set */ if (enable_monitor) - writel(EN7581_SENSE0_EN, priv->base + EN7581_TEMPMONCTL0); + regmap_write(priv->map, EN7581_TEMPMONCTL0, EN7581_SENSE0_EN); return 0; } @@ -302,7 +302,7 @@ static irqreturn_t airoha_thermal_irq(int irq, void *data) bool update = false; u32 status; - status = readl(priv->base + EN7581_TEMPMONINTSTS); + regmap_read(priv->map, EN7581_TEMPMONINTSTS, &status); switch (status & (EN7581_HOFSINTSTS0 | EN7581_LOFSINTSTS0)) { case EN7581_HOFSINTSTS0: event = THERMAL_TRIP_VIOLATED; @@ -318,7 +318,7 @@ static irqreturn_t airoha_thermal_irq(int irq, void *data) } /* Reset Interrupt */ - writel(status, priv->base + EN7581_TEMPMONINTSTS); + regmap_write(priv->map, EN7581_TEMPMONINTSTS, status); if (update) thermal_zone_device_update(priv->tz, event); @@ -336,11 +336,11 @@ static void airoha_thermal_setup_adc_val(struct device *dev, /* sleep 10 ms for ADC to enable */ usleep_range(10 * USEC_PER_MSEC, 11 * USEC_PER_MSEC); - efuse_calib_info = readl(priv->base + EN7581_EFUSE_TEMP_OFFSET_REG); + regmap_read(priv->map, EN7581_EFUSE_TEMP_OFFSET_REG, &efuse_calib_info); if (efuse_calib_info) { priv->default_offset = FIELD_GET(EN7581_EFUSE_TEMP_OFFSET, efuse_calib_info); /* Different slope are applied if the sensor is used for CPU or for package */ - cpu_sensor = readl(priv->base + EN7581_EFUSE_TEMP_CPU_SENSOR_REG); + regmap_read(priv->map, EN7581_EFUSE_TEMP_CPU_SENSOR_REG, &cpu_sensor); if (cpu_sensor) { priv->default_slope = EN7581_SLOPE_X100_DIO_DEFAULT; priv->init_temp = EN7581_INIT_TEMP_FTK_X10; @@ -359,8 +359,8 @@ static void airoha_thermal_setup_adc_val(struct device *dev, static void airoha_thermal_setup_monitor(struct airoha_thermal_priv *priv) { /* Set measure mode */ - writel(FIELD_PREP(EN7581_MSRCTL0, EN7581_MSRCTL_6SAMPLE_MAX_MIX_AVG4), - priv->base + EN7581_TEMPMSRCTL0); + regmap_write(priv->map, EN7581_TEMPMSRCTL0, + FIELD_PREP(EN7581_MSRCTL0, EN7581_MSRCTL_6SAMPLE_MAX_MIX_AVG4)); /* * Configure ADC valid reading addr @@ -375,15 +375,15 @@ static void airoha_thermal_setup_monitor(struct airoha_thermal_priv *priv) * We set valid instead of volt as we don't enable valid/volt * split reading and AHB read valid addr in such case. */ - writel(priv->scu_adc_res.start + EN7581_DOUT_TADC, - priv->base + EN7581_TEMPADCVALIDADDR); + regmap_write(priv->map, EN7581_TEMPADCVALIDADDR, + priv->scu_adc_res.start + EN7581_DOUT_TADC); /* * Configure valid bit on a fake value of bit 16. The ADC outputs * max of 2 bytes for voltage. */ - writel(FIELD_PREP(EN7581_ADV_RD_VALID_POS, 16), - priv->base + EN7581_TEMPADCVALIDMASK); + regmap_write(priv->map, EN7581_TEMPADCVALIDMASK, + FIELD_PREP(EN7581_ADV_RD_VALID_POS, 16)); /* * AHB supports max 12 bytes for ADC voltage. Shift the read @@ -391,40 +391,52 @@ static void airoha_thermal_setup_monitor(struct airoha_thermal_priv *priv) * in the order of half a °C and is acceptable in the context * of triggering interrupt in critical condition. */ - writel(FIELD_PREP(EN7581_ADC_VOLTAGE_SHIFT, 4), - priv->base + EN7581_TEMPADCVOLTAGESHIFT); + regmap_write(priv->map, EN7581_TEMPADCVOLTAGESHIFT, + FIELD_PREP(EN7581_ADC_VOLTAGE_SHIFT, 4)); /* BUS clock is 300MHz counting unit is 3 * 68.64 * 256 = 52.715us */ - writel(FIELD_PREP(EN7581_PERIOD_UNIT, 3), - priv->base + EN7581_TEMPMONCTL1); + regmap_write(priv->map, EN7581_TEMPMONCTL1, + FIELD_PREP(EN7581_PERIOD_UNIT, 3)); /* * filt interval is 1 * 52.715us = 52.715us, * sen interval is 379 * 52.715us = 19.97ms */ - writel(FIELD_PREP(EN7581_FILT_INTERVAL, 1) | - FIELD_PREP(EN7581_FILT_INTERVAL, 379), - priv->base + EN7581_TEMPMONCTL2); + regmap_write(priv->map, EN7581_TEMPMONCTL2, + FIELD_PREP(EN7581_FILT_INTERVAL, 1) | + FIELD_PREP(EN7581_FILT_INTERVAL, 379)); /* AHB poll is set to 146 * 68.64 = 10.02us */ - writel(FIELD_PREP(EN7581_ADC_POLL_INTVL, 146), - priv->base + EN7581_TEMPAHBPOLL); + regmap_write(priv->map, EN7581_TEMPAHBPOLL, + FIELD_PREP(EN7581_ADC_POLL_INTVL, 146)); } +static const struct regmap_config airoha_thermal_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, +}; + static int airoha_thermal_probe(struct platform_device *pdev) { struct airoha_thermal_priv *priv; struct device_node *chip_scu_np; struct device *dev = &pdev->dev; + void __iomem *base; int irq, ret; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; - priv->base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(priv->base)) - return PTR_ERR(priv->base); + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + priv->map = devm_regmap_init_mmio(dev, base, + &airoha_thermal_regmap_config); + if (IS_ERR(priv->map)) + return PTR_ERR(priv->map); chip_scu_np = of_parse_phandle(dev->of_node, "airoha,chip-scu", 0); if (!chip_scu_np) @@ -462,8 +474,8 @@ static int airoha_thermal_probe(struct platform_device *pdev) platform_set_drvdata(pdev, priv); /* Enable LOW and HIGH interrupt */ - writel(EN7581_HOFSINTEN0 | EN7581_LOFSINTEN0, - priv->base + EN7581_TEMPMONINT); + regmap_write(priv->map, EN7581_TEMPMONINT, + EN7581_HOFSINTEN0 | EN7581_LOFSINTEN0); return 0; } -- 2.51.0