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Wysocki" , , Vincent Guittot , Peter Zijlstra , Kevin Hilman , Pavel Machek , Len Brown , Daniel Lezcano , Maulik Shah , "Prasad Sodagudi" , Deepti Jaggi , , Jonathan Corbet Subject: Re: [PATCH v3 6/6] Documentation: power/cpuidle: Document the CPU system wakeup latency QoS Message-ID: <20251124183648.ud4emydldv75xr33@lcpd911> References: <20251121100315.316300-1-ulf.hansson@linaro.org> <20251121100315.316300-7-ulf.hansson@linaro.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20251121100315.316300-7-ulf.hansson@linaro.org> X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0001708E:EE_|DS0PR10MB7398:EE_ X-MS-Office365-Filtering-Correlation-Id: 1c7c8d3c-fff4-468b-cb40-08de2b886f1b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|7416014|376014|82310400026|1800799024|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?BawtZx4+g6oCpJeX9zkUl6tbKokz3LrrKwuJwPoC+rdTq51BG6PMrgrvHzqP?= =?us-ascii?Q?DqSRj5BGSAHVHVnxhmbs3ZtrSX5Mzl9PS317UccWH2bAOGAj3tBWD1sQXNQ5?= =?us-ascii?Q?3C5lQobs7nbk+6zn/v3EyfYG7vSXiMyjf2zdqaquuGL2u1NE5M0BFUmuPjBe?= =?us-ascii?Q?VvuNUizoUa2cEScmcoz+3qHFzOL9Faxz4n25ppcdTllAOXU4tRRaRgxjWNE9?= =?us-ascii?Q?9MyLpwg7zgANc+1bYu1qvKyR8S1cdZFdYzxsdS1ymRUfgO7FxYf5261ztlWC?= =?us-ascii?Q?qS24tw6S6nYwBbB6dShmM9MWcu1mD9MdlKERa62BxTSvkLewW6bcEEzud8pS?= =?us-ascii?Q?Ky8VWuZLhk9z43qcuEVPrYFij/EqFOR0zhNngb9YR8h12dxHYeq/ueYHi5VQ?= =?us-ascii?Q?w540hA79zE8Fka/giUMF9RpF+1biPvnkXU4vnQ7IwYdkloKrKMfRVVTR+WQF?= =?us-ascii?Q?R/XPanaIf458zVmH44a/8QKs8/3wIl6oo0LsC9nT8pjBf+QDTCG7cvMICWqT?= =?us-ascii?Q?yrtgTWSaes1pQXOR48sFrs7ViDQP1PwgYDiMJe8vzEjsbPssiZjzic5U9HmP?= =?us-ascii?Q?rBFm/5VYdMBf8kJ51WEkSB1EoTi0cZX2DW8XfVWLZuK8uJQniDv4Fgjzp529?= =?us-ascii?Q?t7yGQYBtbWdQXZBCc9HOJK8eJRrSBvasa3TljG7Fwgzfqx7Uc1+a+n1P8uLM?= =?us-ascii?Q?qeexEkS6RKFCii4eOWcswRtPV8kR3dLFpYisCUoAIxRJQDAIfpD4SQE9KkCU?= =?us-ascii?Q?VBLqq0HSgyCJuThZT309evhKIpcAc0fRl9puCGHdrZCJ6qn2fYFl09Ms3LDa?= =?us-ascii?Q?sN65MEsf3Z2lAWgY0YeRbNPhgzICbE2hKdeobqwy2z2sAFV2AZHvliQLv9Bb?= =?us-ascii?Q?EzbrnQCb7ZQWsm7rRxurAkZZj/Y3Lxz+xTh41tw8z19yNaVxahUiYv6Zv1Sk?= =?us-ascii?Q?TbKZ01kPvz5b0LNlHbnGmQFNXb+uwCPRJYbIF/slkcGOQ4YK8fNNN/dLMy5z?= =?us-ascii?Q?MplABO7NFIqandpLnztOnl1InVfT+1PTy7o9aunpIi9ZxO+QmqbWG3ilmNuw?= =?us-ascii?Q?UxY7RW+4FYn93tI6Q65JthgH1LsJ+Hu3VR0bsdy4yWj8PxFtm3UHdowXaunl?= =?us-ascii?Q?uMh3bLxZtmdrXA7SfCoY4ArkY7niLQsMALOfms3A31TGb0cfuyFoWknA60Jp?= =?us-ascii?Q?JyBelZ2TJxcsZYOwvSAlf2TPWHVWWYDIBr7qvEQNwfnLJfPEg7lbnvI8zkiO?= =?us-ascii?Q?U7xrUIcanbmmot4sUONcwvg/JbSTaZf/4kiEBBXgp5iO4Rb+aomh5FmeTYGk?= =?us-ascii?Q?z5IRz+dBCSce1+lv/jA7e6gHg4IoiYTul17FeAIj3FXmHPzS4gAI2MpOg4wo?= =?us-ascii?Q?YfQgDMqqvDQ6dJsQCx1lyvSb1Tkts1C4xv6YdlE7YFUWtVo0B9QYoAUeRFyU?= =?us-ascii?Q?7amIRiw/myQyhVJpY2hbJk5Jl1sR+DEhejPQHkCcZ9XfQxuLmQSTDQqVV8s0?= =?us-ascii?Q?neimTGa1i6qvlMZq96BfNZYlcKxNoCHrLgZuteexVSyNt5lRUavuZwaJlzhk?= =?us-ascii?Q?sQIvwps59wM3UyedRDg=3D?= X-Forefront-Antispam-Report: CIP:198.47.21.194;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:flwvzet200.ext.ti.com;PTR:ErrorRetry;CAT:NONE;SFS:(13230040)(36860700013)(7416014)(376014)(82310400026)(1800799024)(7053199007);DIR:OUT;SFP:1101; X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Nov 2025 18:36:51.1909 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1c7c8d3c-fff4-468b-cb40-08de2b886f1b X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.194];Helo=[flwvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001708E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR10MB7398 On Nov 21, 2025 at 11:03:12 +0100, Ulf Hansson wrote: > Let's document how the new CPU system wakeup latency QoS limit can be used > from user space, along with how the constraint is taken into account for > s2idle and cpuidle. > > Cc: Jonathan Corbet > Signed-off-by: Ulf Hansson > --- > > Changes in v3: > - Improved documentation. > - Updated commit message. > > Changes in v2: > - New patch. > > --- > Documentation/admin-guide/pm/cpuidle.rst | 9 +++++++++ > Documentation/power/pm_qos_interface.rst | 9 +++++---- > 2 files changed, 14 insertions(+), 4 deletions(-) > > diff --git a/Documentation/admin-guide/pm/cpuidle.rst b/Documentation/admin-guide/pm/cpuidle.rst > index 0c090b076224..c39ad6ab99d9 100644 > --- a/Documentation/admin-guide/pm/cpuidle.rst > +++ b/Documentation/admin-guide/pm/cpuidle.rst > @@ -580,6 +580,15 @@ the given CPU as the upper limit for the exit latency of the idle states that > they are allowed to select for that CPU. They should never select any idle > states with exit latency beyond that limit. > > +While the above CPU QoS constraints applies to CPU idle time management, user Nit: s/applies/apply > +space may also request a CPU system wakeup latency QoS limit, via the > +`cpu_wakeup_latency` file. This QoS constraint is respected when selecting a > +suitable idle state for the CPUs, while entering the system-wide suspend-to-idle > +sleep state, but also to the regular CPU idle time management. > + > +Note that, the management of the `cpu_wakeup_latency` file works according to > +the 'cpu_dma_latency' file from user space point of view. Moreover, the unit > +is also microseconds. > > Idle States Control Via Kernel Command Line > =========================================== > diff --git a/Documentation/power/pm_qos_interface.rst b/Documentation/power/pm_qos_interface.rst > index 5019c79c7710..4c008e2202f0 100644 > --- a/Documentation/power/pm_qos_interface.rst > +++ b/Documentation/power/pm_qos_interface.rst > @@ -55,7 +55,8 @@ int cpu_latency_qos_request_active(handle): > > From user space: > > -The infrastructure exposes one device node, /dev/cpu_dma_latency, for the CPU > +The infrastructure exposes two separate device nodes, /dev/cpu_dma_latency for > +the CPU latency QoS and /dev/cpu_wakeup_latency for the CPU system wakeup > latency QoS. > > Only processes can register a PM QoS request. To provide for automatic > @@ -63,15 +64,15 @@ cleanup of a process, the interface requires the process to register its > parameter requests as follows. > > To register the default PM QoS target for the CPU latency QoS, the process must > -open /dev/cpu_dma_latency. > +open /dev/cpu_dma_latency. To register a CPU system wakeup QoS limit, the > +process must open /dev/cpu_wakeup_latency. > > As long as the device node is held open that process has a registered > request on the parameter. > > To change the requested target value, the process needs to write an s32 value to > the open device node. Alternatively, it can write a hex string for the value > -using the 10 char long format e.g. "0x12345678". This translates to a > -cpu_latency_qos_update_request() call. > +using the 10 char long format e.g. "0x12345678". LGTM, Reviewed-by: Dhruva Gole -- Best regards, Dhruva Gole Texas Instruments Incorporated