* [PATCH v1 1/9] powercap: intel_rapl: Add a symbol namespace for intel_rapl exports
2026-01-29 18:36 [PATCH v1 0/9] Move RAPL defaults to interface drivers Kuppuswamy Sathyanarayanan
@ 2026-01-29 18:36 ` Kuppuswamy Sathyanarayanan
2026-01-29 18:36 ` [PATCH v1 2/9] powercap: intel_rapl: Cleanup coding style Kuppuswamy Sathyanarayanan
` (8 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Kuppuswamy Sathyanarayanan @ 2026-01-29 18:36 UTC (permalink / raw)
To: Rafael J . Wysocki, Daniel Lezcano
Cc: Zhang Rui, Lukasz Luba, Srinivas Pandruvada, linux-pm,
linux-kernel
Cleanup of the intel_rapl common driver requires introducing additional
exported helper and lifecycle functions. Before adding new exports,
create a dedicated symbol namespace for intel_rapl and update the
relevant interface drivers to explicitly import it.
This makes the intended usage of these symbols explicit, avoids
polluting the global namespace, and prepares the codebase for the
ongoing RAPL refactoring.
No functional changes are intended.
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
---
drivers/powercap/intel_rapl_common.c | 20 +++++++++----------
drivers/powercap/intel_rapl_msr.c | 1 +
drivers/powercap/intel_rapl_tpmi.c | 1 +
.../int340x_thermal/processor_thermal_rapl.c | 1 +
4 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_rapl_common.c
index 3ff6da3bf4e6..3471cee7ac04 100644
--- a/drivers/powercap/intel_rapl_common.c
+++ b/drivers/powercap/intel_rapl_common.c
@@ -2089,7 +2089,7 @@ int rapl_package_add_pmu_locked(struct rapl_package *rp)
return rapl_pmu_update(rp);
}
-EXPORT_SYMBOL_GPL(rapl_package_add_pmu_locked);
+EXPORT_SYMBOL_NS_GPL(rapl_package_add_pmu_locked, "INTEL_RAPL");
int rapl_package_add_pmu(struct rapl_package *rp)
{
@@ -2097,7 +2097,7 @@ int rapl_package_add_pmu(struct rapl_package *rp)
return rapl_package_add_pmu_locked(rp);
}
-EXPORT_SYMBOL_GPL(rapl_package_add_pmu);
+EXPORT_SYMBOL_NS_GPL(rapl_package_add_pmu, "INTEL_RAPL");
void rapl_package_remove_pmu_locked(struct rapl_package *rp)
{
@@ -2115,7 +2115,7 @@ void rapl_package_remove_pmu_locked(struct rapl_package *rp)
perf_pmu_unregister(&rapl_pmu.pmu);
memset(&rapl_pmu, 0, sizeof(struct rapl_pmu));
}
-EXPORT_SYMBOL_GPL(rapl_package_remove_pmu_locked);
+EXPORT_SYMBOL_NS_GPL(rapl_package_remove_pmu_locked, "INTEL_RAPL");
void rapl_package_remove_pmu(struct rapl_package *rp)
{
@@ -2123,7 +2123,7 @@ void rapl_package_remove_pmu(struct rapl_package *rp)
rapl_package_remove_pmu_locked(rp);
}
-EXPORT_SYMBOL_GPL(rapl_package_remove_pmu);
+EXPORT_SYMBOL_NS_GPL(rapl_package_remove_pmu, "INTEL_RAPL");
#endif
/* called from CPU hotplug notifier, hotplug lock held */
@@ -2156,14 +2156,14 @@ void rapl_remove_package_cpuslocked(struct rapl_package *rp)
list_del(&rp->plist);
kfree(rp);
}
-EXPORT_SYMBOL_GPL(rapl_remove_package_cpuslocked);
+EXPORT_SYMBOL_NS_GPL(rapl_remove_package_cpuslocked, "INTEL_RAPL");
void rapl_remove_package(struct rapl_package *rp)
{
guard(cpus_read_lock)();
rapl_remove_package_cpuslocked(rp);
}
-EXPORT_SYMBOL_GPL(rapl_remove_package);
+EXPORT_SYMBOL_NS_GPL(rapl_remove_package, "INTEL_RAPL");
/*
* RAPL Package energy counter scope:
@@ -2206,14 +2206,14 @@ struct rapl_package *rapl_find_package_domain_cpuslocked(int id, struct rapl_if_
return NULL;
}
-EXPORT_SYMBOL_GPL(rapl_find_package_domain_cpuslocked);
+EXPORT_SYMBOL_NS_GPL(rapl_find_package_domain_cpuslocked, "INTEL_RAPL");
struct rapl_package *rapl_find_package_domain(int id, struct rapl_if_priv *priv, bool id_is_cpu)
{
guard(cpus_read_lock)();
return rapl_find_package_domain_cpuslocked(id, priv, id_is_cpu);
}
-EXPORT_SYMBOL_GPL(rapl_find_package_domain);
+EXPORT_SYMBOL_NS_GPL(rapl_find_package_domain, "INTEL_RAPL");
/* called from CPU hotplug notifier, hotplug lock held */
struct rapl_package *rapl_add_package_cpuslocked(int id, struct rapl_if_priv *priv, bool id_is_cpu)
@@ -2267,14 +2267,14 @@ struct rapl_package *rapl_add_package_cpuslocked(int id, struct rapl_if_priv *pr
kfree(rp);
return ERR_PTR(ret);
}
-EXPORT_SYMBOL_GPL(rapl_add_package_cpuslocked);
+EXPORT_SYMBOL_NS_GPL(rapl_add_package_cpuslocked, "INTEL_RAPL");
struct rapl_package *rapl_add_package(int id, struct rapl_if_priv *priv, bool id_is_cpu)
{
guard(cpus_read_lock)();
return rapl_add_package_cpuslocked(id, priv, id_is_cpu);
}
-EXPORT_SYMBOL_GPL(rapl_add_package);
+EXPORT_SYMBOL_NS_GPL(rapl_add_package, "INTEL_RAPL");
static void power_limit_state_save(void)
{
diff --git a/drivers/powercap/intel_rapl_msr.c b/drivers/powercap/intel_rapl_msr.c
index 9a7e150b3536..6f23e601832d 100644
--- a/drivers/powercap/intel_rapl_msr.c
+++ b/drivers/powercap/intel_rapl_msr.c
@@ -264,3 +264,4 @@ module_platform_driver(intel_rapl_msr_driver);
MODULE_DESCRIPTION("Driver for Intel RAPL (Running Average Power Limit) control via MSR interface");
MODULE_AUTHOR("Zhang Rui <rui.zhang@intel.com>");
MODULE_LICENSE("GPL v2");
+MODULE_IMPORT_NS("INTEL_RAPL");
diff --git a/drivers/powercap/intel_rapl_tpmi.c b/drivers/powercap/intel_rapl_tpmi.c
index 0a0b85f4528b..3b52403c14f8 100644
--- a/drivers/powercap/intel_rapl_tpmi.c
+++ b/drivers/powercap/intel_rapl_tpmi.c
@@ -348,6 +348,7 @@ static struct auxiliary_driver intel_rapl_tpmi_driver = {
module_auxiliary_driver(intel_rapl_tpmi_driver)
+MODULE_IMPORT_NS("INTEL_RAPL");
MODULE_IMPORT_NS("INTEL_TPMI");
MODULE_DESCRIPTION("Intel RAPL TPMI Driver");
diff --git a/drivers/thermal/intel/int340x_thermal/processor_thermal_rapl.c b/drivers/thermal/intel/int340x_thermal/processor_thermal_rapl.c
index bf51a17c5be6..e56b18aeda71 100644
--- a/drivers/thermal/intel/int340x_thermal/processor_thermal_rapl.c
+++ b/drivers/thermal/intel/int340x_thermal/processor_thermal_rapl.c
@@ -111,4 +111,5 @@ void proc_thermal_rapl_remove(void)
EXPORT_SYMBOL_GPL(proc_thermal_rapl_remove);
MODULE_LICENSE("GPL v2");
+MODULE_IMPORT_NS("INTEL_RAPL");
MODULE_DESCRIPTION("RAPL interface using MMIO");
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v1 2/9] powercap: intel_rapl: Cleanup coding style
2026-01-29 18:36 [PATCH v1 0/9] Move RAPL defaults to interface drivers Kuppuswamy Sathyanarayanan
2026-01-29 18:36 ` [PATCH v1 1/9] powercap: intel_rapl: Add a symbol namespace for intel_rapl exports Kuppuswamy Sathyanarayanan
@ 2026-01-29 18:36 ` Kuppuswamy Sathyanarayanan
2026-01-29 18:36 ` [PATCH v1 3/9] powercap: intel_rapl: Use GENMASK() and BIT() macros Kuppuswamy Sathyanarayanan
` (7 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Kuppuswamy Sathyanarayanan @ 2026-01-29 18:36 UTC (permalink / raw)
To: Rafael J . Wysocki, Daniel Lezcano
Cc: Zhang Rui, Lukasz Luba, Srinivas Pandruvada, linux-pm,
linux-kernel
Improve code readability and consistency by:
- Aligning macro definitions vertically
- Reformatting primitive info arrays with consistent indentation
- Aligning CPU ID table entries
- Reorganizing macro definitions for better logical grouping
- Using consistent hex formatting (0x00 instead of 0)
- Capitalizing hex digits consistently (0xDF instead of 0xdf)
- Removing unnecessary parentheses around numeric constants
- Simplifying rapl_compute_time_window_atom() to remove redundant
assignments and clarify the to_raw/from_raw conversion paths
- Removing unused macros (TIME_WINDOW_MIN_MSEC & TIME_WINDOW_MAX_MSEC).
No functional changes.
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
---
drivers/powercap/intel_rapl_common.c | 453 ++++++++++++++-------------
1 file changed, 228 insertions(+), 225 deletions(-)
diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_rapl_common.c
index 3471cee7ac04..74a74af8f0ec 100644
--- a/drivers/powercap/intel_rapl_common.c
+++ b/drivers/powercap/intel_rapl_common.c
@@ -31,70 +31,92 @@
#include <asm/msr.h>
/* bitmasks for RAPL MSRs, used by primitive access functions */
-#define ENERGY_STATUS_MASK 0xffffffff
+#define ENERGY_STATUS_MASK 0xffffffff
-#define POWER_LIMIT1_MASK 0x7FFF
-#define POWER_LIMIT1_ENABLE BIT(15)
-#define POWER_LIMIT1_CLAMP BIT(16)
+#define POWER_LIMIT1_MASK 0x7FFF
+#define POWER_LIMIT1_ENABLE BIT(15)
+#define POWER_LIMIT1_CLAMP BIT(16)
-#define POWER_LIMIT2_MASK (0x7FFFULL<<32)
-#define POWER_LIMIT2_ENABLE BIT_ULL(47)
-#define POWER_LIMIT2_CLAMP BIT_ULL(48)
-#define POWER_HIGH_LOCK BIT_ULL(63)
-#define POWER_LOW_LOCK BIT(31)
+#define POWER_LIMIT2_MASK (0x7FFFULL<<32)
+#define POWER_LIMIT2_ENABLE BIT_ULL(47)
+#define POWER_LIMIT2_CLAMP BIT_ULL(48)
+#define POWER_HIGH_LOCK BIT_ULL(63)
+#define POWER_LOW_LOCK BIT(31)
#define POWER_LIMIT4_MASK 0x1FFF
-#define TIME_WINDOW1_MASK (0x7FULL<<17)
-#define TIME_WINDOW2_MASK (0x7FULL<<49)
+#define TIME_WINDOW1_MASK (0x7FULL<<17)
+#define TIME_WINDOW2_MASK (0x7FULL<<49)
-#define POWER_UNIT_OFFSET 0
-#define POWER_UNIT_MASK 0x0F
+#define POWER_UNIT_OFFSET 0x00
+#define POWER_UNIT_MASK 0x0F
-#define ENERGY_UNIT_OFFSET 0x08
-#define ENERGY_UNIT_MASK 0x1F00
+#define ENERGY_UNIT_OFFSET 0x08
+#define ENERGY_UNIT_MASK 0x1F00
-#define TIME_UNIT_OFFSET 0x10
-#define TIME_UNIT_MASK 0xF0000
+#define TIME_UNIT_OFFSET 0x10
+#define TIME_UNIT_MASK 0xF0000
-#define POWER_INFO_MAX_MASK (0x7fffULL<<32)
-#define POWER_INFO_MIN_MASK (0x7fffULL<<16)
-#define POWER_INFO_MAX_TIME_WIN_MASK (0x3fULL<<48)
-#define POWER_INFO_THERMAL_SPEC_MASK 0x7fff
+#define POWER_INFO_MAX_MASK (0x7fffULL<<32)
+#define POWER_INFO_MIN_MASK (0x7fffULL<<16)
+#define POWER_INFO_MAX_TIME_WIN_MASK (0x3fULL<<48)
+#define POWER_INFO_THERMAL_SPEC_MASK 0x7fff
-#define PERF_STATUS_THROTTLE_TIME_MASK 0xffffffff
-#define PP_POLICY_MASK 0x1F
+#define PERF_STATUS_THROTTLE_TIME_MASK 0xffffffff
+#define PP_POLICY_MASK 0x1F
/*
* SPR has different layout for Psys Domain PowerLimit registers.
* There are 17 bits of PL1 and PL2 instead of 15 bits.
* The Enable bits and TimeWindow bits are also shifted as a result.
*/
-#define PSYS_POWER_LIMIT1_MASK 0x1FFFF
-#define PSYS_POWER_LIMIT1_ENABLE BIT(17)
+#define PSYS_POWER_LIMIT1_MASK 0x1FFFF
+#define PSYS_POWER_LIMIT1_ENABLE BIT(17)
-#define PSYS_POWER_LIMIT2_MASK (0x1FFFFULL<<32)
-#define PSYS_POWER_LIMIT2_ENABLE BIT_ULL(49)
+#define PSYS_POWER_LIMIT2_MASK (0x1FFFFULL<<32)
+#define PSYS_POWER_LIMIT2_ENABLE BIT_ULL(49)
-#define PSYS_TIME_WINDOW1_MASK (0x7FULL<<19)
-#define PSYS_TIME_WINDOW2_MASK (0x7FULL<<51)
+#define PSYS_TIME_WINDOW1_MASK (0x7FULL<<19)
+#define PSYS_TIME_WINDOW2_MASK (0x7FULL<<51)
/* bitmasks for RAPL TPMI, used by primitive access functions */
-#define TPMI_POWER_LIMIT_MASK 0x3FFFF
-#define TPMI_POWER_LIMIT_ENABLE BIT_ULL(62)
-#define TPMI_TIME_WINDOW_MASK (0x7FULL<<18)
-#define TPMI_INFO_SPEC_MASK 0x3FFFF
-#define TPMI_INFO_MIN_MASK (0x3FFFFULL << 18)
-#define TPMI_INFO_MAX_MASK (0x3FFFFULL << 36)
+#define TPMI_POWER_LIMIT_MASK 0x3FFFF
+#define TPMI_POWER_LIMIT_ENABLE BIT_ULL(62)
+#define TPMI_TIME_WINDOW_MASK (0x7FULL<<18)
+#define TPMI_INFO_SPEC_MASK 0x3FFFF
+#define TPMI_INFO_MIN_MASK (0x3FFFFULL << 18)
+#define TPMI_INFO_MAX_MASK (0x3FFFFULL << 36)
#define TPMI_INFO_MAX_TIME_WIN_MASK (0x7FULL << 54)
/* Non HW constants */
-#define RAPL_PRIMITIVE_DERIVED BIT(1) /* not from raw data */
-#define RAPL_PRIMITIVE_DUMMY BIT(2)
+#define RAPL_PRIMITIVE_DERIVED BIT(1) /* not from raw data */
+#define RAPL_PRIMITIVE_DUMMY BIT(2)
+
+#define ENERGY_UNIT_SCALE 1000 /* scale from driver unit to powercap unit */
+
+/* per domain data, some are optional */
+#define NR_RAW_PRIMITIVES (NR_RAPL_PRIMITIVES - 2)
+
+#define DOMAIN_STATE_INACTIVE BIT(0)
+#define DOMAIN_STATE_POWER_LIMIT_SET BIT(1)
+
+/* Sideband MBI registers */
+#define IOSF_CPU_POWER_BUDGET_CTL_BYT 0x02
+#define IOSF_CPU_POWER_BUDGET_CTL_TNG 0xDF
+
+#define PACKAGE_PLN_INT_SAVED BIT(0)
+#define MAX_PRIM_NAME 32
+
+/* TPMI Unit register has different layout */
+#define TPMI_POWER_UNIT_OFFSET POWER_UNIT_OFFSET
+#define TPMI_POWER_UNIT_MASK POWER_UNIT_MASK
+#define TPMI_ENERGY_UNIT_OFFSET 0x06
+#define TPMI_ENERGY_UNIT_MASK 0x7C0
+#define TPMI_TIME_UNIT_OFFSET 0x0C
+#define TPMI_TIME_UNIT_MASK 0xF000
+
+#define RAPL_EVENT_MASK GENMASK(7, 0)
-#define TIME_WINDOW_MAX_MSEC 40000
-#define TIME_WINDOW_MIN_MSEC 250
-#define ENERGY_UNIT_SCALE 1000 /* scale from driver unit to powercap unit */
enum unit_type {
ARBITRARY_UNIT, /* no translation */
POWER_UNIT,
@@ -102,12 +124,6 @@ enum unit_type {
TIME_UNIT,
};
-/* per domain data, some are optional */
-#define NR_RAW_PRIMITIVES (NR_RAPL_PRIMITIVES - 2)
-
-#define DOMAIN_STATE_INACTIVE BIT(0)
-#define DOMAIN_STATE_POWER_LIMIT_SET BIT(1)
-
static const char *pl_names[NR_POWER_LIMITS] = {
[POWER_LIMIT1] = "long_term",
[POWER_LIMIT2] = "short_term",
@@ -222,13 +238,6 @@ static struct rapl_defaults *get_defaults(struct rapl_package *rp)
return rp->priv->defaults;
}
-/* Sideband MBI registers */
-#define IOSF_CPU_POWER_BUDGET_CTL_BYT (0x2)
-#define IOSF_CPU_POWER_BUDGET_CTL_TNG (0xdf)
-
-#define PACKAGE_PLN_INT_SAVED BIT(0)
-#define MAX_PRIM_NAME (32)
-
/* per domain data. used to describe individual knobs such that access function
* can be consolidated into one instead of many inline functions.
*/
@@ -659,99 +668,104 @@ static u64 rapl_unit_xlate(struct rapl_domain *rd, enum unit_type type,
/* RAPL primitives for MSR and MMIO I/F */
static struct rapl_primitive_info rpi_msr[NR_RAPL_PRIMITIVES] = {
/* name, mask, shift, msr index, unit divisor */
- [POWER_LIMIT1] = PRIMITIVE_INFO_INIT(POWER_LIMIT1, POWER_LIMIT1_MASK, 0,
- RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
- [POWER_LIMIT2] = PRIMITIVE_INFO_INIT(POWER_LIMIT2, POWER_LIMIT2_MASK, 32,
- RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
- [POWER_LIMIT4] = PRIMITIVE_INFO_INIT(POWER_LIMIT4, POWER_LIMIT4_MASK, 0,
- RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0),
- [ENERGY_COUNTER] = PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0,
- RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0),
- [FW_LOCK] = PRIMITIVE_INFO_INIT(FW_LOCK, POWER_LOW_LOCK, 31,
- RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
- [FW_HIGH_LOCK] = PRIMITIVE_INFO_INIT(FW_LOCK, POWER_HIGH_LOCK, 63,
- RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
- [PL1_ENABLE] = PRIMITIVE_INFO_INIT(PL1_ENABLE, POWER_LIMIT1_ENABLE, 15,
- RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
- [PL1_CLAMP] = PRIMITIVE_INFO_INIT(PL1_CLAMP, POWER_LIMIT1_CLAMP, 16,
- RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
- [PL2_ENABLE] = PRIMITIVE_INFO_INIT(PL2_ENABLE, POWER_LIMIT2_ENABLE, 47,
- RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
- [PL2_CLAMP] = PRIMITIVE_INFO_INIT(PL2_CLAMP, POWER_LIMIT2_CLAMP, 48,
- RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
- [TIME_WINDOW1] = PRIMITIVE_INFO_INIT(TIME_WINDOW1, TIME_WINDOW1_MASK, 17,
- RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
- [TIME_WINDOW2] = PRIMITIVE_INFO_INIT(TIME_WINDOW2, TIME_WINDOW2_MASK, 49,
- RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
- [THERMAL_SPEC_POWER] = PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, POWER_INFO_THERMAL_SPEC_MASK,
- 0, RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
- [MAX_POWER] = PRIMITIVE_INFO_INIT(MAX_POWER, POWER_INFO_MAX_MASK, 32,
- RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
- [MIN_POWER] = PRIMITIVE_INFO_INIT(MIN_POWER, POWER_INFO_MIN_MASK, 16,
- RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
- [MAX_TIME_WINDOW] = PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, POWER_INFO_MAX_TIME_WIN_MASK, 48,
- RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0),
- [THROTTLED_TIME] = PRIMITIVE_INFO_INIT(THROTTLED_TIME, PERF_STATUS_THROTTLE_TIME_MASK, 0,
- RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0),
- [PRIORITY_LEVEL] = PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, PP_POLICY_MASK, 0,
- RAPL_DOMAIN_REG_POLICY, ARBITRARY_UNIT, 0),
- [PSYS_POWER_LIMIT1] = PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT1, PSYS_POWER_LIMIT1_MASK, 0,
- RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
- [PSYS_POWER_LIMIT2] = PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT2, PSYS_POWER_LIMIT2_MASK, 32,
- RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
- [PSYS_PL1_ENABLE] = PRIMITIVE_INFO_INIT(PSYS_PL1_ENABLE, PSYS_POWER_LIMIT1_ENABLE, 17,
- RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
- [PSYS_PL2_ENABLE] = PRIMITIVE_INFO_INIT(PSYS_PL2_ENABLE, PSYS_POWER_LIMIT2_ENABLE, 49,
- RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
- [PSYS_TIME_WINDOW1] = PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW1, PSYS_TIME_WINDOW1_MASK, 19,
- RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
- [PSYS_TIME_WINDOW2] = PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW2, PSYS_TIME_WINDOW2_MASK, 51,
- RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
+ [POWER_LIMIT1] = PRIMITIVE_INFO_INIT(POWER_LIMIT1, POWER_LIMIT1_MASK, 0,
+ RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
+ [POWER_LIMIT2] = PRIMITIVE_INFO_INIT(POWER_LIMIT2, POWER_LIMIT2_MASK, 32,
+ RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
+ [POWER_LIMIT4] = PRIMITIVE_INFO_INIT(POWER_LIMIT4, POWER_LIMIT4_MASK, 0,
+ RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0),
+ [ENERGY_COUNTER] = PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0,
+ RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0),
+ [FW_LOCK] = PRIMITIVE_INFO_INIT(FW_LOCK, POWER_LOW_LOCK, 31,
+ RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
+ [FW_HIGH_LOCK] = PRIMITIVE_INFO_INIT(FW_LOCK, POWER_HIGH_LOCK, 63,
+ RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
+ [PL1_ENABLE] = PRIMITIVE_INFO_INIT(PL1_ENABLE, POWER_LIMIT1_ENABLE, 15,
+ RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
+ [PL1_CLAMP] = PRIMITIVE_INFO_INIT(PL1_CLAMP, POWER_LIMIT1_CLAMP, 16,
+ RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
+ [PL2_ENABLE] = PRIMITIVE_INFO_INIT(PL2_ENABLE, POWER_LIMIT2_ENABLE, 47,
+ RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
+ [PL2_CLAMP] = PRIMITIVE_INFO_INIT(PL2_CLAMP, POWER_LIMIT2_CLAMP, 48,
+ RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
+ [TIME_WINDOW1] = PRIMITIVE_INFO_INIT(TIME_WINDOW1, TIME_WINDOW1_MASK, 17,
+ RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
+ [TIME_WINDOW2] = PRIMITIVE_INFO_INIT(TIME_WINDOW2, TIME_WINDOW2_MASK, 49,
+ RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
+ [THERMAL_SPEC_POWER] = PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER,
+ POWER_INFO_THERMAL_SPEC_MASK, 0,
+ RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
+ [MAX_POWER] = PRIMITIVE_INFO_INIT(MAX_POWER, POWER_INFO_MAX_MASK, 32,
+ RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
+ [MIN_POWER] = PRIMITIVE_INFO_INIT(MIN_POWER, POWER_INFO_MIN_MASK, 16,
+ RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
+ [MAX_TIME_WINDOW] = PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW,
+ POWER_INFO_MAX_TIME_WIN_MASK, 48,
+ RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0),
+ [THROTTLED_TIME] = PRIMITIVE_INFO_INIT(THROTTLED_TIME,
+ PERF_STATUS_THROTTLE_TIME_MASK, 0,
+ RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0),
+ [PRIORITY_LEVEL] = PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, PP_POLICY_MASK, 0,
+ RAPL_DOMAIN_REG_POLICY, ARBITRARY_UNIT, 0),
+ [PSYS_POWER_LIMIT1] = PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT1, PSYS_POWER_LIMIT1_MASK, 0,
+ RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
+ [PSYS_POWER_LIMIT2] = PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT2, PSYS_POWER_LIMIT2_MASK,
+ 32, RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
+ [PSYS_PL1_ENABLE] = PRIMITIVE_INFO_INIT(PSYS_PL1_ENABLE, PSYS_POWER_LIMIT1_ENABLE,
+ 17, RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT,
+ 0),
+ [PSYS_PL2_ENABLE] = PRIMITIVE_INFO_INIT(PSYS_PL2_ENABLE, PSYS_POWER_LIMIT2_ENABLE,
+ 49, RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT,
+ 0),
+ [PSYS_TIME_WINDOW1] = PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW1, PSYS_TIME_WINDOW1_MASK,
+ 19, RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
+ [PSYS_TIME_WINDOW2] = PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW2, PSYS_TIME_WINDOW2_MASK,
+ 51, RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
/* non-hardware */
- [AVERAGE_POWER] = PRIMITIVE_INFO_INIT(AVERAGE_POWER, 0, 0, 0, POWER_UNIT,
- RAPL_PRIMITIVE_DERIVED),
+ [AVERAGE_POWER] = PRIMITIVE_INFO_INIT(AVERAGE_POWER, 0, 0, 0, POWER_UNIT,
+ RAPL_PRIMITIVE_DERIVED),
};
/* RAPL primitives for TPMI I/F */
static struct rapl_primitive_info rpi_tpmi[NR_RAPL_PRIMITIVES] = {
/* name, mask, shift, msr index, unit divisor */
- [POWER_LIMIT1] = PRIMITIVE_INFO_INIT(POWER_LIMIT1, TPMI_POWER_LIMIT_MASK, 0,
- RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
- [POWER_LIMIT2] = PRIMITIVE_INFO_INIT(POWER_LIMIT2, TPMI_POWER_LIMIT_MASK, 0,
- RAPL_DOMAIN_REG_PL2, POWER_UNIT, 0),
- [POWER_LIMIT4] = PRIMITIVE_INFO_INIT(POWER_LIMIT4, TPMI_POWER_LIMIT_MASK, 0,
- RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0),
- [ENERGY_COUNTER] = PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0,
- RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0),
- [PL1_LOCK] = PRIMITIVE_INFO_INIT(PL1_LOCK, POWER_HIGH_LOCK, 63,
- RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
- [PL2_LOCK] = PRIMITIVE_INFO_INIT(PL2_LOCK, POWER_HIGH_LOCK, 63,
- RAPL_DOMAIN_REG_PL2, ARBITRARY_UNIT, 0),
- [PL4_LOCK] = PRIMITIVE_INFO_INIT(PL4_LOCK, POWER_HIGH_LOCK, 63,
- RAPL_DOMAIN_REG_PL4, ARBITRARY_UNIT, 0),
- [PL1_ENABLE] = PRIMITIVE_INFO_INIT(PL1_ENABLE, TPMI_POWER_LIMIT_ENABLE, 62,
- RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
- [PL2_ENABLE] = PRIMITIVE_INFO_INIT(PL2_ENABLE, TPMI_POWER_LIMIT_ENABLE, 62,
- RAPL_DOMAIN_REG_PL2, ARBITRARY_UNIT, 0),
- [PL4_ENABLE] = PRIMITIVE_INFO_INIT(PL4_ENABLE, TPMI_POWER_LIMIT_ENABLE, 62,
- RAPL_DOMAIN_REG_PL4, ARBITRARY_UNIT, 0),
- [TIME_WINDOW1] = PRIMITIVE_INFO_INIT(TIME_WINDOW1, TPMI_TIME_WINDOW_MASK, 18,
- RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
- [TIME_WINDOW2] = PRIMITIVE_INFO_INIT(TIME_WINDOW2, TPMI_TIME_WINDOW_MASK, 18,
- RAPL_DOMAIN_REG_PL2, TIME_UNIT, 0),
- [THERMAL_SPEC_POWER] = PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, TPMI_INFO_SPEC_MASK, 0,
- RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
- [MAX_POWER] = PRIMITIVE_INFO_INIT(MAX_POWER, TPMI_INFO_MAX_MASK, 36,
- RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
- [MIN_POWER] = PRIMITIVE_INFO_INIT(MIN_POWER, TPMI_INFO_MIN_MASK, 18,
- RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
- [MAX_TIME_WINDOW] = PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, TPMI_INFO_MAX_TIME_WIN_MASK, 54,
- RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0),
- [THROTTLED_TIME] = PRIMITIVE_INFO_INIT(THROTTLED_TIME, PERF_STATUS_THROTTLE_TIME_MASK, 0,
- RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0),
+ [POWER_LIMIT1] = PRIMITIVE_INFO_INIT(POWER_LIMIT1, TPMI_POWER_LIMIT_MASK, 0,
+ RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
+ [POWER_LIMIT2] = PRIMITIVE_INFO_INIT(POWER_LIMIT2, TPMI_POWER_LIMIT_MASK, 0,
+ RAPL_DOMAIN_REG_PL2, POWER_UNIT, 0),
+ [POWER_LIMIT4] = PRIMITIVE_INFO_INIT(POWER_LIMIT4, TPMI_POWER_LIMIT_MASK, 0,
+ RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0),
+ [ENERGY_COUNTER] = PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0,
+ RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0),
+ [PL1_LOCK] = PRIMITIVE_INFO_INIT(PL1_LOCK, POWER_HIGH_LOCK, 63,
+ RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
+ [PL2_LOCK] = PRIMITIVE_INFO_INIT(PL2_LOCK, POWER_HIGH_LOCK, 63,
+ RAPL_DOMAIN_REG_PL2, ARBITRARY_UNIT, 0),
+ [PL4_LOCK] = PRIMITIVE_INFO_INIT(PL4_LOCK, POWER_HIGH_LOCK, 63,
+ RAPL_DOMAIN_REG_PL4, ARBITRARY_UNIT, 0),
+ [PL1_ENABLE] = PRIMITIVE_INFO_INIT(PL1_ENABLE, TPMI_POWER_LIMIT_ENABLE, 62,
+ RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
+ [PL2_ENABLE] = PRIMITIVE_INFO_INIT(PL2_ENABLE, TPMI_POWER_LIMIT_ENABLE, 62,
+ RAPL_DOMAIN_REG_PL2, ARBITRARY_UNIT, 0),
+ [PL4_ENABLE] = PRIMITIVE_INFO_INIT(PL4_ENABLE, TPMI_POWER_LIMIT_ENABLE, 62,
+ RAPL_DOMAIN_REG_PL4, ARBITRARY_UNIT, 0),
+ [TIME_WINDOW1] = PRIMITIVE_INFO_INIT(TIME_WINDOW1, TPMI_TIME_WINDOW_MASK, 18,
+ RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
+ [TIME_WINDOW2] = PRIMITIVE_INFO_INIT(TIME_WINDOW2, TPMI_TIME_WINDOW_MASK, 18,
+ RAPL_DOMAIN_REG_PL2, TIME_UNIT, 0),
+ [THERMAL_SPEC_POWER] = PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, TPMI_INFO_SPEC_MASK, 0,
+ RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
+ [MAX_POWER] = PRIMITIVE_INFO_INIT(MAX_POWER, TPMI_INFO_MAX_MASK, 36,
+ RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
+ [MIN_POWER] = PRIMITIVE_INFO_INIT(MIN_POWER, TPMI_INFO_MIN_MASK, 18,
+ RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
+ [MAX_TIME_WINDOW] = PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, TPMI_INFO_MAX_TIME_WIN_MASK,
+ 54, RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0),
+ [THROTTLED_TIME] = PRIMITIVE_INFO_INIT(THROTTLED_TIME, PERF_STATUS_THROTTLE_TIME_MASK,
+ 0, RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0),
/* non-hardware */
- [AVERAGE_POWER] = PRIMITIVE_INFO_INIT(AVERAGE_POWER, 0, 0, 0,
- POWER_UNIT, RAPL_PRIMITIVE_DERIVED),
+ [AVERAGE_POWER] = PRIMITIVE_INFO_INIT(AVERAGE_POWER, 0, 0, 0, POWER_UNIT,
+ RAPL_PRIMITIVE_DERIVED),
};
static struct rapl_primitive_info *get_rpi(struct rapl_package *rp, int prim)
@@ -1131,26 +1145,16 @@ static u64 rapl_compute_time_window_core(struct rapl_domain *rd, u64 value,
static u64 rapl_compute_time_window_atom(struct rapl_domain *rd, u64 value,
bool to_raw)
{
+ if (to_raw)
+ return div64_u64(value, rd->time_unit);
+
/*
* Atom time unit encoding is straight forward val * time_unit,
* where time_unit is default to 1 sec. Never 0.
*/
- if (!to_raw)
- return (value) ? value * rd->time_unit : rd->time_unit;
-
- value = div64_u64(value, rd->time_unit);
-
- return value;
+ return (value) ? value * rd->time_unit : rd->time_unit;
}
-/* TPMI Unit register has different layout */
-#define TPMI_POWER_UNIT_OFFSET POWER_UNIT_OFFSET
-#define TPMI_POWER_UNIT_MASK POWER_UNIT_MASK
-#define TPMI_ENERGY_UNIT_OFFSET 0x06
-#define TPMI_ENERGY_UNIT_MASK 0x7C0
-#define TPMI_TIME_UNIT_OFFSET 0x0C
-#define TPMI_TIME_UNIT_MASK 0xF000
-
static int rapl_check_unit_tpmi(struct rapl_domain *rd)
{
struct reg_action ra;
@@ -1241,77 +1245,77 @@ static const struct rapl_defaults rapl_defaults_amd = {
};
static const struct x86_cpu_id rapl_ids[] __initconst = {
- X86_MATCH_VFM(INTEL_SANDYBRIDGE, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_SANDYBRIDGE_X, &rapl_defaults_core),
-
- X86_MATCH_VFM(INTEL_IVYBRIDGE, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &rapl_defaults_core),
-
- X86_MATCH_VFM(INTEL_HASWELL, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_HASWELL_L, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_HASWELL_G, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_HASWELL_X, &rapl_defaults_hsw_server),
-
- X86_MATCH_VFM(INTEL_BROADWELL, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_BROADWELL_G, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_BROADWELL_D, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_BROADWELL_X, &rapl_defaults_hsw_server),
-
- X86_MATCH_VFM(INTEL_SKYLAKE, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_SKYLAKE_L, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_SKYLAKE_X, &rapl_defaults_hsw_server),
- X86_MATCH_VFM(INTEL_KABYLAKE_L, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_KABYLAKE, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_CANNONLAKE_L, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_ICELAKE_L, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_ICELAKE, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_ICELAKE_NNPI, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_ICELAKE_X, &rapl_defaults_hsw_server),
- X86_MATCH_VFM(INTEL_ICELAKE_D, &rapl_defaults_hsw_server),
- X86_MATCH_VFM(INTEL_COMETLAKE_L, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_COMETLAKE, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_TIGERLAKE_L, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_TIGERLAKE, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_ROCKETLAKE, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_ALDERLAKE, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_ALDERLAKE_L, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_RAPTORLAKE, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_RAPTORLAKE_P, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_RAPTORLAKE_S, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_BARTLETTLAKE, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_METEORLAKE, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_METEORLAKE_L, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &rapl_defaults_spr_server),
- X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &rapl_defaults_spr_server),
- X86_MATCH_VFM(INTEL_LUNARLAKE_M, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_WILDCATLAKE_L, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_NOVALAKE, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_NOVALAKE_L, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_ARROWLAKE_H, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_ARROWLAKE, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_ARROWLAKE_U, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_LAKEFIELD, &rapl_defaults_core),
-
- X86_MATCH_VFM(INTEL_ATOM_SILVERMONT, &rapl_defaults_byt),
- X86_MATCH_VFM(INTEL_ATOM_AIRMONT, &rapl_defaults_cht),
- X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID, &rapl_defaults_tng),
- X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID2,&rapl_defaults_ann),
- X86_MATCH_VFM(INTEL_ATOM_GOLDMONT, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_PLUS, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_D, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_ATOM_TREMONT, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_ATOM_TREMONT_D, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_ATOM_TREMONT_L, &rapl_defaults_core),
-
- X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &rapl_defaults_hsw_server),
- X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &rapl_defaults_hsw_server),
-
- X86_MATCH_VENDOR_FAM(AMD, 0x17, &rapl_defaults_amd),
- X86_MATCH_VENDOR_FAM(AMD, 0x19, &rapl_defaults_amd),
- X86_MATCH_VENDOR_FAM(AMD, 0x1A, &rapl_defaults_amd),
- X86_MATCH_VENDOR_FAM(HYGON, 0x18, &rapl_defaults_amd),
+ X86_MATCH_VFM(INTEL_SANDYBRIDGE, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_SANDYBRIDGE_X, &rapl_defaults_core),
+
+ X86_MATCH_VFM(INTEL_IVYBRIDGE, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &rapl_defaults_core),
+
+ X86_MATCH_VFM(INTEL_HASWELL, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_HASWELL_L, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_HASWELL_G, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_HASWELL_X, &rapl_defaults_hsw_server),
+
+ X86_MATCH_VFM(INTEL_BROADWELL, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_BROADWELL_G, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_BROADWELL_D, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_BROADWELL_X, &rapl_defaults_hsw_server),
+
+ X86_MATCH_VFM(INTEL_SKYLAKE, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_SKYLAKE_L, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_SKYLAKE_X, &rapl_defaults_hsw_server),
+ X86_MATCH_VFM(INTEL_KABYLAKE_L, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_KABYLAKE, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_CANNONLAKE_L, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_ICELAKE_L, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_ICELAKE, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_ICELAKE_NNPI, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_ICELAKE_X, &rapl_defaults_hsw_server),
+ X86_MATCH_VFM(INTEL_ICELAKE_D, &rapl_defaults_hsw_server),
+ X86_MATCH_VFM(INTEL_COMETLAKE_L, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_COMETLAKE, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_TIGERLAKE_L, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_TIGERLAKE, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_ROCKETLAKE, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_ALDERLAKE, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_ALDERLAKE_L, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_RAPTORLAKE, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_RAPTORLAKE_P, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_RAPTORLAKE_S, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_BARTLETTLAKE, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_METEORLAKE, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_METEORLAKE_L, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &rapl_defaults_spr_server),
+ X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &rapl_defaults_spr_server),
+ X86_MATCH_VFM(INTEL_LUNARLAKE_M, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_WILDCATLAKE_L, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_NOVALAKE, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_NOVALAKE_L, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_ARROWLAKE_H, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_ARROWLAKE, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_ARROWLAKE_U, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_LAKEFIELD, &rapl_defaults_core),
+
+ X86_MATCH_VFM(INTEL_ATOM_SILVERMONT, &rapl_defaults_byt),
+ X86_MATCH_VFM(INTEL_ATOM_AIRMONT, &rapl_defaults_cht),
+ X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID, &rapl_defaults_tng),
+ X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID2, &rapl_defaults_ann),
+ X86_MATCH_VFM(INTEL_ATOM_GOLDMONT, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_PLUS, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_D, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_ATOM_TREMONT, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_ATOM_TREMONT_D, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_ATOM_TREMONT_L, &rapl_defaults_core),
+
+ X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &rapl_defaults_hsw_server),
+ X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &rapl_defaults_hsw_server),
+
+ X86_MATCH_VENDOR_FAM(AMD, 0x17, &rapl_defaults_amd),
+ X86_MATCH_VENDOR_FAM(AMD, 0x19, &rapl_defaults_amd),
+ X86_MATCH_VENDOR_FAM(AMD, 0x1A, &rapl_defaults_amd),
+ X86_MATCH_VENDOR_FAM(HYGON, 0x18, &rapl_defaults_amd),
{}
};
MODULE_DEVICE_TABLE(x86cpu, rapl_ids);
@@ -1780,7 +1784,6 @@ enum perf_rapl_events {
PERF_RAPL_PSYS, /* psys */
PERF_RAPL_MAX
};
-#define RAPL_EVENT_MASK GENMASK(7, 0)
static const int event_to_domain[PERF_RAPL_MAX] = {
[PERF_RAPL_PP0] = RAPL_DOMAIN_PP0,
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v1 3/9] powercap: intel_rapl: Use GENMASK() and BIT() macros
2026-01-29 18:36 [PATCH v1 0/9] Move RAPL defaults to interface drivers Kuppuswamy Sathyanarayanan
2026-01-29 18:36 ` [PATCH v1 1/9] powercap: intel_rapl: Add a symbol namespace for intel_rapl exports Kuppuswamy Sathyanarayanan
2026-01-29 18:36 ` [PATCH v1 2/9] powercap: intel_rapl: Cleanup coding style Kuppuswamy Sathyanarayanan
@ 2026-01-29 18:36 ` Kuppuswamy Sathyanarayanan
2026-01-29 21:52 ` David Laight
2026-01-29 18:36 ` [PATCH v1 4/9] powercap: intel_rapl: Use unit conversion macros from units.h Kuppuswamy Sathyanarayanan
` (6 subsequent siblings)
9 siblings, 1 reply; 13+ messages in thread
From: Kuppuswamy Sathyanarayanan @ 2026-01-29 18:36 UTC (permalink / raw)
To: Rafael J . Wysocki, Daniel Lezcano
Cc: Zhang Rui, Lukasz Luba, Srinivas Pandruvada, linux-pm,
linux-kernel
Replace hardcoded bitmasks and bit shift operations with standard
GENMASK(), GENMASK_ULL(), BIT(), and BIT_ULL() macros for better
readability and to follow kernel coding conventions.
No functional changes.
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
---
drivers/powercap/intel_rapl_common.c | 78 ++++++++++++++--------------
1 file changed, 39 insertions(+), 39 deletions(-)
diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_rapl_common.c
index 74a74af8f0ec..0faafba8cc7c 100644
--- a/drivers/powercap/intel_rapl_common.c
+++ b/drivers/powercap/intel_rapl_common.c
@@ -31,62 +31,62 @@
#include <asm/msr.h>
/* bitmasks for RAPL MSRs, used by primitive access functions */
-#define ENERGY_STATUS_MASK 0xffffffff
+#define ENERGY_STATUS_MASK GENMASK(31, 0)
-#define POWER_LIMIT1_MASK 0x7FFF
+#define POWER_LIMIT1_MASK GENMASK(14, 0)
#define POWER_LIMIT1_ENABLE BIT(15)
#define POWER_LIMIT1_CLAMP BIT(16)
-#define POWER_LIMIT2_MASK (0x7FFFULL<<32)
+#define POWER_LIMIT2_MASK GENMASK_ULL(46, 32)
#define POWER_LIMIT2_ENABLE BIT_ULL(47)
#define POWER_LIMIT2_CLAMP BIT_ULL(48)
#define POWER_HIGH_LOCK BIT_ULL(63)
#define POWER_LOW_LOCK BIT(31)
-#define POWER_LIMIT4_MASK 0x1FFF
+#define POWER_LIMIT4_MASK GENMASK(12, 0)
-#define TIME_WINDOW1_MASK (0x7FULL<<17)
-#define TIME_WINDOW2_MASK (0x7FULL<<49)
+#define TIME_WINDOW1_MASK GENMASK_ULL(23, 17)
+#define TIME_WINDOW2_MASK GENMASK_ULL(55, 49)
#define POWER_UNIT_OFFSET 0x00
-#define POWER_UNIT_MASK 0x0F
+#define POWER_UNIT_MASK GENMASK(3, 0)
#define ENERGY_UNIT_OFFSET 0x08
-#define ENERGY_UNIT_MASK 0x1F00
+#define ENERGY_UNIT_MASK GENMASK(12, 8)
#define TIME_UNIT_OFFSET 0x10
-#define TIME_UNIT_MASK 0xF0000
+#define TIME_UNIT_MASK GENMASK(19, 16)
-#define POWER_INFO_MAX_MASK (0x7fffULL<<32)
-#define POWER_INFO_MIN_MASK (0x7fffULL<<16)
-#define POWER_INFO_MAX_TIME_WIN_MASK (0x3fULL<<48)
-#define POWER_INFO_THERMAL_SPEC_MASK 0x7fff
+#define POWER_INFO_MAX_MASK GENMASK_ULL(46, 32)
+#define POWER_INFO_MIN_MASK GENMASK_ULL(30, 16)
+#define POWER_INFO_MAX_TIME_WIN_MASK GENMASK_ULL(53, 48)
+#define POWER_INFO_THERMAL_SPEC_MASK GENMASK(14, 0)
-#define PERF_STATUS_THROTTLE_TIME_MASK 0xffffffff
-#define PP_POLICY_MASK 0x1F
+#define PERF_STATUS_THROTTLE_TIME_MASK GENMASK(31, 0)
+#define PP_POLICY_MASK GENMASK(4, 0)
/*
* SPR has different layout for Psys Domain PowerLimit registers.
* There are 17 bits of PL1 and PL2 instead of 15 bits.
* The Enable bits and TimeWindow bits are also shifted as a result.
*/
-#define PSYS_POWER_LIMIT1_MASK 0x1FFFF
+#define PSYS_POWER_LIMIT1_MASK GENMASK_ULL(16, 0)
#define PSYS_POWER_LIMIT1_ENABLE BIT(17)
-#define PSYS_POWER_LIMIT2_MASK (0x1FFFFULL<<32)
+#define PSYS_POWER_LIMIT2_MASK GENMASK_ULL(48, 32)
#define PSYS_POWER_LIMIT2_ENABLE BIT_ULL(49)
-#define PSYS_TIME_WINDOW1_MASK (0x7FULL<<19)
-#define PSYS_TIME_WINDOW2_MASK (0x7FULL<<51)
+#define PSYS_TIME_WINDOW1_MASK GENMASK_ULL(25, 19)
+#define PSYS_TIME_WINDOW2_MASK GENMASK_ULL(57, 51)
/* bitmasks for RAPL TPMI, used by primitive access functions */
-#define TPMI_POWER_LIMIT_MASK 0x3FFFF
+#define TPMI_POWER_LIMIT_MASK GENMASK_ULL(17, 0)
#define TPMI_POWER_LIMIT_ENABLE BIT_ULL(62)
-#define TPMI_TIME_WINDOW_MASK (0x7FULL<<18)
-#define TPMI_INFO_SPEC_MASK 0x3FFFF
-#define TPMI_INFO_MIN_MASK (0x3FFFFULL << 18)
-#define TPMI_INFO_MAX_MASK (0x3FFFFULL << 36)
-#define TPMI_INFO_MAX_TIME_WIN_MASK (0x7FULL << 54)
+#define TPMI_TIME_WINDOW_MASK GENMASK_ULL(24, 18)
+#define TPMI_INFO_SPEC_MASK GENMASK_ULL(17, 0)
+#define TPMI_INFO_MIN_MASK GENMASK_ULL(35, 18)
+#define TPMI_INFO_MAX_MASK GENMASK_ULL(53, 36)
+#define TPMI_INFO_MAX_TIME_WIN_MASK GENMASK_ULL(60, 54)
/* Non HW constants */
#define RAPL_PRIMITIVE_DERIVED BIT(1) /* not from raw data */
@@ -111,9 +111,9 @@
#define TPMI_POWER_UNIT_OFFSET POWER_UNIT_OFFSET
#define TPMI_POWER_UNIT_MASK POWER_UNIT_MASK
#define TPMI_ENERGY_UNIT_OFFSET 0x06
-#define TPMI_ENERGY_UNIT_MASK 0x7C0
+#define TPMI_ENERGY_UNIT_MASK GENMASK_ULL(10, 6)
#define TPMI_TIME_UNIT_OFFSET 0x0C
-#define TPMI_TIME_UNIT_MASK 0xF000
+#define TPMI_TIME_UNIT_MASK GENMASK_ULL(15, 12)
#define RAPL_EVENT_MASK GENMASK(7, 0)
@@ -964,13 +964,13 @@ static int rapl_check_unit_core(struct rapl_domain *rd)
}
value = (ra.value & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
- rd->energy_unit = ENERGY_UNIT_SCALE * 1000000 / (1 << value);
+ rd->energy_unit = ENERGY_UNIT_SCALE * 1000000 / BIT(value);
value = (ra.value & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET;
- rd->power_unit = 1000000 / (1 << value);
+ rd->power_unit = 1000000 / BIT(value);
value = (ra.value & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET;
- rd->time_unit = 1000000 / (1 << value);
+ rd->time_unit = 1000000 / BIT(value);
pr_debug("Core CPU %s:%s energy=%dpJ, time=%dus, power=%duW\n",
rd->rp->name, rd->name, rd->energy_unit, rd->time_unit, rd->power_unit);
@@ -992,13 +992,13 @@ static int rapl_check_unit_atom(struct rapl_domain *rd)
}
value = (ra.value & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
- rd->energy_unit = ENERGY_UNIT_SCALE * 1 << value;
+ rd->energy_unit = ENERGY_UNIT_SCALE * BIT(value);
value = (ra.value & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET;
- rd->power_unit = (1 << value) * 1000;
+ rd->power_unit = BIT(value) * 1000;
value = (ra.value & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET;
- rd->time_unit = 1000000 / (1 << value);
+ rd->time_unit = 1000000 / BIT(value);
pr_debug("Atom %s:%s energy=%dpJ, time=%dus, power=%duW\n",
rd->rp->name, rd->name, rd->energy_unit, rd->time_unit, rd->power_unit);
@@ -1102,8 +1102,8 @@ static void set_floor_freq_atom(struct rapl_domain *rd, bool enable)
&power_ctrl_orig_val);
mdata = power_ctrl_orig_val;
if (enable) {
- mdata &= ~(0x7f << 8);
- mdata |= 1 << 8;
+ mdata &= ~GENMASK(14, 8);
+ mdata |= BIT(8);
}
iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_CR_WRITE,
defaults->floor_freq_reg_addr, mdata);
@@ -1136,7 +1136,7 @@ static u64 rapl_compute_time_window_core(struct rapl_domain *rd, u64 value,
if (y > 0x1f)
return 0x7f;
- f = div64_u64(4 * (value - (1ULL << y)), 1ULL << y);
+ f = div64_u64(4 * (value - BIT_ULL(y)), BIT_ULL(y));
value = (y & 0x1f) | ((f & 0x3) << 5);
}
return value;
@@ -1169,13 +1169,13 @@ static int rapl_check_unit_tpmi(struct rapl_domain *rd)
}
value = (ra.value & TPMI_ENERGY_UNIT_MASK) >> TPMI_ENERGY_UNIT_OFFSET;
- rd->energy_unit = ENERGY_UNIT_SCALE * 1000000 / (1 << value);
+ rd->energy_unit = ENERGY_UNIT_SCALE * 1000000 / BIT(value);
value = (ra.value & TPMI_POWER_UNIT_MASK) >> TPMI_POWER_UNIT_OFFSET;
- rd->power_unit = 1000000 / (1 << value);
+ rd->power_unit = 1000000 / BIT(value);
value = (ra.value & TPMI_TIME_UNIT_MASK) >> TPMI_TIME_UNIT_OFFSET;
- rd->time_unit = 1000000 / (1 << value);
+ rd->time_unit = 1000000 / BIT(value);
pr_debug("Core CPU %s:%s energy=%dpJ, time=%dus, power=%duW\n",
rd->rp->name, rd->name, rd->energy_unit, rd->time_unit, rd->power_unit);
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v1 3/9] powercap: intel_rapl: Use GENMASK() and BIT() macros
2026-01-29 18:36 ` [PATCH v1 3/9] powercap: intel_rapl: Use GENMASK() and BIT() macros Kuppuswamy Sathyanarayanan
@ 2026-01-29 21:52 ` David Laight
2026-01-29 22:17 ` Kuppuswamy Sathyanarayanan
0 siblings, 1 reply; 13+ messages in thread
From: David Laight @ 2026-01-29 21:52 UTC (permalink / raw)
To: Kuppuswamy Sathyanarayanan
Cc: Rafael J . Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Srinivas Pandruvada, linux-pm, linux-kernel
On Thu, 29 Jan 2026 10:36:40 -0800
Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> wrote:
> Replace hardcoded bitmasks and bit shift operations with standard
> GENMASK(), GENMASK_ULL(), BIT(), and BIT_ULL() macros for better
> readability and to follow kernel coding conventions.
>
> No functional changes.
Assuming that changing values to 'unsigned long' doesn't have any
subtle side effects.
...
> value = (ra.value & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
> - rd->energy_unit = ENERGY_UNIT_SCALE * 1000000 / (1 << value);
> + rd->energy_unit = ENERGY_UNIT_SCALE * 1000000 / BIT(value);
That should really be:
rd->energy_unit = ENERGY_UNIT_SCALE * 1000000 >> value;
While using BIT() for bit patterns is resonable, wholesale substition
isn't really right - and that isn't a bit pattern.
David
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v1 3/9] powercap: intel_rapl: Use GENMASK() and BIT() macros
2026-01-29 21:52 ` David Laight
@ 2026-01-29 22:17 ` Kuppuswamy Sathyanarayanan
0 siblings, 0 replies; 13+ messages in thread
From: Kuppuswamy Sathyanarayanan @ 2026-01-29 22:17 UTC (permalink / raw)
To: David Laight
Cc: Rafael J . Wysocki, Daniel Lezcano, Zhang Rui, Lukasz Luba,
Srinivas Pandruvada, linux-pm, linux-kernel
On 1/29/2026 1:52 PM, David Laight wrote:
> On Thu, 29 Jan 2026 10:36:40 -0800
> Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> wrote:
>
>> Replace hardcoded bitmasks and bit shift operations with standard
>> GENMASK(), GENMASK_ULL(), BIT(), and BIT_ULL() macros for better
>> readability and to follow kernel coding conventions.
>>
>> No functional changes.
>
> Assuming that changing values to 'unsigned long' doesn't have any
> subtle side effects.
>
> ...
>> value = (ra.value & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
>> - rd->energy_unit = ENERGY_UNIT_SCALE * 1000000 / (1 << value);
>> + rd->energy_unit = ENERGY_UNIT_SCALE * 1000000 / BIT(value);
>
> That should really be:
> rd->energy_unit = ENERGY_UNIT_SCALE * 1000000 >> value;
Type change to unsigned long will not have any impact for this use case.
However, as you noted, using right shift (>>) instead of division by
BIT() is the correct approach here anyway.
>
> While using BIT() for bit patterns is resonable, wholesale substition
> isn't really right - and that isn't a bit pattern.
Agreed. I will use right shift for 1 / (1 << value) use cases.
>
> David
--
Sathyanarayanan Kuppuswamy
Linux Kernel Developer
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v1 4/9] powercap: intel_rapl: Use unit conversion macros from units.h
2026-01-29 18:36 [PATCH v1 0/9] Move RAPL defaults to interface drivers Kuppuswamy Sathyanarayanan
` (2 preceding siblings ...)
2026-01-29 18:36 ` [PATCH v1 3/9] powercap: intel_rapl: Use GENMASK() and BIT() macros Kuppuswamy Sathyanarayanan
@ 2026-01-29 18:36 ` Kuppuswamy Sathyanarayanan
2026-01-29 18:36 ` [PATCH v1 5/9] powercap: intel_rapl: Allow interface drivers to configure rapl_defaults Kuppuswamy Sathyanarayanan
` (5 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Kuppuswamy Sathyanarayanan @ 2026-01-29 18:36 UTC (permalink / raw)
To: Rafael J . Wysocki, Daniel Lezcano
Cc: Zhang Rui, Lukasz Luba, Srinivas Pandruvada, linux-pm,
linux-kernel
Replace hardcoded numeric constants with standard unit conversion
macros from linux/units.h for better code clarity and
self-documentation.
Add MICROJOULE_PER_JOULE and NANOJOULE_PER_JOULE to units.h to
support energy unit conversions, following the existing pattern
for power units.
No functional changes.
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
---
drivers/powercap/intel_rapl_common.c | 19 ++++++++++---------
include/linux/units.h | 3 +++
2 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_rapl_common.c
index 0faafba8cc7c..8f9d504fb64c 100644
--- a/drivers/powercap/intel_rapl_common.c
+++ b/drivers/powercap/intel_rapl_common.c
@@ -24,6 +24,7 @@
#include <linux/suspend.h>
#include <linux/sysfs.h>
#include <linux/types.h>
+#include <linux/units.h>
#include <asm/cpu_device_id.h>
#include <asm/intel-family.h>
@@ -964,13 +965,13 @@ static int rapl_check_unit_core(struct rapl_domain *rd)
}
value = (ra.value & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
- rd->energy_unit = ENERGY_UNIT_SCALE * 1000000 / BIT(value);
+ rd->energy_unit = ENERGY_UNIT_SCALE * MICROJOULE_PER_JOULE / BIT(value);
value = (ra.value & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET;
- rd->power_unit = 1000000 / BIT(value);
+ rd->power_unit = MICROWATT_PER_WATT / BIT(value);
value = (ra.value & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET;
- rd->time_unit = 1000000 / BIT(value);
+ rd->time_unit = USEC_PER_SEC / BIT(value);
pr_debug("Core CPU %s:%s energy=%dpJ, time=%dus, power=%duW\n",
rd->rp->name, rd->name, rd->energy_unit, rd->time_unit, rd->power_unit);
@@ -995,10 +996,10 @@ static int rapl_check_unit_atom(struct rapl_domain *rd)
rd->energy_unit = ENERGY_UNIT_SCALE * BIT(value);
value = (ra.value & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET;
- rd->power_unit = BIT(value) * 1000;
+ rd->power_unit = BIT(value) * MILLIWATT_PER_WATT;
value = (ra.value & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET;
- rd->time_unit = 1000000 / BIT(value);
+ rd->time_unit = USEC_PER_SEC / BIT(value);
pr_debug("Atom %s:%s energy=%dpJ, time=%dus, power=%duW\n",
rd->rp->name, rd->name, rd->energy_unit, rd->time_unit, rd->power_unit);
@@ -1169,13 +1170,13 @@ static int rapl_check_unit_tpmi(struct rapl_domain *rd)
}
value = (ra.value & TPMI_ENERGY_UNIT_MASK) >> TPMI_ENERGY_UNIT_OFFSET;
- rd->energy_unit = ENERGY_UNIT_SCALE * 1000000 / BIT(value);
+ rd->energy_unit = ENERGY_UNIT_SCALE * MICROJOULE_PER_JOULE / BIT(value);
value = (ra.value & TPMI_POWER_UNIT_MASK) >> TPMI_POWER_UNIT_OFFSET;
- rd->power_unit = 1000000 / BIT(value);
+ rd->power_unit = MICROWATT_PER_WATT / BIT(value);
value = (ra.value & TPMI_TIME_UNIT_MASK) >> TPMI_TIME_UNIT_OFFSET;
- rd->time_unit = 1000000 / BIT(value);
+ rd->time_unit = USEC_PER_SEC / BIT(value);
pr_debug("Core CPU %s:%s energy=%dpJ, time=%dus, power=%duW\n",
rd->rp->name, rd->name, rd->energy_unit, rd->time_unit, rd->power_unit);
@@ -1208,7 +1209,7 @@ static const struct rapl_defaults rapl_defaults_spr_server = {
.check_unit = rapl_check_unit_core,
.set_floor_freq = set_floor_freq_default,
.compute_time_window = rapl_compute_time_window_core,
- .psys_domain_energy_unit = 1000000000,
+ .psys_domain_energy_unit = NANOJOULE_PER_JOULE,
.spr_psys_bits = true,
};
diff --git a/include/linux/units.h b/include/linux/units.h
index 00e15de33eca..8c17d98cd67e 100644
--- a/include/linux/units.h
+++ b/include/linux/units.h
@@ -35,6 +35,9 @@
#define MICROWATT_PER_MILLIWATT 1000UL
#define MICROWATT_PER_WATT 1000000UL
+#define MICROJOULE_PER_JOULE 1000000UL
+#define NANOJOULE_PER_JOULE 1000000000UL
+
#define BYTES_PER_KBIT (KILO / BITS_PER_BYTE)
#define BYTES_PER_MBIT (MEGA / BITS_PER_BYTE)
#define BYTES_PER_GBIT (GIGA / BITS_PER_BYTE)
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v1 5/9] powercap: intel_rapl: Allow interface drivers to configure rapl_defaults
2026-01-29 18:36 [PATCH v1 0/9] Move RAPL defaults to interface drivers Kuppuswamy Sathyanarayanan
` (3 preceding siblings ...)
2026-01-29 18:36 ` [PATCH v1 4/9] powercap: intel_rapl: Use unit conversion macros from units.h Kuppuswamy Sathyanarayanan
@ 2026-01-29 18:36 ` Kuppuswamy Sathyanarayanan
2026-01-29 18:36 ` [PATCH v1 6/9] powercap: intel_rapl: Move TPMI default settings into TPMI interface driver Kuppuswamy Sathyanarayanan
` (4 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Kuppuswamy Sathyanarayanan @ 2026-01-29 18:36 UTC (permalink / raw)
To: Rafael J . Wysocki, Daniel Lezcano
Cc: Zhang Rui, Lukasz Luba, Srinivas Pandruvada, linux-pm,
linux-kernel
RAPL default settings vary across different RAPL interfaces (MSR, TPMI,
MMIO). Currently, these defaults are stored in the common RAPL driver,
which requires interface-specific handling logic and makes the common
layer unnecessarily complex. There is no strong reason for the common
code to own these defaults, since they are inherently
interface-specific.
To prepare for moving default configuration into the individual
interface drivers,
1. Move struct rapl_defaults into a shared header so that interface
drivers can directly populate their own default settings.
2. Change the @defaults field in struct rapl_if_priv from void * to
const struct rapl_defaults * to improve type safety and readability
and update the common driver to use the typed defaults structure.
3. Update all internal getter functions and local pointers to use
const struct rapl_defaults * to maintain const-correctness.
4. Rename and export the common helper functions (check_unit,
set_floor_freq, compute_time_window) so interface drivers may
reuse or override them as appropriate.
No functional changes. This is a preparatory refactoring to allow
interface drivers to supply their own RAPL default settings.
Co-developed-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
---
drivers/powercap/intel_rapl_common.c | 64 ++++++++++++----------------
include/linux/intel_rapl.h | 17 +++++++-
2 files changed, 43 insertions(+), 38 deletions(-)
diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_rapl_common.c
index 8f9d504fb64c..b60d8fd6cc82 100644
--- a/drivers/powercap/intel_rapl_common.c
+++ b/drivers/powercap/intel_rapl_common.c
@@ -221,20 +221,10 @@ static int get_pl_prim(struct rapl_domain *rd, int pl, enum pl_prims prim)
#define power_zone_to_rapl_domain(_zone) \
container_of(_zone, struct rapl_domain, power_zone)
-struct rapl_defaults {
- u8 floor_freq_reg_addr;
- int (*check_unit)(struct rapl_domain *rd);
- void (*set_floor_freq)(struct rapl_domain *rd, bool mode);
- u64 (*compute_time_window)(struct rapl_domain *rd, u64 val,
- bool to_raw);
- unsigned int dram_domain_energy_unit;
- unsigned int psys_domain_energy_unit;
- bool spr_psys_bits;
-};
-static struct rapl_defaults *defaults_msr;
+static const struct rapl_defaults *defaults_msr;
static const struct rapl_defaults defaults_tpmi;
-static struct rapl_defaults *get_defaults(struct rapl_package *rp)
+static const struct rapl_defaults *get_defaults(struct rapl_package *rp)
{
return rp->priv->defaults;
}
@@ -351,7 +341,7 @@ static int find_nr_power_limit(struct rapl_domain *rd)
static int set_domain_enable(struct powercap_zone *power_zone, bool mode)
{
struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
- struct rapl_defaults *defaults = get_defaults(rd->rp);
+ const struct rapl_defaults *defaults = get_defaults(rd->rp);
u64 val;
int ret;
@@ -640,7 +630,7 @@ static u64 rapl_unit_xlate(struct rapl_domain *rd, enum unit_type type,
u64 value, int to_raw)
{
u64 units = 1;
- struct rapl_defaults *defaults = get_defaults(rd->rp);
+ const struct rapl_defaults *defaults = get_defaults(rd->rp);
u64 scale = 1;
switch (type) {
@@ -785,11 +775,11 @@ static int rapl_config(struct rapl_package *rp)
/* MMIO I/F shares the same register layout as MSR registers */
case RAPL_IF_MMIO:
case RAPL_IF_MSR:
- rp->priv->defaults = (void *)defaults_msr;
+ rp->priv->defaults = defaults_msr;
rp->priv->rpi = (void *)rpi_msr;
break;
case RAPL_IF_TPMI:
- rp->priv->defaults = (void *)&defaults_tpmi;
+ rp->priv->defaults = &defaults_tpmi;
rp->priv->rpi = (void *)rpi_tpmi;
break;
default:
@@ -806,7 +796,7 @@ static int rapl_config(struct rapl_package *rp)
static enum rapl_primitives
prim_fixups(struct rapl_domain *rd, enum rapl_primitives prim)
{
- struct rapl_defaults *defaults = get_defaults(rd->rp);
+ const struct rapl_defaults *defaults = get_defaults(rd->rp);
if (!defaults->spr_psys_bits)
return prim;
@@ -951,7 +941,7 @@ static int rapl_write_pl_data(struct rapl_domain *rd, int pl,
* power unit : microWatts : Represented in milliWatts by default
* time unit : microseconds: Represented in seconds by default
*/
-static int rapl_check_unit_core(struct rapl_domain *rd)
+int rapl_default_check_unit(struct rapl_domain *rd)
{
struct reg_action ra;
u32 value;
@@ -978,6 +968,7 @@ static int rapl_check_unit_core(struct rapl_domain *rd)
return 0;
}
+EXPORT_SYMBOL_NS_GPL(rapl_default_check_unit, "INTEL_RAPL");
static int rapl_check_unit_atom(struct rapl_domain *rd)
{
@@ -1071,7 +1062,7 @@ static void package_power_limit_irq_restore(struct rapl_package *rp)
wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
}
-static void set_floor_freq_default(struct rapl_domain *rd, bool mode)
+void rapl_default_set_floor_freq(struct rapl_domain *rd, bool mode)
{
int i;
@@ -1085,11 +1076,12 @@ static void set_floor_freq_default(struct rapl_domain *rd, bool mode)
rapl_write_pl_data(rd, i, PL_CLAMP, mode);
}
}
+EXPORT_SYMBOL_NS_GPL(rapl_default_set_floor_freq, "INTEL_RAPL");
static void set_floor_freq_atom(struct rapl_domain *rd, bool enable)
{
static u32 power_ctrl_orig_val;
- struct rapl_defaults *defaults = get_defaults(rd->rp);
+ const struct rapl_defaults *defaults = get_defaults(rd->rp);
u32 mdata;
if (!defaults->floor_freq_reg_addr) {
@@ -1110,8 +1102,7 @@ static void set_floor_freq_atom(struct rapl_domain *rd, bool enable)
defaults->floor_freq_reg_addr, mdata);
}
-static u64 rapl_compute_time_window_core(struct rapl_domain *rd, u64 value,
- bool to_raw)
+u64 rapl_default_compute_time_window(struct rapl_domain *rd, u64 value, bool to_raw)
{
u64 f, y; /* fraction and exp. used for time unit */
@@ -1142,6 +1133,7 @@ static u64 rapl_compute_time_window_core(struct rapl_domain *rd, u64 value,
}
return value;
}
+EXPORT_SYMBOL_NS_GPL(rapl_default_compute_time_window, "INTEL_RAPL");
static u64 rapl_compute_time_window_atom(struct rapl_domain *rd, u64 value,
bool to_raw)
@@ -1187,28 +1179,28 @@ static int rapl_check_unit_tpmi(struct rapl_domain *rd)
static const struct rapl_defaults defaults_tpmi = {
.check_unit = rapl_check_unit_tpmi,
/* Reuse existing logic, ignore the PL_CLAMP failures and enable all Power Limits */
- .set_floor_freq = set_floor_freq_default,
- .compute_time_window = rapl_compute_time_window_core,
+ .set_floor_freq = rapl_default_set_floor_freq,
+ .compute_time_window = rapl_default_compute_time_window,
};
static const struct rapl_defaults rapl_defaults_core = {
.floor_freq_reg_addr = 0,
- .check_unit = rapl_check_unit_core,
- .set_floor_freq = set_floor_freq_default,
- .compute_time_window = rapl_compute_time_window_core,
+ .check_unit = rapl_default_check_unit,
+ .set_floor_freq = rapl_default_set_floor_freq,
+ .compute_time_window = rapl_default_compute_time_window,
};
static const struct rapl_defaults rapl_defaults_hsw_server = {
- .check_unit = rapl_check_unit_core,
- .set_floor_freq = set_floor_freq_default,
- .compute_time_window = rapl_compute_time_window_core,
+ .check_unit = rapl_default_check_unit,
+ .set_floor_freq = rapl_default_set_floor_freq,
+ .compute_time_window = rapl_default_compute_time_window,
.dram_domain_energy_unit = 15300,
};
static const struct rapl_defaults rapl_defaults_spr_server = {
- .check_unit = rapl_check_unit_core,
- .set_floor_freq = set_floor_freq_default,
- .compute_time_window = rapl_compute_time_window_core,
+ .check_unit = rapl_default_check_unit,
+ .set_floor_freq = rapl_default_set_floor_freq,
+ .compute_time_window = rapl_default_compute_time_window,
.psys_domain_energy_unit = NANOJOULE_PER_JOULE,
.spr_psys_bits = true,
};
@@ -1242,7 +1234,7 @@ static const struct rapl_defaults rapl_defaults_cht = {
};
static const struct rapl_defaults rapl_defaults_amd = {
- .check_unit = rapl_check_unit_core,
+ .check_unit = rapl_default_check_unit,
};
static const struct x86_cpu_id rapl_ids[] __initconst = {
@@ -1448,7 +1440,7 @@ static int rapl_check_domain(int domain, struct rapl_package *rp)
*/
static int rapl_get_domain_unit(struct rapl_domain *rd)
{
- struct rapl_defaults *defaults = get_defaults(rd->rp);
+ const struct rapl_defaults *defaults = get_defaults(rd->rp);
int ret;
if (!rd->regs[RAPL_DOMAIN_REG_UNIT].val) {
@@ -2347,7 +2339,7 @@ static int __init rapl_init(void)
id = x86_match_cpu(rapl_ids);
if (id) {
- defaults_msr = (struct rapl_defaults *)id->driver_data;
+ defaults_msr = (const struct rapl_defaults *)id->driver_data;
rapl_msr_platdev = platform_device_alloc("intel_rapl_msr", 0);
if (!rapl_msr_platdev)
diff --git a/include/linux/intel_rapl.h b/include/linux/intel_rapl.h
index f479ef5b3341..19f619fb37ff 100644
--- a/include/linux/intel_rapl.h
+++ b/include/linux/intel_rapl.h
@@ -128,6 +128,16 @@ struct reg_action {
int err;
};
+struct rapl_defaults {
+ u8 floor_freq_reg_addr;
+ int (*check_unit)(struct rapl_domain *rd);
+ void (*set_floor_freq)(struct rapl_domain *rd, bool mode);
+ u64 (*compute_time_window)(struct rapl_domain *rd, u64 val, bool to_raw);
+ unsigned int dram_domain_energy_unit;
+ unsigned int psys_domain_energy_unit;
+ bool spr_psys_bits;
+};
+
/**
* struct rapl_if_priv: private data for different RAPL interfaces
* @control_type: Each RAPL interface must have its own powercap
@@ -142,7 +152,7 @@ struct reg_action {
* registers.
* @write_raw: Callback for writing RAPL interface specific
* registers.
- * @defaults: internal pointer to interface default settings
+ * @defaults: pointer to default settings
* @rpi: internal pointer to interface primitive info
*/
struct rapl_if_priv {
@@ -154,7 +164,7 @@ struct rapl_if_priv {
int limits[RAPL_DOMAIN_MAX];
int (*read_raw)(int id, struct reg_action *ra, bool atomic);
int (*write_raw)(int id, struct reg_action *ra);
- void *defaults;
+ const struct rapl_defaults *defaults;
void *rpi;
};
@@ -211,6 +221,9 @@ void rapl_remove_package_cpuslocked(struct rapl_package *rp);
struct rapl_package *rapl_find_package_domain(int id, struct rapl_if_priv *priv, bool id_is_cpu);
struct rapl_package *rapl_add_package(int id, struct rapl_if_priv *priv, bool id_is_cpu);
void rapl_remove_package(struct rapl_package *rp);
+int rapl_default_check_unit(struct rapl_domain *rd);
+void rapl_default_set_floor_freq(struct rapl_domain *rd, bool mode);
+u64 rapl_default_compute_time_window(struct rapl_domain *rd, u64 value, bool to_raw);
#ifdef CONFIG_PERF_EVENTS
int rapl_package_add_pmu(struct rapl_package *rp);
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v1 6/9] powercap: intel_rapl: Move TPMI default settings into TPMI interface driver
2026-01-29 18:36 [PATCH v1 0/9] Move RAPL defaults to interface drivers Kuppuswamy Sathyanarayanan
` (4 preceding siblings ...)
2026-01-29 18:36 ` [PATCH v1 5/9] powercap: intel_rapl: Allow interface drivers to configure rapl_defaults Kuppuswamy Sathyanarayanan
@ 2026-01-29 18:36 ` Kuppuswamy Sathyanarayanan
2026-01-29 18:36 ` [PATCH v1 7/9] thermal: intel: int340x: processor: Move RAPL defaults to MMIO driver Kuppuswamy Sathyanarayanan
` (3 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Kuppuswamy Sathyanarayanan @ 2026-01-29 18:36 UTC (permalink / raw)
To: Rafael J . Wysocki, Daniel Lezcano
Cc: Zhang Rui, Lukasz Luba, Srinivas Pandruvada, linux-pm,
linux-kernel
TPMI-specific RAPL defaults differ from those used by MSR and MMIO
interfaces. Keeping them in RAPL common driver introduces unnecessary
complexity.
Move the TPMI defaults into the TPMI interface driver. This change
includes the following updates:
1. Add a TPMI-local struct rapl_defaults instance and assign it to
priv->defaults during TPMI probe.
2. Move rapl_check_unit_tpmi() and related unit-field definitions from
the common driver into the TPMI driver.
3. In rapl_check_unit_tpmi(), replace the generic get_rid() usage with
direct access to the TPMI package ID, since the function is now
interface-specific.
No functional changes are intended.
Co-developed-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
---
drivers/powercap/intel_rapl_common.c | 45 --------------------------
drivers/powercap/intel_rapl_tpmi.c | 47 ++++++++++++++++++++++++++++
2 files changed, 47 insertions(+), 45 deletions(-)
diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_rapl_common.c
index b60d8fd6cc82..54d88f1311ed 100644
--- a/drivers/powercap/intel_rapl_common.c
+++ b/drivers/powercap/intel_rapl_common.c
@@ -108,14 +108,6 @@
#define PACKAGE_PLN_INT_SAVED BIT(0)
#define MAX_PRIM_NAME 32
-/* TPMI Unit register has different layout */
-#define TPMI_POWER_UNIT_OFFSET POWER_UNIT_OFFSET
-#define TPMI_POWER_UNIT_MASK POWER_UNIT_MASK
-#define TPMI_ENERGY_UNIT_OFFSET 0x06
-#define TPMI_ENERGY_UNIT_MASK GENMASK_ULL(10, 6)
-#define TPMI_TIME_UNIT_OFFSET 0x0C
-#define TPMI_TIME_UNIT_MASK GENMASK_ULL(15, 12)
-
#define RAPL_EVENT_MASK GENMASK(7, 0)
enum unit_type {
@@ -222,7 +214,6 @@ static int get_pl_prim(struct rapl_domain *rd, int pl, enum pl_prims prim)
container_of(_zone, struct rapl_domain, power_zone)
static const struct rapl_defaults *defaults_msr;
-static const struct rapl_defaults defaults_tpmi;
static const struct rapl_defaults *get_defaults(struct rapl_package *rp)
{
@@ -779,7 +770,6 @@ static int rapl_config(struct rapl_package *rp)
rp->priv->rpi = (void *)rpi_msr;
break;
case RAPL_IF_TPMI:
- rp->priv->defaults = &defaults_tpmi;
rp->priv->rpi = (void *)rpi_tpmi;
break;
default:
@@ -1148,41 +1138,6 @@ static u64 rapl_compute_time_window_atom(struct rapl_domain *rd, u64 value,
return (value) ? value * rd->time_unit : rd->time_unit;
}
-static int rapl_check_unit_tpmi(struct rapl_domain *rd)
-{
- struct reg_action ra;
- u32 value;
-
- ra.reg = rd->regs[RAPL_DOMAIN_REG_UNIT];
- ra.mask = ~0;
- if (rd->rp->priv->read_raw(get_rid(rd->rp), &ra, false)) {
- pr_err("Failed to read power unit REG 0x%llx on %s:%s, exit.\n",
- ra.reg.val, rd->rp->name, rd->name);
- return -ENODEV;
- }
-
- value = (ra.value & TPMI_ENERGY_UNIT_MASK) >> TPMI_ENERGY_UNIT_OFFSET;
- rd->energy_unit = ENERGY_UNIT_SCALE * MICROJOULE_PER_JOULE / BIT(value);
-
- value = (ra.value & TPMI_POWER_UNIT_MASK) >> TPMI_POWER_UNIT_OFFSET;
- rd->power_unit = MICROWATT_PER_WATT / BIT(value);
-
- value = (ra.value & TPMI_TIME_UNIT_MASK) >> TPMI_TIME_UNIT_OFFSET;
- rd->time_unit = USEC_PER_SEC / BIT(value);
-
- pr_debug("Core CPU %s:%s energy=%dpJ, time=%dus, power=%duW\n",
- rd->rp->name, rd->name, rd->energy_unit, rd->time_unit, rd->power_unit);
-
- return 0;
-}
-
-static const struct rapl_defaults defaults_tpmi = {
- .check_unit = rapl_check_unit_tpmi,
- /* Reuse existing logic, ignore the PL_CLAMP failures and enable all Power Limits */
- .set_floor_freq = rapl_default_set_floor_freq,
- .compute_time_window = rapl_default_compute_time_window,
-};
-
static const struct rapl_defaults rapl_defaults_core = {
.floor_freq_reg_addr = 0,
.check_unit = rapl_default_check_unit,
diff --git a/drivers/powercap/intel_rapl_tpmi.c b/drivers/powercap/intel_rapl_tpmi.c
index 3b52403c14f8..2d69cf594dc2 100644
--- a/drivers/powercap/intel_rapl_tpmi.c
+++ b/drivers/powercap/intel_rapl_tpmi.c
@@ -9,12 +9,14 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/auxiliary_bus.h>
+#include <linux/bits.h>
#include <linux/intel_rapl.h>
#include <linux/intel_tpmi.h>
#include <linux/intel_vsec.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/slab.h>
+#include <linux/units.h>
#define TPMI_RAPL_MAJOR_VERSION 0
#define TPMI_RAPL_MINOR_VERSION 1
@@ -250,6 +252,50 @@ static int parse_one_domain(struct tpmi_rapl_package *trp, u32 offset)
return 0;
}
+/* TPMI Unit register has different layout */
+#define TPMI_ENERGY_UNIT_SCALE 1000
+#define TPMI_POWER_UNIT_OFFSET 0x00
+#define TPMI_POWER_UNIT_MASK GENMASK(3, 0)
+#define TPMI_ENERGY_UNIT_OFFSET 0x06
+#define TPMI_ENERGY_UNIT_MASK GENMASK_ULL(10, 6)
+#define TPMI_TIME_UNIT_OFFSET 0x0C
+#define TPMI_TIME_UNIT_MASK GENMASK_ULL(15, 12)
+
+static int rapl_check_unit_tpmi(struct rapl_domain *rd)
+{
+ struct reg_action ra;
+ u32 value;
+
+ ra.reg = rd->regs[RAPL_DOMAIN_REG_UNIT];
+ ra.mask = ~0;
+ if (tpmi_rapl_read_raw(rd->rp->id, &ra, false)) {
+ pr_err("Failed to read power unit REG 0x%llx on %s:%s, exit.\n",
+ ra.reg.val, rd->rp->name, rd->name);
+ return -ENODEV;
+ }
+
+ value = (ra.value & TPMI_ENERGY_UNIT_MASK) >> TPMI_ENERGY_UNIT_OFFSET;
+ rd->energy_unit = TPMI_ENERGY_UNIT_SCALE * MICROJOULE_PER_JOULE / BIT(value);
+
+ value = (ra.value & TPMI_POWER_UNIT_MASK) >> TPMI_POWER_UNIT_OFFSET;
+ rd->power_unit = MICROWATT_PER_WATT / BIT(value);
+
+ value = (ra.value & TPMI_TIME_UNIT_MASK) >> TPMI_TIME_UNIT_OFFSET;
+ rd->time_unit = USEC_PER_SEC / BIT(value);
+
+ pr_debug("Core CPU %s:%s energy=%dpJ, time=%dus, power=%duW\n",
+ rd->rp->name, rd->name, rd->energy_unit, rd->time_unit, rd->power_unit);
+
+ return 0;
+}
+
+static const struct rapl_defaults defaults_tpmi = {
+ .check_unit = rapl_check_unit_tpmi,
+ /* Reuse existing logic, ignore the PL_CLAMP failures and enable all Power Limits */
+ .set_floor_freq = rapl_default_set_floor_freq,
+ .compute_time_window = rapl_default_compute_time_window,
+};
+
static int intel_rapl_tpmi_probe(struct auxiliary_device *auxdev,
const struct auxiliary_device_id *id)
{
@@ -297,6 +343,7 @@ static int intel_rapl_tpmi_probe(struct auxiliary_device *auxdev,
trp->priv.read_raw = tpmi_rapl_read_raw;
trp->priv.write_raw = tpmi_rapl_write_raw;
trp->priv.control_type = tpmi_control_type;
+ trp->priv.defaults = &defaults_tpmi;
/* RAPL TPMI I/F is per physical package */
trp->rp = rapl_find_package_domain(info->package_id, &trp->priv, false);
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v1 7/9] thermal: intel: int340x: processor: Move RAPL defaults to MMIO driver
2026-01-29 18:36 [PATCH v1 0/9] Move RAPL defaults to interface drivers Kuppuswamy Sathyanarayanan
` (5 preceding siblings ...)
2026-01-29 18:36 ` [PATCH v1 6/9] powercap: intel_rapl: Move TPMI default settings into TPMI interface driver Kuppuswamy Sathyanarayanan
@ 2026-01-29 18:36 ` Kuppuswamy Sathyanarayanan
2026-01-29 18:36 ` [PATCH v1 8/9] powercap: intel_rapl: Register PM notifier only when RAPL package exists Kuppuswamy Sathyanarayanan
` (2 subsequent siblings)
9 siblings, 0 replies; 13+ messages in thread
From: Kuppuswamy Sathyanarayanan @ 2026-01-29 18:36 UTC (permalink / raw)
To: Rafael J . Wysocki, Daniel Lezcano
Cc: Zhang Rui, Lukasz Luba, Srinivas Pandruvada, linux-pm,
linux-kernel
Previously, the MMIO and MSR RAPL interfaces shared the same set of
RAPL defaults provided by common code. However, unlike the MSR
interface, the MMIO RAPL interface does not require CPU-specific
variations in its default handling. Keeping the RAPL defaults in
the RAPL common driver therefore provides no additional benefit.
Move the MMIO defaults into the MMIO interface driver. This change
includes the following updates:
* Introduce a MMIO-local rapl_defaults instance with the appropriate
default callbacks.
* Assign the MMIO-specific rapl_defaults to priv->defaults during
MMIO driver initialization.
No functional changes are expected.
Co-developed-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
---
.../intel/int340x_thermal/processor_thermal_rapl.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/thermal/intel/int340x_thermal/processor_thermal_rapl.c b/drivers/thermal/intel/int340x_thermal/processor_thermal_rapl.c
index e56b18aeda71..5dbeb0a43c8c 100644
--- a/drivers/thermal/intel/int340x_thermal/processor_thermal_rapl.c
+++ b/drivers/thermal/intel/int340x_thermal/processor_thermal_rapl.c
@@ -19,6 +19,13 @@ static const struct rapl_mmio_regs rapl_mmio_default = {
.limits[RAPL_DOMAIN_DRAM] = BIT(POWER_LIMIT2),
};
+static const struct rapl_defaults rapl_defaults_mmio = {
+ .floor_freq_reg_addr = 0,
+ .check_unit = rapl_default_check_unit,
+ .set_floor_freq = rapl_default_set_floor_freq,
+ .compute_time_window = rapl_default_compute_time_window,
+};
+
static int rapl_mmio_read_raw(int cpu, struct reg_action *ra, bool atomic)
{
if (!ra->reg.mmio)
@@ -67,6 +74,7 @@ int proc_thermal_rapl_add(struct pci_dev *pdev, struct proc_thermal_device *proc
rapl_mmio_priv.read_raw = rapl_mmio_read_raw;
rapl_mmio_priv.write_raw = rapl_mmio_write_raw;
+ rapl_mmio_priv.defaults = &rapl_defaults_mmio;
rapl_mmio_priv.control_type = powercap_register_control_type(NULL, "intel-rapl-mmio", NULL);
if (IS_ERR(rapl_mmio_priv.control_type)) {
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v1 8/9] powercap: intel_rapl: Register PM notifier only when RAPL package exists
2026-01-29 18:36 [PATCH v1 0/9] Move RAPL defaults to interface drivers Kuppuswamy Sathyanarayanan
` (6 preceding siblings ...)
2026-01-29 18:36 ` [PATCH v1 7/9] thermal: intel: int340x: processor: Move RAPL defaults to MMIO driver Kuppuswamy Sathyanarayanan
@ 2026-01-29 18:36 ` Kuppuswamy Sathyanarayanan
2026-01-29 18:36 ` [PATCH v1 9/9] powercap: intel_rapl: Move MSR default settings into MSR interface driver Kuppuswamy Sathyanarayanan
2026-01-29 19:20 ` [PATCH v1 0/9] Move RAPL defaults to interface drivers srinivas pandruvada
9 siblings, 0 replies; 13+ messages in thread
From: Kuppuswamy Sathyanarayanan @ 2026-01-29 18:36 UTC (permalink / raw)
To: Rafael J . Wysocki, Daniel Lezcano
Cc: Zhang Rui, Lukasz Luba, Srinivas Pandruvada, linux-pm,
linux-kernel
The PM notifier callbacks are needed only when a valid RAPL package
device is registered. Register and unregister the PM notifier callbacks
when a RAPL package device is added or removed.
This is a preparatory patch before moving MSR rapl_defaults into the
MSR RAPL interface driver.
Co-developed-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
---
drivers/powercap/intel_rapl_common.c | 130 +++++++++++++--------------
1 file changed, 64 insertions(+), 66 deletions(-)
diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_rapl_common.c
index 54d88f1311ed..648bef1d5de1 100644
--- a/drivers/powercap/intel_rapl_common.c
+++ b/drivers/powercap/intel_rapl_common.c
@@ -2077,6 +2077,64 @@ void rapl_package_remove_pmu(struct rapl_package *rp)
EXPORT_SYMBOL_NS_GPL(rapl_package_remove_pmu, "INTEL_RAPL");
#endif
+/* pm notifier for saving/restoring Power Limit settings */
+static void power_limit_state_save(void)
+{
+ struct rapl_package *rp;
+ struct rapl_domain *rd;
+ int ret;
+
+ cpus_read_lock();
+ list_for_each_entry(rp, &rapl_packages, plist) {
+ if (!rp->power_zone)
+ continue;
+ rd = power_zone_to_rapl_domain(rp->power_zone);
+ for (int i = POWER_LIMIT1; i < NR_POWER_LIMITS; i++) {
+ ret = rapl_read_pl_data(rd, i, PL_LIMIT, true,
+ &rd->rpl[i].last_power_limit);
+ if (ret)
+ rd->rpl[i].last_power_limit = 0;
+ }
+ }
+ cpus_read_unlock();
+}
+
+static void power_limit_state_restore(void)
+{
+ struct rapl_package *rp;
+ struct rapl_domain *rd;
+
+ cpus_read_lock();
+ list_for_each_entry(rp, &rapl_packages, plist) {
+ if (!rp->power_zone)
+ continue;
+ rd = power_zone_to_rapl_domain(rp->power_zone);
+ for (int i = POWER_LIMIT1; i < NR_POWER_LIMITS; i++)
+ if (rd->rpl[i].last_power_limit)
+ rapl_write_pl_data(rd, i, PL_LIMIT,
+ rd->rpl[i].last_power_limit);
+ }
+ cpus_read_unlock();
+}
+
+static int rapl_pm_callback(struct notifier_block *nb,
+ unsigned long mode, void *_unused)
+{
+ switch (mode) {
+ case PM_SUSPEND_PREPARE:
+ power_limit_state_save();
+ break;
+ case PM_POST_SUSPEND:
+ power_limit_state_restore();
+ break;
+ }
+ return NOTIFY_OK;
+}
+
+static struct notifier_block rapl_pm_notifier = {
+ .notifier_call = rapl_pm_callback,
+};
+
/* called from CPU hotplug notifier, hotplug lock held */
void rapl_remove_package_cpuslocked(struct rapl_package *rp)
{
@@ -2106,6 +2164,9 @@ void rapl_remove_package_cpuslocked(struct rapl_package *rp)
&rd_package->power_zone);
list_del(&rp->plist);
kfree(rp);
+
+ if (list_empty(&rapl_packages))
+ unregister_pm_notifier(&rapl_pm_notifier);
}
EXPORT_SYMBOL_NS_GPL(rapl_remove_package_cpuslocked, "INTEL_RAPL");
@@ -2208,6 +2269,8 @@ struct rapl_package *rapl_add_package_cpuslocked(int id, struct rapl_if_priv *pr
}
ret = rapl_package_register_powercap(rp);
if (!ret) {
+ if (list_empty(&rapl_packages))
+ register_pm_notifier(&rapl_pm_notifier);
INIT_LIST_HEAD(&rp->plist);
list_add(&rp->plist, &rapl_packages);
return rp;
@@ -2227,64 +2290,6 @@ struct rapl_package *rapl_add_package(int id, struct rapl_if_priv *priv, bool id
}
EXPORT_SYMBOL_NS_GPL(rapl_add_package, "INTEL_RAPL");
-static void power_limit_state_save(void)
-{
- struct rapl_package *rp;
- struct rapl_domain *rd;
- int ret, i;
-
- cpus_read_lock();
- list_for_each_entry(rp, &rapl_packages, plist) {
- if (!rp->power_zone)
- continue;
- rd = power_zone_to_rapl_domain(rp->power_zone);
- for (i = POWER_LIMIT1; i < NR_POWER_LIMITS; i++) {
- ret = rapl_read_pl_data(rd, i, PL_LIMIT, true,
- &rd->rpl[i].last_power_limit);
- if (ret)
- rd->rpl[i].last_power_limit = 0;
- }
- }
- cpus_read_unlock();
-}
-
-static void power_limit_state_restore(void)
-{
- struct rapl_package *rp;
- struct rapl_domain *rd;
- int i;
-
- cpus_read_lock();
- list_for_each_entry(rp, &rapl_packages, plist) {
- if (!rp->power_zone)
- continue;
- rd = power_zone_to_rapl_domain(rp->power_zone);
- for (i = POWER_LIMIT1; i < NR_POWER_LIMITS; i++)
- if (rd->rpl[i].last_power_limit)
- rapl_write_pl_data(rd, i, PL_LIMIT,
- rd->rpl[i].last_power_limit);
- }
- cpus_read_unlock();
-}
-
-static int rapl_pm_callback(struct notifier_block *nb,
- unsigned long mode, void *_unused)
-{
- switch (mode) {
- case PM_SUSPEND_PREPARE:
- power_limit_state_save();
- break;
- case PM_POST_SUSPEND:
- power_limit_state_restore();
- break;
- }
- return NOTIFY_OK;
-}
-
-static struct notifier_block rapl_pm_notifier = {
- .notifier_call = rapl_pm_callback,
-};
-
static struct platform_device *rapl_msr_platdev;
static int __init rapl_init(void)
@@ -2307,19 +2312,12 @@ static int __init rapl_init(void)
}
}
- ret = register_pm_notifier(&rapl_pm_notifier);
- if (ret && rapl_msr_platdev) {
- platform_device_del(rapl_msr_platdev);
- platform_device_put(rapl_msr_platdev);
- }
-
- return ret;
+ return 0;
}
static void __exit rapl_exit(void)
{
platform_device_unregister(rapl_msr_platdev);
- unregister_pm_notifier(&rapl_pm_notifier);
}
fs_initcall(rapl_init);
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v1 9/9] powercap: intel_rapl: Move MSR default settings into MSR interface driver
2026-01-29 18:36 [PATCH v1 0/9] Move RAPL defaults to interface drivers Kuppuswamy Sathyanarayanan
` (7 preceding siblings ...)
2026-01-29 18:36 ` [PATCH v1 8/9] powercap: intel_rapl: Register PM notifier only when RAPL package exists Kuppuswamy Sathyanarayanan
@ 2026-01-29 18:36 ` Kuppuswamy Sathyanarayanan
2026-01-29 19:20 ` [PATCH v1 0/9] Move RAPL defaults to interface drivers srinivas pandruvada
9 siblings, 0 replies; 13+ messages in thread
From: Kuppuswamy Sathyanarayanan @ 2026-01-29 18:36 UTC (permalink / raw)
To: Rafael J . Wysocki, Daniel Lezcano
Cc: Zhang Rui, Lukasz Luba, Srinivas Pandruvada, linux-pm,
linux-kernel
MSR-specific RAPL defaults differ from those used by the TPMI interface.
The MMIO and MSR interfaces shared the same rapl_defaults pointer in the
common driver, but MMIO does not require the CPU-specific variations
needed by MSR. Keeping these in the common driver adds unnecessary
complexity and MSR-specific initialization.
Move MSR defaults and CPU matching into the MSR interface driver.
Moves
-----
* Move rapl_check_unit_atom(), set_floor_freq_atom(), and
rapl_compute_time_window_atom() into intel_rapl_msr.c.
* Move MSR unit-field GENMASK definitions and local constants.
* Move all MSR-related rapl_defaults tables and the CPU-ID matching
logic (rapl_ids[]) into the MSR driver.
* Move iosf_mbi dependencies (floor-frequency control and related MBI
register definitions) as they are MSR-platform specific.
Modifications
-------------
* Replace the common driver's platform-device manual alloc/add sequence
with platform_device_register_data() in the MSR driver to pass
matching rapl_defaults as platform_data.
* Update MSR driver probe to assign pdev->dev.platform_data to
priv->defaults.
* Update Atom helper functions to use rp->lead_cpu directly for MSR
reads/writes instead of the generic get_rid().
* Update Atom floor frequency logic to access defaults via the
package private data pointer.
* Convert MSR device creation from fs_initcall() to module_init().
This preserves existing enumeration behavior as the driver was
already using module_init().
* Since rapl_ids need to exist after boot, remove __initconst
specifier.
No functional changes are expected.
Co-developed-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
---
drivers/powercap/intel_rapl_common.c | 232 -------------------------
drivers/powercap/intel_rapl_msr.c | 250 ++++++++++++++++++++++++++-
2 files changed, 249 insertions(+), 233 deletions(-)
diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_rapl_common.c
index 648bef1d5de1..75637ad69152 100644
--- a/drivers/powercap/intel_rapl_common.c
+++ b/drivers/powercap/intel_rapl_common.c
@@ -28,7 +28,6 @@
#include <asm/cpu_device_id.h>
#include <asm/intel-family.h>
-#include <asm/iosf_mbi.h>
#include <asm/msr.h>
/* bitmasks for RAPL MSRs, used by primitive access functions */
@@ -213,8 +212,6 @@ static int get_pl_prim(struct rapl_domain *rd, int pl, enum pl_prims prim)
#define power_zone_to_rapl_domain(_zone) \
container_of(_zone, struct rapl_domain, power_zone)
-static const struct rapl_defaults *defaults_msr;
-
static const struct rapl_defaults *get_defaults(struct rapl_package *rp)
{
return rp->priv->defaults;
@@ -766,7 +763,6 @@ static int rapl_config(struct rapl_package *rp)
/* MMIO I/F shares the same register layout as MSR registers */
case RAPL_IF_MMIO:
case RAPL_IF_MSR:
- rp->priv->defaults = defaults_msr;
rp->priv->rpi = (void *)rpi_msr;
break;
case RAPL_IF_TPMI:
@@ -960,34 +956,6 @@ int rapl_default_check_unit(struct rapl_domain *rd)
}
EXPORT_SYMBOL_NS_GPL(rapl_default_check_unit, "INTEL_RAPL");
-static int rapl_check_unit_atom(struct rapl_domain *rd)
-{
- struct reg_action ra;
- u32 value;
-
- ra.reg = rd->regs[RAPL_DOMAIN_REG_UNIT];
- ra.mask = ~0;
- if (rd->rp->priv->read_raw(get_rid(rd->rp), &ra, false)) {
- pr_err("Failed to read power unit REG 0x%llx on %s:%s, exit.\n",
- ra.reg.val, rd->rp->name, rd->name);
- return -ENODEV;
- }
-
- value = (ra.value & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
- rd->energy_unit = ENERGY_UNIT_SCALE * BIT(value);
-
- value = (ra.value & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET;
- rd->power_unit = BIT(value) * MILLIWATT_PER_WATT;
-
- value = (ra.value & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET;
- rd->time_unit = USEC_PER_SEC / BIT(value);
-
- pr_debug("Atom %s:%s energy=%dpJ, time=%dus, power=%duW\n",
- rd->rp->name, rd->name, rd->energy_unit, rd->time_unit, rd->power_unit);
-
- return 0;
-}
-
static void power_limit_irq_save_cpu(void *info)
{
u32 l, h = 0;
@@ -1068,30 +1036,6 @@ void rapl_default_set_floor_freq(struct rapl_domain *rd, bool mode)
}
EXPORT_SYMBOL_NS_GPL(rapl_default_set_floor_freq, "INTEL_RAPL");
-static void set_floor_freq_atom(struct rapl_domain *rd, bool enable)
-{
- static u32 power_ctrl_orig_val;
- const struct rapl_defaults *defaults = get_defaults(rd->rp);
- u32 mdata;
-
- if (!defaults->floor_freq_reg_addr) {
- pr_err("Invalid floor frequency config register\n");
- return;
- }
-
- if (!power_ctrl_orig_val)
- iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_CR_READ,
- defaults->floor_freq_reg_addr,
- &power_ctrl_orig_val);
- mdata = power_ctrl_orig_val;
- if (enable) {
- mdata &= ~GENMASK(14, 8);
- mdata |= BIT(8);
- }
- iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_CR_WRITE,
- defaults->floor_freq_reg_addr, mdata);
-}
-
u64 rapl_default_compute_time_window(struct rapl_domain *rd, u64 value, bool to_raw)
{
u64 f, y; /* fraction and exp. used for time unit */
@@ -1125,149 +1069,6 @@ u64 rapl_default_compute_time_window(struct rapl_domain *rd, u64 value, bool to_
}
EXPORT_SYMBOL_NS_GPL(rapl_default_compute_time_window, "INTEL_RAPL");
-static u64 rapl_compute_time_window_atom(struct rapl_domain *rd, u64 value,
- bool to_raw)
-{
- if (to_raw)
- return div64_u64(value, rd->time_unit);
-
- /*
- * Atom time unit encoding is straight forward val * time_unit,
- * where time_unit is default to 1 sec. Never 0.
- */
- return (value) ? value * rd->time_unit : rd->time_unit;
-}
-
-static const struct rapl_defaults rapl_defaults_core = {
- .floor_freq_reg_addr = 0,
- .check_unit = rapl_default_check_unit,
- .set_floor_freq = rapl_default_set_floor_freq,
- .compute_time_window = rapl_default_compute_time_window,
-};
-
-static const struct rapl_defaults rapl_defaults_hsw_server = {
- .check_unit = rapl_default_check_unit,
- .set_floor_freq = rapl_default_set_floor_freq,
- .compute_time_window = rapl_default_compute_time_window,
- .dram_domain_energy_unit = 15300,
-};
-
-static const struct rapl_defaults rapl_defaults_spr_server = {
- .check_unit = rapl_default_check_unit,
- .set_floor_freq = rapl_default_set_floor_freq,
- .compute_time_window = rapl_default_compute_time_window,
- .psys_domain_energy_unit = NANOJOULE_PER_JOULE,
- .spr_psys_bits = true,
-};
-
-static const struct rapl_defaults rapl_defaults_byt = {
- .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_BYT,
- .check_unit = rapl_check_unit_atom,
- .set_floor_freq = set_floor_freq_atom,
- .compute_time_window = rapl_compute_time_window_atom,
-};
-
-static const struct rapl_defaults rapl_defaults_tng = {
- .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_TNG,
- .check_unit = rapl_check_unit_atom,
- .set_floor_freq = set_floor_freq_atom,
- .compute_time_window = rapl_compute_time_window_atom,
-};
-
-static const struct rapl_defaults rapl_defaults_ann = {
- .floor_freq_reg_addr = 0,
- .check_unit = rapl_check_unit_atom,
- .set_floor_freq = NULL,
- .compute_time_window = rapl_compute_time_window_atom,
-};
-
-static const struct rapl_defaults rapl_defaults_cht = {
- .floor_freq_reg_addr = 0,
- .check_unit = rapl_check_unit_atom,
- .set_floor_freq = NULL,
- .compute_time_window = rapl_compute_time_window_atom,
-};
-
-static const struct rapl_defaults rapl_defaults_amd = {
- .check_unit = rapl_default_check_unit,
-};
-
-static const struct x86_cpu_id rapl_ids[] __initconst = {
- X86_MATCH_VFM(INTEL_SANDYBRIDGE, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_SANDYBRIDGE_X, &rapl_defaults_core),
-
- X86_MATCH_VFM(INTEL_IVYBRIDGE, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &rapl_defaults_core),
-
- X86_MATCH_VFM(INTEL_HASWELL, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_HASWELL_L, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_HASWELL_G, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_HASWELL_X, &rapl_defaults_hsw_server),
-
- X86_MATCH_VFM(INTEL_BROADWELL, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_BROADWELL_G, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_BROADWELL_D, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_BROADWELL_X, &rapl_defaults_hsw_server),
-
- X86_MATCH_VFM(INTEL_SKYLAKE, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_SKYLAKE_L, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_SKYLAKE_X, &rapl_defaults_hsw_server),
- X86_MATCH_VFM(INTEL_KABYLAKE_L, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_KABYLAKE, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_CANNONLAKE_L, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_ICELAKE_L, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_ICELAKE, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_ICELAKE_NNPI, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_ICELAKE_X, &rapl_defaults_hsw_server),
- X86_MATCH_VFM(INTEL_ICELAKE_D, &rapl_defaults_hsw_server),
- X86_MATCH_VFM(INTEL_COMETLAKE_L, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_COMETLAKE, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_TIGERLAKE_L, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_TIGERLAKE, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_ROCKETLAKE, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_ALDERLAKE, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_ALDERLAKE_L, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_RAPTORLAKE, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_RAPTORLAKE_P, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_RAPTORLAKE_S, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_BARTLETTLAKE, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_METEORLAKE, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_METEORLAKE_L, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &rapl_defaults_spr_server),
- X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &rapl_defaults_spr_server),
- X86_MATCH_VFM(INTEL_LUNARLAKE_M, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_WILDCATLAKE_L, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_NOVALAKE, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_NOVALAKE_L, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_ARROWLAKE_H, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_ARROWLAKE, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_ARROWLAKE_U, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_LAKEFIELD, &rapl_defaults_core),
-
- X86_MATCH_VFM(INTEL_ATOM_SILVERMONT, &rapl_defaults_byt),
- X86_MATCH_VFM(INTEL_ATOM_AIRMONT, &rapl_defaults_cht),
- X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID, &rapl_defaults_tng),
- X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID2, &rapl_defaults_ann),
- X86_MATCH_VFM(INTEL_ATOM_GOLDMONT, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_PLUS, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_D, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_ATOM_TREMONT, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_ATOM_TREMONT_D, &rapl_defaults_core),
- X86_MATCH_VFM(INTEL_ATOM_TREMONT_L, &rapl_defaults_core),
-
- X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &rapl_defaults_hsw_server),
- X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &rapl_defaults_hsw_server),
-
- X86_MATCH_VENDOR_FAM(AMD, 0x17, &rapl_defaults_amd),
- X86_MATCH_VENDOR_FAM(AMD, 0x19, &rapl_defaults_amd),
- X86_MATCH_VENDOR_FAM(AMD, 0x1A, &rapl_defaults_amd),
- X86_MATCH_VENDOR_FAM(HYGON, 0x18, &rapl_defaults_amd),
- {}
-};
-MODULE_DEVICE_TABLE(x86cpu, rapl_ids);
-
/* Read once for all raw primitive data for domains */
static void rapl_update_domain_data(struct rapl_package *rp)
{
@@ -2290,39 +2091,6 @@ struct rapl_package *rapl_add_package(int id, struct rapl_if_priv *priv, bool id
}
EXPORT_SYMBOL_NS_GPL(rapl_add_package, "INTEL_RAPL");
-static struct platform_device *rapl_msr_platdev;
-
-static int __init rapl_init(void)
-{
- const struct x86_cpu_id *id;
- int ret;
-
- id = x86_match_cpu(rapl_ids);
- if (id) {
- defaults_msr = (const struct rapl_defaults *)id->driver_data;
-
- rapl_msr_platdev = platform_device_alloc("intel_rapl_msr", 0);
- if (!rapl_msr_platdev)
- return -ENOMEM;
-
- ret = platform_device_add(rapl_msr_platdev);
- if (ret) {
- platform_device_put(rapl_msr_platdev);
- return ret;
- }
- }
-
- return 0;
-}
-
-static void __exit rapl_exit(void)
-{
- platform_device_unregister(rapl_msr_platdev);
-}
-
-fs_initcall(rapl_init);
-module_exit(rapl_exit);
-
MODULE_DESCRIPTION("Intel Runtime Average Power Limit (RAPL) common code");
MODULE_AUTHOR("Jacob Pan <jacob.jun.pan@intel.com>");
MODULE_LICENSE("GPL v2");
diff --git a/drivers/powercap/intel_rapl_msr.c b/drivers/powercap/intel_rapl_msr.c
index 6f23e601832d..cb89905e9ae1 100644
--- a/drivers/powercap/intel_rapl_msr.c
+++ b/drivers/powercap/intel_rapl_msr.c
@@ -21,15 +21,33 @@
#include <linux/intel_rapl.h>
#include <linux/processor.h>
#include <linux/platform_device.h>
+#include <linux/units.h>
+#include <linux/bits.h>
#include <asm/cpu_device_id.h>
#include <asm/intel-family.h>
+#include <asm/iosf_mbi.h>
#include <asm/msr.h>
/* Local defines */
#define MSR_PLATFORM_POWER_LIMIT 0x0000065C
#define MSR_VR_CURRENT_CONFIG 0x00000601
+#define ENERGY_UNIT_SCALE 1000 /* scale from driver unit to powercap unit */
+
+#define POWER_UNIT_OFFSET 0x00
+#define POWER_UNIT_MASK GENMASK(3, 0)
+
+#define ENERGY_UNIT_OFFSET 0x08
+#define ENERGY_UNIT_MASK GENMASK(12, 8)
+
+#define TIME_UNIT_OFFSET 0x10
+#define TIME_UNIT_MASK GENMASK(19, 16)
+
+/* Sideband MBI registers */
+#define IOSF_CPU_POWER_BUDGET_CTL_BYT 0x02
+#define IOSF_CPU_POWER_BUDGET_CTL_TNG 0xDF
+
/* private data for RAPL MSR Interface */
static struct rapl_if_priv *rapl_msr_priv;
@@ -186,6 +204,201 @@ static const struct x86_cpu_id pmu_support_ids[] = {
{}
};
+static int rapl_check_unit_atom(struct rapl_domain *rd)
+{
+ struct reg_action ra;
+ u32 value;
+
+ ra.reg = rd->regs[RAPL_DOMAIN_REG_UNIT];
+ ra.mask = ~0;
+ if (rapl_msr_read_raw(rd->rp->lead_cpu, &ra, false)) {
+ pr_err("Failed to read power unit REG 0x%llx on %s:%s, exit.\n",
+ ra.reg.val, rd->rp->name, rd->name);
+ return -ENODEV;
+ }
+
+ value = (ra.value & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
+ rd->energy_unit = ENERGY_UNIT_SCALE * BIT(value);
+
+ value = (ra.value & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET;
+ rd->power_unit = BIT(value) * MILLIWATT_PER_WATT;
+
+ value = (ra.value & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET;
+ rd->time_unit = USEC_PER_SEC / BIT(value);
+
+ pr_debug("Atom %s:%s energy=%dpJ, time=%dus, power=%duW\n",
+ rd->rp->name, rd->name, rd->energy_unit, rd->time_unit, rd->power_unit);
+
+ return 0;
+}
+
+static void set_floor_freq_atom(struct rapl_domain *rd, bool enable)
+{
+ static u32 power_ctrl_orig_val;
+ const struct rapl_defaults *defaults = rd->rp->priv->defaults;
+ u32 mdata;
+
+ if (!defaults->floor_freq_reg_addr) {
+ pr_err("Invalid floor frequency config register\n");
+ return;
+ }
+
+ if (!power_ctrl_orig_val)
+ iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_CR_READ,
+ defaults->floor_freq_reg_addr,
+ &power_ctrl_orig_val);
+ mdata = power_ctrl_orig_val;
+ if (enable) {
+ mdata &= ~GENMASK(14, 8);
+ mdata |= BIT(8);
+ }
+ iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_CR_WRITE,
+ defaults->floor_freq_reg_addr, mdata);
+}
+
+static u64 rapl_compute_time_window_atom(struct rapl_domain *rd, u64 value,
+ bool to_raw)
+{
+ if (to_raw)
+ return div64_u64(value, rd->time_unit);
+
+ /*
+ * Atom time unit encoding is straight forward val * time_unit,
+ * where time_unit is default to 1 sec. Never 0.
+ */
+ return value ? value * rd->time_unit : rd->time_unit;
+}
+
+static const struct rapl_defaults rapl_defaults_core = {
+ .floor_freq_reg_addr = 0,
+ .check_unit = rapl_default_check_unit,
+ .set_floor_freq = rapl_default_set_floor_freq,
+ .compute_time_window = rapl_default_compute_time_window,
+};
+
+static const struct rapl_defaults rapl_defaults_hsw_server = {
+ .check_unit = rapl_default_check_unit,
+ .set_floor_freq = rapl_default_set_floor_freq,
+ .compute_time_window = rapl_default_compute_time_window,
+ .dram_domain_energy_unit = 15300,
+};
+
+static const struct rapl_defaults rapl_defaults_spr_server = {
+ .check_unit = rapl_default_check_unit,
+ .set_floor_freq = rapl_default_set_floor_freq,
+ .compute_time_window = rapl_default_compute_time_window,
+ .psys_domain_energy_unit = NANOJOULE_PER_JOULE,
+ .spr_psys_bits = true,
+};
+
+static const struct rapl_defaults rapl_defaults_byt = {
+ .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_BYT,
+ .check_unit = rapl_check_unit_atom,
+ .set_floor_freq = set_floor_freq_atom,
+ .compute_time_window = rapl_compute_time_window_atom,
+};
+
+static const struct rapl_defaults rapl_defaults_tng = {
+ .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_TNG,
+ .check_unit = rapl_check_unit_atom,
+ .set_floor_freq = set_floor_freq_atom,
+ .compute_time_window = rapl_compute_time_window_atom,
+};
+
+static const struct rapl_defaults rapl_defaults_ann = {
+ .floor_freq_reg_addr = 0,
+ .check_unit = rapl_check_unit_atom,
+ .set_floor_freq = NULL,
+ .compute_time_window = rapl_compute_time_window_atom,
+};
+
+static const struct rapl_defaults rapl_defaults_cht = {
+ .floor_freq_reg_addr = 0,
+ .check_unit = rapl_check_unit_atom,
+ .set_floor_freq = NULL,
+ .compute_time_window = rapl_compute_time_window_atom,
+};
+
+static const struct rapl_defaults rapl_defaults_amd = {
+ .check_unit = rapl_default_check_unit,
+};
+
+static const struct x86_cpu_id rapl_ids[] = {
+ X86_MATCH_VFM(INTEL_SANDYBRIDGE, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_SANDYBRIDGE_X, &rapl_defaults_core),
+
+ X86_MATCH_VFM(INTEL_IVYBRIDGE, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &rapl_defaults_core),
+
+ X86_MATCH_VFM(INTEL_HASWELL, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_HASWELL_L, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_HASWELL_G, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_HASWELL_X, &rapl_defaults_hsw_server),
+
+ X86_MATCH_VFM(INTEL_BROADWELL, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_BROADWELL_G, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_BROADWELL_D, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_BROADWELL_X, &rapl_defaults_hsw_server),
+
+ X86_MATCH_VFM(INTEL_SKYLAKE, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_SKYLAKE_L, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_SKYLAKE_X, &rapl_defaults_hsw_server),
+ X86_MATCH_VFM(INTEL_KABYLAKE_L, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_KABYLAKE, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_CANNONLAKE_L, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_ICELAKE_L, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_ICELAKE, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_ICELAKE_NNPI, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_ICELAKE_X, &rapl_defaults_hsw_server),
+ X86_MATCH_VFM(INTEL_ICELAKE_D, &rapl_defaults_hsw_server),
+ X86_MATCH_VFM(INTEL_COMETLAKE_L, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_COMETLAKE, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_TIGERLAKE_L, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_TIGERLAKE, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_ROCKETLAKE, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_ALDERLAKE, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_ALDERLAKE_L, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_RAPTORLAKE, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_RAPTORLAKE_P, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_RAPTORLAKE_S, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_BARTLETTLAKE, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_METEORLAKE, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_METEORLAKE_L, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &rapl_defaults_spr_server),
+ X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &rapl_defaults_spr_server),
+ X86_MATCH_VFM(INTEL_LUNARLAKE_M, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_WILDCATLAKE_L, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_NOVALAKE, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_NOVALAKE_L, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_ARROWLAKE_H, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_ARROWLAKE, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_ARROWLAKE_U, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_LAKEFIELD, &rapl_defaults_core),
+
+ X86_MATCH_VFM(INTEL_ATOM_SILVERMONT, &rapl_defaults_byt),
+ X86_MATCH_VFM(INTEL_ATOM_AIRMONT, &rapl_defaults_cht),
+ X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID, &rapl_defaults_tng),
+ X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID2, &rapl_defaults_ann),
+ X86_MATCH_VFM(INTEL_ATOM_GOLDMONT, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_PLUS, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_D, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_ATOM_TREMONT, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_ATOM_TREMONT_D, &rapl_defaults_core),
+ X86_MATCH_VFM(INTEL_ATOM_TREMONT_L, &rapl_defaults_core),
+
+ X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &rapl_defaults_hsw_server),
+ X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &rapl_defaults_hsw_server),
+
+ X86_MATCH_VENDOR_FAM(AMD, 0x17, &rapl_defaults_amd),
+ X86_MATCH_VENDOR_FAM(AMD, 0x19, &rapl_defaults_amd),
+ X86_MATCH_VENDOR_FAM(AMD, 0x1A, &rapl_defaults_amd),
+ X86_MATCH_VENDOR_FAM(HYGON, 0x18, &rapl_defaults_amd),
+ {}
+};
+MODULE_DEVICE_TABLE(x86cpu, rapl_ids);
+
static int rapl_msr_probe(struct platform_device *pdev)
{
const struct x86_cpu_id *id = x86_match_cpu(pl4_support_ids);
@@ -205,6 +418,7 @@ static int rapl_msr_probe(struct platform_device *pdev)
}
rapl_msr_priv->read_raw = rapl_msr_read_raw;
rapl_msr_priv->write_raw = rapl_msr_write_raw;
+ rapl_msr_priv->defaults = (const struct rapl_defaults *)pdev->dev.platform_data;
if (id) {
rapl_msr_priv->limits[RAPL_DOMAIN_PACKAGE] |= BIT(POWER_LIMIT4);
@@ -259,7 +473,41 @@ static struct platform_driver intel_rapl_msr_driver = {
},
};
-module_platform_driver(intel_rapl_msr_driver);
+static struct platform_device *rapl_msr_platdev;
+
+static int intel_rapl_msr_init(void)
+{
+ const struct rapl_defaults *def;
+ const struct x86_cpu_id *id;
+ int ret;
+
+ ret = platform_driver_register(&intel_rapl_msr_driver);
+ if (ret)
+ return ret;
+
+ /* Create the MSR RAPL platform device for supported platforms */
+ id = x86_match_cpu(rapl_ids);
+ if (!id)
+ return 0;
+
+ def = (const struct rapl_defaults *)id->driver_data;
+
+ rapl_msr_platdev = platform_device_register_data(NULL, "intel_rapl_msr", 0, def,
+ sizeof(*def));
+ if (IS_ERR(rapl_msr_platdev))
+ pr_debug("intel_rapl_msr device register failed, ret:%ld\n",
+ PTR_ERR(rapl_msr_platdev));
+
+ return 0;
+}
+module_init(intel_rapl_msr_init);
+
+static void intel_rapl_msr_exit(void)
+{
+ platform_device_unregister(rapl_msr_platdev);
+ platform_driver_unregister(&intel_rapl_msr_driver);
+}
+module_exit(intel_rapl_msr_exit);
MODULE_DESCRIPTION("Driver for Intel RAPL (Running Average Power Limit) control via MSR interface");
MODULE_AUTHOR("Zhang Rui <rui.zhang@intel.com>");
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v1 0/9] Move RAPL defaults to interface drivers
2026-01-29 18:36 [PATCH v1 0/9] Move RAPL defaults to interface drivers Kuppuswamy Sathyanarayanan
` (8 preceding siblings ...)
2026-01-29 18:36 ` [PATCH v1 9/9] powercap: intel_rapl: Move MSR default settings into MSR interface driver Kuppuswamy Sathyanarayanan
@ 2026-01-29 19:20 ` srinivas pandruvada
9 siblings, 0 replies; 13+ messages in thread
From: srinivas pandruvada @ 2026-01-29 19:20 UTC (permalink / raw)
To: Kuppuswamy Sathyanarayanan, Rafael J . Wysocki, Daniel Lezcano
Cc: Zhang Rui, Lukasz Luba, linux-pm, linux-kernel
On Thu, 2026-01-29 at 10:36 -0800, Kuppuswamy Sathyanarayanan wrote:
> Hi All,
>
> The Intel RAPL common driver has accumulated a significant amount of
> interface-specific logic over time. There is very little common code
> shared across the MSR, TPMI, and MMIO interface-specific defaults.
> Keeping these interface-specific defaults in the common layer
> therefore
> provides no real benefit and instead increases complexity and
> maintenance burden.
>
> As a first step toward cleaning this up, this series moves
> rapl_defaults ownership from the common driver into the individual
> interface drivers and allows each interface to provide its own
> defaults
> directly. Additional interface-specific cleanups in the RAPL common
> driver will be addressed in follow-up work. This series is a
> continuation of the earlier cleanup and refactoring effort initiated
> by Zhang Rui.
>
For the series:
Acked-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
> Patch Summary:
>
> Patch 1-4/9: Preparatory patches that do code cleanups in
> intel_rapl_common
> driver.
> Patch 5/9: Preparatory patch that renames/declares the common
> functions.
> Patch 6/9: Move TPMI default settings from the common driver into the
> TPMI interface driver.
>
> Patch 7/9: Move MMIO default settings from the common driver into the
> MMIO interface driver.
>
> Patch 8/9: Register the PM notifier only when a RAPL package exists.
>
> Patch 9/9: Move MSR default settings from the common driver into the
> MSR
> interface driver.
>
> No functional changes are intended across the series. This is
> strictly a
> structural refactoring to simplify the common RAPL code and prepare
> it
> for further cleanups.
>
> Kuppuswamy Sathyanarayanan (9):
> powercap: intel_rapl: Add a symbol namespace for intel_rapl exports
> powercap: intel_rapl: Cleanup coding style
> powercap: intel_rapl: Use GENMASK() and BIT() macros
> powercap: intel_rapl: Use unit conversion macros from units.h
> powercap: intel_rapl: Allow interface drivers to configure
> rapl_defaults
> powercap: intel_rapl: Move TPMI default settings into TPMI
> interface
> driver
> thermal: intel: int340x: processor: Move RAPL defaults to MMIO
> driver
> powercap: intel_rapl: Register PM notifier only when RAPL package
> exists
> powercap: intel_rapl: Move MSR default settings into MSR interface
> driver
>
> drivers/powercap/intel_rapl_common.c | 755 ++++++----------
> --
> drivers/powercap/intel_rapl_msr.c | 251 +++++-
> drivers/powercap/intel_rapl_tpmi.c | 48 ++
> .../int340x_thermal/processor_thermal_rapl.c | 9 +
> include/linux/intel_rapl.h | 17 +-
> include/linux/units.h | 3 +
> 6 files changed, 561 insertions(+), 522 deletions(-)
^ permalink raw reply [flat|nested] 13+ messages in thread