Re: [PATCH v7 3/3] PCI: Add support for PCIe WAKE# interrupt

[kernel test robot <lkp@intel.com>]

Hi Krishna,

kernel test robot noticed the following build errors:

[auto build test ERROR on cee73b1e840c154f64ace682cb477c1ae2e29cc4]

url:    https://github.com/intel-lab-lkp/linux/commits/Krishna-Chaitanya-Chundru/PM-sleep-wakeirq-Add-support-for-dedicated-shared-wake-IRQ-setup/20260218-162247
base:   cee73b1e840c154f64ace682cb477c1ae2e29cc4
patch link:    https://lore.kernel.org/r/20260218-wakeirq_support-v7-3-0d4689830207%40oss.qualcomm.com
patch subject: [PATCH v7 3/3] PCI: Add support for PCIe WAKE# interrupt
config: sparc64-randconfig-002-20260218 (https://download.01.org/0day-ci/archive/20260219/202602190038.BHg9UcM5-lkp@intel.com/config)
compiler: sparc64-linux-gcc (GCC) 12.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260219/202602190038.BHg9UcM5-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202602190038.BHg9UcM5-lkp@intel.com/

All errors (new ones prefixed by >>):

   sparc64-linux-ld: drivers/pci/pci.o: in function `platform_pci_configure_wake':
>> drivers/pci/pci.c:1128:(.text+0x39c8): undefined reference to `pci_configure_of_wake_gpio'
   sparc64-linux-ld: drivers/pci/pci.o: in function `platform_pci_remove_wake':
>> drivers/pci/pci.c:1133:(.text+0x39d4): undefined reference to `pci_remove_of_wake_gpio'


vim +1128 drivers/pci/pci.c

  1125	
  1126	void platform_pci_configure_wake(struct pci_dev *dev)
  1127	{
> 1128		return pci_configure_of_wake_gpio(dev);
  1129	}
  1130	
  1131	void platform_pci_remove_wake(struct pci_dev *dev)
  1132	{
> 1133		return pci_remove_of_wake_gpio(dev);
  1134	}
  1135	/**
  1136	 * pci_update_current_state - Read power state of given device and cache it
  1137	 * @dev: PCI device to handle.
  1138	 * @state: State to cache in case the device doesn't have the PM capability
  1139	 *
  1140	 * The power state is read from the PMCSR register, which however is
  1141	 * inaccessible in D3cold.  The platform firmware is therefore queried first
  1142	 * to detect accessibility of the register.  In case the platform firmware
  1143	 * reports an incorrect state or the device isn't power manageable by the
  1144	 * platform at all, we try to detect D3cold by testing accessibility of the
  1145	 * vendor ID in config space.
  1146	 */
  1147	void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
  1148	{
  1149		if (platform_pci_get_power_state(dev) == PCI_D3cold) {
  1150			dev->current_state = PCI_D3cold;
  1151		} else if (dev->pm_cap) {
  1152			u16 pmcsr;
  1153	
  1154			pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
  1155			if (PCI_POSSIBLE_ERROR(pmcsr)) {
  1156				dev->current_state = PCI_D3cold;
  1157				return;
  1158			}
  1159			dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK;
  1160		} else {
  1161			dev->current_state = state;
  1162		}
  1163	}
  1164	

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