[PATCH 0/6] Enable NVL support in intel_pmc_core

[PATCH 0/6] Enable NVL support in intel_pmc_core

[Xi Pardee]

This patch series introduces two new features, enhances existing
functionalities, and adds NVL support to the intel_pmc_core driver.

The first two patches add new attributes to improve Package C-state
debugging. The third and fourth patches refine current functionality
for better support. The fifth patch enables the intel_pmc_core driver
retrieves PMC information only for available PMCs. Finally, the last
patch adds support for Nova Lake platforms.

Xi Pardee (6):
  platform/x86/intel/pmc: Enable PkgC LTR blocking counter
  platform/x86/intel/pmc: Enable Pkgc blocking residency counter
  platform/x86/intel/pmc: Use PCI DID for PMC SSRAM device discovery
  platform/x86/intel/pmc: Add support for variable DMU offsets
  platform/x86/intel/pmc: Retrieve PMC info only for available PMCs
  platform/x86/intel/pmc: Add Nova Lake support to intel_pmc_core driver

 drivers/platform/x86/intel/pmc/Makefile |    2 +-
 drivers/platform/x86/intel/pmc/arl.c    |   11 +-
 drivers/platform/x86/intel/pmc/core.c   |  141 ++-
 drivers/platform/x86/intel/pmc/core.h   |   64 +-
 drivers/platform/x86/intel/pmc/lnl.c    |    5 +-
 drivers/platform/x86/intel/pmc/mtl.c    |    6 +-
 drivers/platform/x86/intel/pmc/nvl.c    | 1537 +++++++++++++++++++++++
 drivers/platform/x86/intel/pmc/ptl.c    |    7 +-
 drivers/platform/x86/intel/pmc/wcl.c    |    5 +-
 9 files changed, 1743 insertions(+), 35 deletions(-)
 create mode 100644 drivers/platform/x86/intel/pmc/nvl.c

-- 
2.43.0

[PATCH 1/6] platform/x86/intel/pmc: Enable PkgC LTR blocking counter

[Xi Pardee]

Enable the Package C-state LTR blocking counter in the PMT telemetry
region. This counter records how many times any Package C-state entry
is blocked for the specified reasons.

Signed-off-by: Xi Pardee <xi.pardee@linux.intel.com>
---
 drivers/platform/x86/intel/pmc/core.c | 77 ++++++++++++++++++++++-----
 drivers/platform/x86/intel/pmc/core.h | 15 +++++-
 2 files changed, 79 insertions(+), 13 deletions(-)

diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c
index 02b303418d185..bf95a1f2ba428 100644
--- a/drivers/platform/x86/intel/pmc/core.c
+++ b/drivers/platform/x86/intel/pmc/core.c
@@ -1071,6 +1071,28 @@ static int pmc_core_die_c6_us_show(struct seq_file *s, void *unused)
 }
 DEFINE_SHOW_ATTRIBUTE(pmc_core_die_c6_us);
 
+static int pmc_core_pkgc_ltr_blocker_show(struct seq_file *s, void *unused)
+{
+	struct pmc_dev *pmcdev = s->private;
+	const char **pkgc_ltr_blocker_counters;
+	u32 counter, offset;
+	unsigned int i;
+	int ret;
+
+	offset = pmcdev->pkgc_ltr_blocker_offset;
+	pkgc_ltr_blocker_counters = pmcdev->pkgc_ltr_blocker_counters;
+	for (i = 0; pkgc_ltr_blocker_counters[i]; i++, offset++) {
+		ret = pmt_telem_read32(pmcdev->pc_ep, offset,
+				       &counter, 1);
+		if (ret)
+			return ret;
+		seq_printf(s, "%-30s %-30u\n", pkgc_ltr_blocker_counters[i], counter);
+	}
+
+	return 0;
+}
+DEFINE_SHOW_ATTRIBUTE(pmc_core_pkgc_ltr_blocker);
+
 static int pmc_core_lpm_latch_mode_show(struct seq_file *s, void *unused)
 {
 	struct pmc_dev *pmcdev = s->private;
@@ -1322,7 +1344,7 @@ static struct telem_endpoint *pmc_core_register_endpoint(struct pci_dev *pcidev,
 	return ERR_PTR(-ENODEV);
 }
 
-void pmc_core_punit_pmt_init(struct pmc_dev *pmcdev, u32 *guids)
+void pmc_core_punit_pmt_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info)
 {
 	struct telem_endpoint *ep;
 	struct pci_dev *pcidev;
@@ -1333,17 +1355,35 @@ void pmc_core_punit_pmt_init(struct pmc_dev *pmcdev, u32 *guids)
 		return;
 	}
 
-	ep = pmc_core_register_endpoint(pcidev, guids);
-	pci_dev_put(pcidev);
-	if (IS_ERR(ep)) {
-		dev_err(&pmcdev->pdev->dev,
-			"pmc_core: couldn't get DMU telem endpoint %ld",
-			PTR_ERR(ep));
-		return;
+	if (pmc_dev_info->dmu_guids) {
+		ep = pmc_core_register_endpoint(pcidev, pmc_dev_info->dmu_guids);
+		if (IS_ERR(ep)) {
+			dev_err(&pmcdev->pdev->dev,
+				"pmc_core: couldn't get DMU telem endpoint %ld",
+				PTR_ERR(ep));
+			goto release_dev;
+		}
+
+		pmcdev->punit_ep = ep;
+		pmcdev->die_c6_offset = MTL_PMT_DMU_DIE_C6_OFFSET;
+	}
+
+	if (pmc_dev_info->pc_guid) {
+		ep = pmt_telem_find_and_register_endpoint(pcidev, pmc_dev_info->pc_guid, 0);
+		if (IS_ERR(ep)) {
+			dev_err(&pmcdev->pdev->dev,
+				"pmc_core: couldn't get Package C-state telem endpoint %ld",
+				PTR_ERR(ep));
+			goto release_dev;
+		}
+
+		pmcdev->pc_ep = ep;
+		pmcdev->pkgc_ltr_blocker_counters = pmc_dev_info->pkgc_ltr_blocker_counters;
+		pmcdev->pkgc_ltr_blocker_offset = pmc_dev_info->pkgc_ltr_blocker_offset;
 	}
 
-	pmcdev->punit_ep = ep;
-	pmcdev->die_c6_offset = MTL_PMT_DMU_DIE_C6_OFFSET;
+release_dev:
+	pci_dev_put(pcidev);
 }
 
 void pmc_core_set_device_d3(unsigned int device)
@@ -1467,6 +1507,13 @@ static void pmc_core_dbgfs_register(struct pmc_dev *pmcdev, struct pmc_dev_info
 				    pmcdev->dbgfs_dir, pmcdev,
 				    &pmc_core_die_c6_us_fops);
 	}
+
+	if (pmcdev->pc_ep) {
+		debugfs_create_file("pkgc_ltr_blocker_show", 0444,
+				    pmcdev->dbgfs_dir, pmcdev,
+				    &pmc_core_pkgc_ltr_blocker_fops);
+	}
+
 }
 
 /*
@@ -1717,8 +1764,8 @@ int generic_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info)
 	}
 
 	pmc_core_get_low_power_modes(pmcdev);
-	if (pmc_dev_info->dmu_guids)
-		pmc_core_punit_pmt_init(pmcdev, pmc_dev_info->dmu_guids);
+	if (pmc_dev_info->dmu_guids || pmc_dev_info->pc_guid)
+		pmc_core_punit_pmt_init(pmcdev, pmc_dev_info);
 
 	if (ssram) {
 		ret = pmc_core_get_telem_info(pmcdev, pmc_dev_info);
@@ -1739,6 +1786,9 @@ int generic_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info)
 	if (pmcdev->punit_ep)
 		pmt_telem_unregister_endpoint(pmcdev->punit_ep);
 
+	if (pmcdev->pc_ep)
+		pmt_telem_unregister_endpoint(pmcdev->pc_ep);
+
 	return ret;
 }
 
@@ -1835,6 +1885,9 @@ static void pmc_core_clean_structure(struct platform_device *pdev)
 	if (pmcdev->punit_ep)
 		pmt_telem_unregister_endpoint(pmcdev->punit_ep);
 
+	if (pmcdev->pc_ep)
+		pmt_telem_unregister_endpoint(pmcdev->pc_ep);
+
 	platform_set_drvdata(pdev, NULL);
 }
 
diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h
index 118c8740ad3aa..a20aab73c1409 100644
--- a/drivers/platform/x86/intel/pmc/core.h
+++ b/drivers/platform/x86/intel/pmc/core.h
@@ -453,6 +453,9 @@ struct pmc {
  * @suspend:		Function to perform platform specific suspend
  * @resume:		Function to perform platform specific resume
  *
+ * @pkgc_ltr_blocker_counters: Array of PKGC LTR blocker counters
+ * @pkgc_ltr_blocker_offset: Offset to PKGC LTR blockers in telemetry region
+ *
  * pmc_dev contains info about power management controller device.
  */
 struct pmc_dev {
@@ -471,8 +474,12 @@ struct pmc_dev {
 	u8 num_of_pkgc;
 
 	u32 die_c6_offset;
+	struct telem_endpoint *pc_ep;
 	struct telem_endpoint *punit_ep;
 	struct pmc_info *regmap_list;
+
+	const char **pkgc_ltr_blocker_counters;
+	u32 pkgc_ltr_blocker_offset;
 };
 
 enum pmc_index {
@@ -486,12 +493,15 @@ enum pmc_index {
  * struct pmc_dev_info - Structure to keep PMC device info
  * @pci_func:		Function number of the primary PMC
  * @dmu_guids:		List of Die Management Unit GUID
+ * @pc_guid:		GUID for telemetry region to read PKGC blocker info
+ * @pkgc_ltr_blocker_offset: Offset to PKGC LTR blockers in telemetry region
  * @regmap_list:	Pointer to a list of pmc_info structure that could be
  *			available for the platform. When set, this field implies
  *			SSRAM support.
  * @map:		Pointer to a pmc_reg_map struct that contains platform
  *			specific attributes of the primary PMC
  * @sub_req_show:	File operations to show substate requirements
+ * @pkgc_ltr_blocker_counters: Array of PKGC LTR blocker counters
  * @suspend:		Function to perform platform specific suspend
  * @resume:		Function to perform platform specific resume
  * @init:		Function to perform platform specific init action
@@ -500,9 +510,12 @@ enum pmc_index {
 struct pmc_dev_info {
 	u8 pci_func;
 	u32 *dmu_guids;
+	u32 pc_guid;
+	u32 pkgc_ltr_blocker_offset;
 	struct pmc_info *regmap_list;
 	const struct pmc_reg_map *map;
 	const struct file_operations *sub_req_show;
+	const char **pkgc_ltr_blocker_counters;
 	void (*suspend)(struct pmc_dev *pmcdev);
 	int (*resume)(struct pmc_dev *pmcdev);
 	int (*init)(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info);
@@ -535,7 +548,7 @@ int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value, int ignore);
 
 int pmc_core_resume_common(struct pmc_dev *pmcdev);
 int get_primary_reg_base(struct pmc *pmc);
-void pmc_core_punit_pmt_init(struct pmc_dev *pmcdev, u32 *guids);
+void pmc_core_punit_pmt_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info);
 void pmc_core_set_device_d3(unsigned int device);
 
 int generic_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info);
-- 
2.43.0

Re: [PATCH 1/6] platform/x86/intel/pmc: Enable PkgC LTR blocking counter

[Ilpo Järvinen]

On Mon, 2 Mar 2026, Xi Pardee wrote:

> Enable the Package C-state LTR blocking counter in the PMT telemetry
> region. This counter records how many times any Package C-state entry
> is blocked for the specified reasons.
> 
> Signed-off-by: Xi Pardee <xi.pardee@linux.intel.com>
> ---
>  drivers/platform/x86/intel/pmc/core.c | 77 ++++++++++++++++++++++-----
>  drivers/platform/x86/intel/pmc/core.h | 15 +++++-
>  2 files changed, 79 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c
> index 02b303418d185..bf95a1f2ba428 100644
> --- a/drivers/platform/x86/intel/pmc/core.c
> +++ b/drivers/platform/x86/intel/pmc/core.c
> @@ -1071,6 +1071,28 @@ static int pmc_core_die_c6_us_show(struct seq_file *s, void *unused)
>  }
>  DEFINE_SHOW_ATTRIBUTE(pmc_core_die_c6_us);
>  
> +static int pmc_core_pkgc_ltr_blocker_show(struct seq_file *s, void *unused)
> +{
> +	struct pmc_dev *pmcdev = s->private;
> +	const char **pkgc_ltr_blocker_counters;
> +	u32 counter, offset;
> +	unsigned int i;
> +	int ret;
> +
> +	offset = pmcdev->pkgc_ltr_blocker_offset;
> +	pkgc_ltr_blocker_counters = pmcdev->pkgc_ltr_blocker_counters;
> +	for (i = 0; pkgc_ltr_blocker_counters[i]; i++, offset++) {
> +		ret = pmt_telem_read32(pmcdev->pc_ep, offset,
> +				       &counter, 1);

Fits easily to one line. Though, I'm not sure if offset variable improves 
things, more like it makes this more complex than it need to be. To me it 
would look more straightforward to do just:

		ret = pmt_telem_read32(pmcdev->pc_ep, 
				       pmcdev->pkgc_ltr_blocker_offset + i,
				       ...);

> +		if (ret)
> +			return ret;
> +		seq_printf(s, "%-30s %-30u\n", pkgc_ltr_blocker_counters[i], counter);
> +	}
> +
> +	return 0;
> +}
> +DEFINE_SHOW_ATTRIBUTE(pmc_core_pkgc_ltr_blocker);
> +
>  static int pmc_core_lpm_latch_mode_show(struct seq_file *s, void *unused)
>  {
>  	struct pmc_dev *pmcdev = s->private;
> @@ -1322,7 +1344,7 @@ static struct telem_endpoint *pmc_core_register_endpoint(struct pci_dev *pcidev,
>  	return ERR_PTR(-ENODEV);
>  }
>  
> -void pmc_core_punit_pmt_init(struct pmc_dev *pmcdev, u32 *guids)
> +void pmc_core_punit_pmt_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info)
>  {
>  	struct telem_endpoint *ep;
>  	struct pci_dev *pcidev;
> @@ -1333,17 +1355,35 @@ void pmc_core_punit_pmt_init(struct pmc_dev *pmcdev, u32 *guids)
>  		return;
>  	}
>  
> -	ep = pmc_core_register_endpoint(pcidev, guids);
> -	pci_dev_put(pcidev);
> -	if (IS_ERR(ep)) {
> -		dev_err(&pmcdev->pdev->dev,
> -			"pmc_core: couldn't get DMU telem endpoint %ld",
> -			PTR_ERR(ep));
> -		return;
> +	if (pmc_dev_info->dmu_guids) {
> +		ep = pmc_core_register_endpoint(pcidev, pmc_dev_info->dmu_guids);
> +		if (IS_ERR(ep)) {
> +			dev_err(&pmcdev->pdev->dev,
> +				"pmc_core: couldn't get DMU telem endpoint %ld",
> +				PTR_ERR(ep));
> +			goto release_dev;
> +		}
> +
> +		pmcdev->punit_ep = ep;
> +		pmcdev->die_c6_offset = MTL_PMT_DMU_DIE_C6_OFFSET;
> +	}
> +
> +	if (pmc_dev_info->pc_guid) {
> +		ep = pmt_telem_find_and_register_endpoint(pcidev, pmc_dev_info->pc_guid, 0);
> +		if (IS_ERR(ep)) {
> +			dev_err(&pmcdev->pdev->dev,
> +				"pmc_core: couldn't get Package C-state telem endpoint %ld",
> +				PTR_ERR(ep));
> +			goto release_dev;
> +		}
> +
> +		pmcdev->pc_ep = ep;
> +		pmcdev->pkgc_ltr_blocker_counters = pmc_dev_info->pkgc_ltr_blocker_counters;
> +		pmcdev->pkgc_ltr_blocker_offset = pmc_dev_info->pkgc_ltr_blocker_offset;
>  	}
>  
> -	pmcdev->punit_ep = ep;
> -	pmcdev->die_c6_offset = MTL_PMT_DMU_DIE_C6_OFFSET;
> +release_dev:
> +	pci_dev_put(pcidev);

Use __free(pci_dev_put) instead of complicating the code flow. 
Please remember to place the variable declaration at the place of 
assignment (no = NULL; assignments with __free()). You may want to do the 
__free() conversion in own patch preceeding this.

-- 
 i.

>  }
>  
>  void pmc_core_set_device_d3(unsigned int device)
> @@ -1467,6 +1507,13 @@ static void pmc_core_dbgfs_register(struct pmc_dev *pmcdev, struct pmc_dev_info
>  				    pmcdev->dbgfs_dir, pmcdev,
>  				    &pmc_core_die_c6_us_fops);
>  	}
> +
> +	if (pmcdev->pc_ep) {
> +		debugfs_create_file("pkgc_ltr_blocker_show", 0444,
> +				    pmcdev->dbgfs_dir, pmcdev,
> +				    &pmc_core_pkgc_ltr_blocker_fops);
> +	}
> +
>  }
>  
>  /*
> @@ -1717,8 +1764,8 @@ int generic_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info)
>  	}
>  
>  	pmc_core_get_low_power_modes(pmcdev);
> -	if (pmc_dev_info->dmu_guids)
> -		pmc_core_punit_pmt_init(pmcdev, pmc_dev_info->dmu_guids);
> +	if (pmc_dev_info->dmu_guids || pmc_dev_info->pc_guid)
> +		pmc_core_punit_pmt_init(pmcdev, pmc_dev_info);
>  
>  	if (ssram) {
>  		ret = pmc_core_get_telem_info(pmcdev, pmc_dev_info);
> @@ -1739,6 +1786,9 @@ int generic_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info)
>  	if (pmcdev->punit_ep)
>  		pmt_telem_unregister_endpoint(pmcdev->punit_ep);
>  
> +	if (pmcdev->pc_ep)
> +		pmt_telem_unregister_endpoint(pmcdev->pc_ep);
> +
>  	return ret;
>  }
>  
> @@ -1835,6 +1885,9 @@ static void pmc_core_clean_structure(struct platform_device *pdev)
>  	if (pmcdev->punit_ep)
>  		pmt_telem_unregister_endpoint(pmcdev->punit_ep);
>  
> +	if (pmcdev->pc_ep)
> +		pmt_telem_unregister_endpoint(pmcdev->pc_ep);
> +
>  	platform_set_drvdata(pdev, NULL);
>  }
>  
> diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h
> index 118c8740ad3aa..a20aab73c1409 100644
> --- a/drivers/platform/x86/intel/pmc/core.h
> +++ b/drivers/platform/x86/intel/pmc/core.h
> @@ -453,6 +453,9 @@ struct pmc {
>   * @suspend:		Function to perform platform specific suspend
>   * @resume:		Function to perform platform specific resume
>   *
> + * @pkgc_ltr_blocker_counters: Array of PKGC LTR blocker counters
> + * @pkgc_ltr_blocker_offset: Offset to PKGC LTR blockers in telemetry region
> + *
>   * pmc_dev contains info about power management controller device.
>   */
>  struct pmc_dev {
> @@ -471,8 +474,12 @@ struct pmc_dev {
>  	u8 num_of_pkgc;
>  
>  	u32 die_c6_offset;
> +	struct telem_endpoint *pc_ep;
>  	struct telem_endpoint *punit_ep;
>  	struct pmc_info *regmap_list;
> +
> +	const char **pkgc_ltr_blocker_counters;
> +	u32 pkgc_ltr_blocker_offset;
>  };
>  
>  enum pmc_index {
> @@ -486,12 +493,15 @@ enum pmc_index {
>   * struct pmc_dev_info - Structure to keep PMC device info
>   * @pci_func:		Function number of the primary PMC
>   * @dmu_guids:		List of Die Management Unit GUID
> + * @pc_guid:		GUID for telemetry region to read PKGC blocker info
> + * @pkgc_ltr_blocker_offset: Offset to PKGC LTR blockers in telemetry region
>   * @regmap_list:	Pointer to a list of pmc_info structure that could be
>   *			available for the platform. When set, this field implies
>   *			SSRAM support.
>   * @map:		Pointer to a pmc_reg_map struct that contains platform
>   *			specific attributes of the primary PMC
>   * @sub_req_show:	File operations to show substate requirements
> + * @pkgc_ltr_blocker_counters: Array of PKGC LTR blocker counters
>   * @suspend:		Function to perform platform specific suspend
>   * @resume:		Function to perform platform specific resume
>   * @init:		Function to perform platform specific init action
> @@ -500,9 +510,12 @@ enum pmc_index {
>  struct pmc_dev_info {
>  	u8 pci_func;
>  	u32 *dmu_guids;
> +	u32 pc_guid;
> +	u32 pkgc_ltr_blocker_offset;
>  	struct pmc_info *regmap_list;
>  	const struct pmc_reg_map *map;
>  	const struct file_operations *sub_req_show;
> +	const char **pkgc_ltr_blocker_counters;
>  	void (*suspend)(struct pmc_dev *pmcdev);
>  	int (*resume)(struct pmc_dev *pmcdev);
>  	int (*init)(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info);
> @@ -535,7 +548,7 @@ int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value, int ignore);
>  
>  int pmc_core_resume_common(struct pmc_dev *pmcdev);
>  int get_primary_reg_base(struct pmc *pmc);
> -void pmc_core_punit_pmt_init(struct pmc_dev *pmcdev, u32 *guids);
> +void pmc_core_punit_pmt_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info);
>  void pmc_core_set_device_d3(unsigned int device);
>  
>  int generic_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info);
> 

[PATCH 2/6] platform/x86/intel/pmc: Enable Pkgc blocking residency counter

[Xi Pardee]

Enable the Package C-state blocking counter in the PMT telemetry
region. This counter reports the number of 10 µs intervals during
which a Package C-state 10.2/3 entry was blocked for the specified
reasons.

Signed-off-by: Xi Pardee <xi.pardee@linux.intel.com>
---
 drivers/platform/x86/intel/pmc/core.c | 27 +++++++++++++++++++++++++++
 drivers/platform/x86/intel/pmc/core.h |  8 ++++++++
 2 files changed, 35 insertions(+)

diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c
index bf95a1f2ba428..e5b48a68cf495 100644
--- a/drivers/platform/x86/intel/pmc/core.c
+++ b/drivers/platform/x86/intel/pmc/core.c
@@ -1093,6 +1093,28 @@ static int pmc_core_pkgc_ltr_blocker_show(struct seq_file *s, void *unused)
 }
 DEFINE_SHOW_ATTRIBUTE(pmc_core_pkgc_ltr_blocker);
 
+static int pmc_core_pkgc_blocker_residency_show(struct seq_file *s, void *unused)
+{
+	struct pmc_dev *pmcdev = s->private;
+	const char **pkgc_blocker_counters;
+	u32 counter, offset;
+	unsigned int i;
+	int ret;
+
+	offset = pmcdev->pkgc_blocker_offset;
+	pkgc_blocker_counters = pmcdev->pkgc_blocker_counters;
+	for (i = 0; pkgc_blocker_counters[i]; i++, offset++) {
+		ret = pmt_telem_read32(pmcdev->pc_ep, offset,
+				       &counter, 1);
+		if (ret)
+			return ret;
+		seq_printf(s, "%-30s %-30u\n", pkgc_blocker_counters[i], counter);
+	}
+
+	return 0;
+}
+DEFINE_SHOW_ATTRIBUTE(pmc_core_pkgc_blocker_residency);
+
 static int pmc_core_lpm_latch_mode_show(struct seq_file *s, void *unused)
 {
 	struct pmc_dev *pmcdev = s->private;
@@ -1380,6 +1402,8 @@ void pmc_core_punit_pmt_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_de
 		pmcdev->pc_ep = ep;
 		pmcdev->pkgc_ltr_blocker_counters = pmc_dev_info->pkgc_ltr_blocker_counters;
 		pmcdev->pkgc_ltr_blocker_offset = pmc_dev_info->pkgc_ltr_blocker_offset;
+		pmcdev->pkgc_blocker_counters = pmc_dev_info->pkgc_blocker_counters;
+		pmcdev->pkgc_blocker_offset = pmc_dev_info->pkgc_blocker_offset;
 	}
 
 release_dev:
@@ -1512,6 +1536,9 @@ static void pmc_core_dbgfs_register(struct pmc_dev *pmcdev, struct pmc_dev_info
 		debugfs_create_file("pkgc_ltr_blocker_show", 0444,
 				    pmcdev->dbgfs_dir, pmcdev,
 				    &pmc_core_pkgc_ltr_blocker_fops);
+		debugfs_create_file("pkgc_blocker_residency_show", 0444,
+				    pmcdev->dbgfs_dir, pmcdev,
+				    &pmc_core_pkgc_blocker_residency_fops);
 	}
 
 }
diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h
index a20aab73c1409..829b1dee3f636 100644
--- a/drivers/platform/x86/intel/pmc/core.h
+++ b/drivers/platform/x86/intel/pmc/core.h
@@ -455,6 +455,8 @@ struct pmc {
  *
  * @pkgc_ltr_blocker_counters: Array of PKGC LTR blocker counters
  * @pkgc_ltr_blocker_offset: Offset to PKGC LTR blockers in telemetry region
+ * @pkgc_blocker_counters: Array of PKGC blocker counters
+ * @pkgc_blocker_offset: Offset to PKGC blocker in telemetry region
  *
  * pmc_dev contains info about power management controller device.
  */
@@ -480,6 +482,8 @@ struct pmc_dev {
 
 	const char **pkgc_ltr_blocker_counters;
 	u32 pkgc_ltr_blocker_offset;
+	const char **pkgc_blocker_counters;
+	u32 pkgc_blocker_offset;
 };
 
 enum pmc_index {
@@ -495,6 +499,7 @@ enum pmc_index {
  * @dmu_guids:		List of Die Management Unit GUID
  * @pc_guid:		GUID for telemetry region to read PKGC blocker info
  * @pkgc_ltr_blocker_offset: Offset to PKGC LTR blockers in telemetry region
+ * @pkgc_blocker_offset:Offset to PKGC blocker in telemetry region
  * @regmap_list:	Pointer to a list of pmc_info structure that could be
  *			available for the platform. When set, this field implies
  *			SSRAM support.
@@ -502,6 +507,7 @@ enum pmc_index {
  *			specific attributes of the primary PMC
  * @sub_req_show:	File operations to show substate requirements
  * @pkgc_ltr_blocker_counters: Array of PKGC LTR blocker counters
+ * @pkgc_blocker_counters: Array of PKGC blocker counters
  * @suspend:		Function to perform platform specific suspend
  * @resume:		Function to perform platform specific resume
  * @init:		Function to perform platform specific init action
@@ -512,10 +518,12 @@ struct pmc_dev_info {
 	u32 *dmu_guids;
 	u32 pc_guid;
 	u32 pkgc_ltr_blocker_offset;
+	u32 pkgc_blocker_offset;
 	struct pmc_info *regmap_list;
 	const struct pmc_reg_map *map;
 	const struct file_operations *sub_req_show;
 	const char **pkgc_ltr_blocker_counters;
+	const char **pkgc_blocker_counters;
 	void (*suspend)(struct pmc_dev *pmcdev);
 	int (*resume)(struct pmc_dev *pmcdev);
 	int (*init)(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info);
-- 
2.43.0

Re: [PATCH 2/6] platform/x86/intel/pmc: Enable Pkgc blocking residency counter

[Ilpo Järvinen]

[-- Attachment #1: Type: text/plain, Size: 5133 bytes --]

On Mon, 2 Mar 2026, Xi Pardee wrote:

> Enable the Package C-state blocking counter in the PMT telemetry
> region. This counter reports the number of 10 µs intervals during
> which a Package C-state 10.2/3 entry was blocked for the specified
> reasons.
> 
> Signed-off-by: Xi Pardee <xi.pardee@linux.intel.com>
> ---
>  drivers/platform/x86/intel/pmc/core.c | 27 +++++++++++++++++++++++++++
>  drivers/platform/x86/intel/pmc/core.h |  8 ++++++++
>  2 files changed, 35 insertions(+)
> 
> diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c
> index bf95a1f2ba428..e5b48a68cf495 100644
> --- a/drivers/platform/x86/intel/pmc/core.c
> +++ b/drivers/platform/x86/intel/pmc/core.c
> @@ -1093,6 +1093,28 @@ static int pmc_core_pkgc_ltr_blocker_show(struct seq_file *s, void *unused)
>  }
>  DEFINE_SHOW_ATTRIBUTE(pmc_core_pkgc_ltr_blocker);
>  
> +static int pmc_core_pkgc_blocker_residency_show(struct seq_file *s, void *unused)
> +{
> +	struct pmc_dev *pmcdev = s->private;
> +	const char **pkgc_blocker_counters;
> +	u32 counter, offset;
> +	unsigned int i;
> +	int ret;
> +
> +	offset = pmcdev->pkgc_blocker_offset;
> +	pkgc_blocker_counters = pmcdev->pkgc_blocker_counters;
> +	for (i = 0; pkgc_blocker_counters[i]; i++, offset++) {
> +		ret = pmt_telem_read32(pmcdev->pc_ep, offset,
> +				       &counter, 1);
> +		if (ret)
> +			return ret;
> +		seq_printf(s, "%-30s %-30u\n", pkgc_blocker_counters[i], counter);
> +	}
> +
> +	return 0;

I wonder if it would be create a common helper as this looks practically 
the same as pmc_core_pkgc_ltr_blocker_show() added in the previous patch?

> +}
> +DEFINE_SHOW_ATTRIBUTE(pmc_core_pkgc_blocker_residency);
> +
>  static int pmc_core_lpm_latch_mode_show(struct seq_file *s, void *unused)
>  {
>  	struct pmc_dev *pmcdev = s->private;
> @@ -1380,6 +1402,8 @@ void pmc_core_punit_pmt_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_de
>  		pmcdev->pc_ep = ep;
>  		pmcdev->pkgc_ltr_blocker_counters = pmc_dev_info->pkgc_ltr_blocker_counters;
>  		pmcdev->pkgc_ltr_blocker_offset = pmc_dev_info->pkgc_ltr_blocker_offset;
> +		pmcdev->pkgc_blocker_counters = pmc_dev_info->pkgc_blocker_counters;
> +		pmcdev->pkgc_blocker_offset = pmc_dev_info->pkgc_blocker_offset;
>  	}
>  
>  release_dev:
> @@ -1512,6 +1536,9 @@ static void pmc_core_dbgfs_register(struct pmc_dev *pmcdev, struct pmc_dev_info
>  		debugfs_create_file("pkgc_ltr_blocker_show", 0444,
>  				    pmcdev->dbgfs_dir, pmcdev,
>  				    &pmc_core_pkgc_ltr_blocker_fops);
> +		debugfs_create_file("pkgc_blocker_residency_show", 0444,
> +				    pmcdev->dbgfs_dir, pmcdev,
> +				    &pmc_core_pkgc_blocker_residency_fops);
>  	}
>  
>  }
> diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h
> index a20aab73c1409..829b1dee3f636 100644
> --- a/drivers/platform/x86/intel/pmc/core.h
> +++ b/drivers/platform/x86/intel/pmc/core.h
> @@ -455,6 +455,8 @@ struct pmc {
>   *
>   * @pkgc_ltr_blocker_counters: Array of PKGC LTR blocker counters
>   * @pkgc_ltr_blocker_offset: Offset to PKGC LTR blockers in telemetry region
> + * @pkgc_blocker_counters: Array of PKGC blocker counters
> + * @pkgc_blocker_offset: Offset to PKGC blocker in telemetry region
>   *
>   * pmc_dev contains info about power management controller device.
>   */
> @@ -480,6 +482,8 @@ struct pmc_dev {
>  
>  	const char **pkgc_ltr_blocker_counters;
>  	u32 pkgc_ltr_blocker_offset;
> +	const char **pkgc_blocker_counters;
> +	u32 pkgc_blocker_offset;
>  };
>  
>  enum pmc_index {
> @@ -495,6 +499,7 @@ enum pmc_index {
>   * @dmu_guids:		List of Die Management Unit GUID
>   * @pc_guid:		GUID for telemetry region to read PKGC blocker info
>   * @pkgc_ltr_blocker_offset: Offset to PKGC LTR blockers in telemetry region
> + * @pkgc_blocker_offset:Offset to PKGC blocker in telemetry region
>   * @regmap_list:	Pointer to a list of pmc_info structure that could be
>   *			available for the platform. When set, this field implies
>   *			SSRAM support.
> @@ -502,6 +507,7 @@ enum pmc_index {
>   *			specific attributes of the primary PMC
>   * @sub_req_show:	File operations to show substate requirements
>   * @pkgc_ltr_blocker_counters: Array of PKGC LTR blocker counters
> + * @pkgc_blocker_counters: Array of PKGC blocker counters
>   * @suspend:		Function to perform platform specific suspend
>   * @resume:		Function to perform platform specific resume
>   * @init:		Function to perform platform specific init action
> @@ -512,10 +518,12 @@ struct pmc_dev_info {
>  	u32 *dmu_guids;
>  	u32 pc_guid;
>  	u32 pkgc_ltr_blocker_offset;
> +	u32 pkgc_blocker_offset;
>  	struct pmc_info *regmap_list;
>  	const struct pmc_reg_map *map;
>  	const struct file_operations *sub_req_show;
>  	const char **pkgc_ltr_blocker_counters;
> +	const char **pkgc_blocker_counters;
>  	void (*suspend)(struct pmc_dev *pmcdev);
>  	int (*resume)(struct pmc_dev *pmcdev);
>  	int (*init)(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info);
> 

-- 
 i.

[PATCH 3/6] platform/x86/intel/pmc: Use PCI DID for PMC SSRAM device discovery

[Xi Pardee]

Update the PMC SSRAM discovery process to identify the device using its
PCI Device ID rather than relying on a fixed PCI bus location. The
enumeration of integrated devices on the PCI bus is no longer guaranteed
to be consistent across CPUs.

On earlier platforms, the IOE and PCH SSRAM devices were hidden from the
BIOS, and the SOC SSRAM device is associated to telemetry regions from all
available SSRAM devices. Starting with Nova Lake, the IOE and PCH SSRAM
devices register their telemetry regions independently, meaning each
telemetry region is now linked to its corresponding SSRAM device. A new
ssram_hidden attribute has been added to the pmc_dev_info structure to
reflect this distinction.

Signed-off-by: David E. Box <david.e.box@linux.intel.com>
Signed-off-by: Xi Pardee <xi.pardee@linux.intel.com>
---
 drivers/platform/x86/intel/pmc/arl.c  |  4 ++--
 drivers/platform/x86/intel/pmc/core.c | 16 ++++++++++++----
 drivers/platform/x86/intel/pmc/core.h |  6 ++++--
 drivers/platform/x86/intel/pmc/lnl.c  |  2 +-
 drivers/platform/x86/intel/pmc/mtl.c  |  2 +-
 drivers/platform/x86/intel/pmc/ptl.c  |  2 +-
 drivers/platform/x86/intel/pmc/wcl.c  |  2 +-
 7 files changed, 22 insertions(+), 12 deletions(-)

diff --git a/drivers/platform/x86/intel/pmc/arl.c b/drivers/platform/x86/intel/pmc/arl.c
index eb23bc68340ab..95372a0807acf 100644
--- a/drivers/platform/x86/intel/pmc/arl.c
+++ b/drivers/platform/x86/intel/pmc/arl.c
@@ -720,7 +720,6 @@ static int arl_h_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_
 
 static u32 ARL_PMT_DMU_GUIDS[] = {ARL_PMT_DMU_GUID, 0x0};
 struct pmc_dev_info arl_pmc_dev = {
-	.pci_func = 0,
 	.dmu_guids = ARL_PMT_DMU_GUIDS,
 	.regmap_list = arl_pmc_info_list,
 	.map = &arl_socs_reg_map,
@@ -729,11 +728,11 @@ struct pmc_dev_info arl_pmc_dev = {
 	.resume = arl_resume,
 	.init = arl_core_init,
 	.sub_req = pmc_core_pmt_get_lpm_req,
+	.ssram_hidden = true,
 };
 
 static u32 ARL_H_PMT_DMU_GUIDS[] = {ARL_PMT_DMU_GUID, ARL_H_PMT_DMU_GUID, 0x0};
 struct pmc_dev_info arl_h_pmc_dev = {
-	.pci_func = 2,
 	.dmu_guids = ARL_H_PMT_DMU_GUIDS,
 	.regmap_list = arl_pmc_info_list,
 	.map = &mtl_socm_reg_map,
@@ -742,4 +741,5 @@ struct pmc_dev_info arl_h_pmc_dev = {
 	.resume = arl_h_resume,
 	.init = arl_h_core_init,
 	.sub_req = pmc_core_pmt_get_lpm_req,
+	.ssram_hidden = true,
 };
diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c
index e5b48a68cf495..7670970c995b9 100644
--- a/drivers/platform/x86/intel/pmc/core.c
+++ b/drivers/platform/x86/intel/pmc/core.c
@@ -1660,12 +1660,10 @@ static int pmc_core_get_telem_info(struct pmc_dev *pmcdev, struct pmc_dev_info *
 	unsigned int pmc_idx;
 	int ret;
 
-	pcidev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(20, pmc_dev_info->pci_func));
-	if (!pcidev)
-		return -ENODEV;
-
 	for (pmc_idx = 0; pmc_idx < ARRAY_SIZE(pmcdev->pmcs); ++pmc_idx) {
+		struct pci_dev *pcidev __free(pci_dev_put) = NULL;
 		struct pmc *pmc;
+		u16 devid;
 
 		pmc = pmcdev->pmcs[pmc_idx];
 		if (!pmc)
@@ -1674,6 +1672,15 @@ static int pmc_core_get_telem_info(struct pmc_dev *pmcdev, struct pmc_dev_info *
 		if (!pmc->map->lpm_req_guid)
 			return -ENXIO;
 
+		if (pmc_dev_info->ssram_hidden)
+			devid = pmcdev->pmcs[PMC_IDX_MAIN]->devid;
+		else
+			devid = pmc->devid;
+
+		pcidev = pci_get_device(PCI_VENDOR_ID_INTEL, devid, NULL);
+		if (!pcidev)
+			return -ENODEV;
+
 		ep = pmt_telem_find_and_register_endpoint(pcidev, pmc->map->lpm_req_guid, 0);
 		if (IS_ERR(ep)) {
 			dev_dbg(&pmcdev->pdev->dev, "couldn't get telem endpoint %pe", ep);
@@ -1724,6 +1731,7 @@ static int pmc_core_pmc_add(struct pmc_dev *pmcdev, unsigned int pmc_idx)
 
 	pmc->map = map;
 	pmc->base_addr = pmc_ssram_telemetry.base_addr;
+	pmc->devid = pmc_ssram_telemetry.devid;
 	pmc->regbase = ioremap(pmc->base_addr, pmc->map->regmap_length);
 
 	if (!pmc->regbase) {
diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h
index 829b1dee3f636..31fe71b01120b 100644
--- a/drivers/platform/x86/intel/pmc/core.h
+++ b/drivers/platform/x86/intel/pmc/core.h
@@ -425,6 +425,7 @@ struct pmc_info {
  * @ltr_ign:		Holds LTR ignore data while suspended
  * @num_lpm_modes:	Count of enabled modes
  * @lpm_en_modes:	Array of enabled modes from lowest to highest priority
+ * @devid:		Device ID of the SSRAM device
  *
  * pmc contains info about one power management controller device.
  */
@@ -436,6 +437,7 @@ struct pmc {
 	u32 ltr_ign;
 	u8 num_lpm_modes;
 	u8 lpm_en_modes[LPM_MAX_NUM_MODES];
+	u16 devid;
 };
 
 /**
@@ -495,7 +497,6 @@ enum pmc_index {
 
 /**
  * struct pmc_dev_info - Structure to keep PMC device info
- * @pci_func:		Function number of the primary PMC
  * @dmu_guids:		List of Die Management Unit GUID
  * @pc_guid:		GUID for telemetry region to read PKGC blocker info
  * @pkgc_ltr_blocker_offset: Offset to PKGC LTR blockers in telemetry region
@@ -512,9 +513,9 @@ enum pmc_index {
  * @resume:		Function to perform platform specific resume
  * @init:		Function to perform platform specific init action
  * @sub_req:		Function to achieve low power mode substate requirements
+ * @ssram_hidden:	Flag to indicate whether SSRAM is hidden
  */
 struct pmc_dev_info {
-	u8 pci_func;
 	u32 *dmu_guids;
 	u32 pc_guid;
 	u32 pkgc_ltr_blocker_offset;
@@ -528,6 +529,7 @@ struct pmc_dev_info {
 	int (*resume)(struct pmc_dev *pmcdev);
 	int (*init)(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info);
 	int (*sub_req)(struct pmc_dev *pmcdev, struct pmc *pmc, struct telem_endpoint *ep);
+	bool ssram_hidden;
 };
 
 extern const struct pmc_bit_map msr_map[];
diff --git a/drivers/platform/x86/intel/pmc/lnl.c b/drivers/platform/x86/intel/pmc/lnl.c
index 1cd81ee54dcf8..18f303af328e3 100644
--- a/drivers/platform/x86/intel/pmc/lnl.c
+++ b/drivers/platform/x86/intel/pmc/lnl.c
@@ -571,7 +571,6 @@ static int lnl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_in
 }
 
 struct pmc_dev_info lnl_pmc_dev = {
-	.pci_func = 2,
 	.regmap_list = lnl_pmc_info_list,
 	.map = &lnl_socm_reg_map,
 	.sub_req_show = &pmc_core_substate_req_regs_fops,
@@ -579,4 +578,5 @@ struct pmc_dev_info lnl_pmc_dev = {
 	.resume = lnl_resume,
 	.init = lnl_core_init,
 	.sub_req = pmc_core_pmt_get_lpm_req,
+	.ssram_hidden = true,
 };
diff --git a/drivers/platform/x86/intel/pmc/mtl.c b/drivers/platform/x86/intel/pmc/mtl.c
index 57508cbf9cd42..193ebbe584023 100644
--- a/drivers/platform/x86/intel/pmc/mtl.c
+++ b/drivers/platform/x86/intel/pmc/mtl.c
@@ -994,7 +994,6 @@ static int mtl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_in
 
 static u32 MTL_PMT_DMU_GUIDS[] = {MTL_PMT_DMU_GUID, 0x0};
 struct pmc_dev_info mtl_pmc_dev = {
-	.pci_func = 2,
 	.dmu_guids = MTL_PMT_DMU_GUIDS,
 	.regmap_list = mtl_pmc_info_list,
 	.map = &mtl_socm_reg_map,
@@ -1003,4 +1002,5 @@ struct pmc_dev_info mtl_pmc_dev = {
 	.resume = mtl_resume,
 	.init = mtl_core_init,
 	.sub_req = pmc_core_pmt_get_lpm_req,
+	.ssram_hidden = true,
 };
diff --git a/drivers/platform/x86/intel/pmc/ptl.c b/drivers/platform/x86/intel/pmc/ptl.c
index 1f48e2bbc699f..6c68772e738c8 100644
--- a/drivers/platform/x86/intel/pmc/ptl.c
+++ b/drivers/platform/x86/intel/pmc/ptl.c
@@ -569,7 +569,6 @@ static int ptl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_in
 }
 
 struct pmc_dev_info ptl_pmc_dev = {
-	.pci_func = 2,
 	.regmap_list = ptl_pmc_info_list,
 	.map = &ptl_pcdp_reg_map,
 	.sub_req_show = &pmc_core_substate_blk_req_fops,
@@ -577,4 +576,5 @@ struct pmc_dev_info ptl_pmc_dev = {
 	.resume = ptl_resume,
 	.init = ptl_core_init,
 	.sub_req = pmc_core_pmt_get_blk_sub_req,
+	.ssram_hidden = true,
 };
diff --git a/drivers/platform/x86/intel/pmc/wcl.c b/drivers/platform/x86/intel/pmc/wcl.c
index a45707e6364f2..b55069945e9e7 100644
--- a/drivers/platform/x86/intel/pmc/wcl.c
+++ b/drivers/platform/x86/intel/pmc/wcl.c
@@ -493,7 +493,6 @@ static int wcl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_in
 }
 
 struct pmc_dev_info wcl_pmc_dev = {
-	.pci_func = 2,
 	.regmap_list = wcl_pmc_info_list,
 	.map = &wcl_pcdn_reg_map,
 	.sub_req_show = &pmc_core_substate_blk_req_fops,
@@ -501,4 +500,5 @@ struct pmc_dev_info wcl_pmc_dev = {
 	.resume = wcl_resume,
 	.init = wcl_core_init,
 	.sub_req = pmc_core_pmt_get_blk_sub_req,
+	.ssram_hidden = true,
 };
-- 
2.43.0

Re: [PATCH 3/6] platform/x86/intel/pmc: Use PCI DID for PMC SSRAM device discovery

[Ilpo Järvinen]

On Mon, 2 Mar 2026, Xi Pardee wrote:

> Update the PMC SSRAM discovery process to identify the device using its
> PCI Device ID rather than relying on a fixed PCI bus location. The
> enumeration of integrated devices on the PCI bus is no longer guaranteed
> to be consistent across CPUs.
> 
> On earlier platforms, the IOE and PCH SSRAM devices were hidden from the
> BIOS, and the SOC SSRAM device is associated to telemetry regions from all
> available SSRAM devices. Starting with Nova Lake, the IOE and PCH SSRAM
> devices register their telemetry regions independently, meaning each
> telemetry region is now linked to its corresponding SSRAM device. A new
> ssram_hidden attribute has been added to the pmc_dev_info structure to
> reflect this distinction.
>
> Signed-off-by: David E. Box <david.e.box@linux.intel.com>
> Signed-off-by: Xi Pardee <xi.pardee@linux.intel.com>
> ---
>  drivers/platform/x86/intel/pmc/arl.c  |  4 ++--
>  drivers/platform/x86/intel/pmc/core.c | 16 ++++++++++++----
>  drivers/platform/x86/intel/pmc/core.h |  6 ++++--
>  drivers/platform/x86/intel/pmc/lnl.c  |  2 +-
>  drivers/platform/x86/intel/pmc/mtl.c  |  2 +-
>  drivers/platform/x86/intel/pmc/ptl.c  |  2 +-
>  drivers/platform/x86/intel/pmc/wcl.c  |  2 +-
>  7 files changed, 22 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/platform/x86/intel/pmc/arl.c b/drivers/platform/x86/intel/pmc/arl.c
> index eb23bc68340ab..95372a0807acf 100644
> --- a/drivers/platform/x86/intel/pmc/arl.c
> +++ b/drivers/platform/x86/intel/pmc/arl.c
> @@ -720,7 +720,6 @@ static int arl_h_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_
>  
>  static u32 ARL_PMT_DMU_GUIDS[] = {ARL_PMT_DMU_GUID, 0x0};
>  struct pmc_dev_info arl_pmc_dev = {
> -	.pci_func = 0,
>  	.dmu_guids = ARL_PMT_DMU_GUIDS,
>  	.regmap_list = arl_pmc_info_list,
>  	.map = &arl_socs_reg_map,
> @@ -729,11 +728,11 @@ struct pmc_dev_info arl_pmc_dev = {
>  	.resume = arl_resume,
>  	.init = arl_core_init,
>  	.sub_req = pmc_core_pmt_get_lpm_req,
> +	.ssram_hidden = true,
>  };
>  
>  static u32 ARL_H_PMT_DMU_GUIDS[] = {ARL_PMT_DMU_GUID, ARL_H_PMT_DMU_GUID, 0x0};
>  struct pmc_dev_info arl_h_pmc_dev = {
> -	.pci_func = 2,
>  	.dmu_guids = ARL_H_PMT_DMU_GUIDS,
>  	.regmap_list = arl_pmc_info_list,
>  	.map = &mtl_socm_reg_map,
> @@ -742,4 +741,5 @@ struct pmc_dev_info arl_h_pmc_dev = {
>  	.resume = arl_h_resume,
>  	.init = arl_h_core_init,
>  	.sub_req = pmc_core_pmt_get_lpm_req,
> +	.ssram_hidden = true,
>  };
> diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c
> index e5b48a68cf495..7670970c995b9 100644
> --- a/drivers/platform/x86/intel/pmc/core.c
> +++ b/drivers/platform/x86/intel/pmc/core.c
> @@ -1660,12 +1660,10 @@ static int pmc_core_get_telem_info(struct pmc_dev *pmcdev, struct pmc_dev_info *
>  	unsigned int pmc_idx;
>  	int ret;
>  
> -	pcidev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(20, pmc_dev_info->pci_func));
> -	if (!pcidev)
> -		return -ENODEV;
> -
>  	for (pmc_idx = 0; pmc_idx < ARRAY_SIZE(pmcdev->pmcs); ++pmc_idx) {
> +		struct pci_dev *pcidev __free(pci_dev_put) = NULL;

Please don't use = NULL; pattern with __free() because it's dangerous in 
some cases, please see the long comment in cleanup.h for details why.

Place the declaration where you do the assignment.

>  		struct pmc *pmc;
> +		u16 devid;
>  
>  		pmc = pmcdev->pmcs[pmc_idx];
>  		if (!pmc)
> @@ -1674,6 +1672,15 @@ static int pmc_core_get_telem_info(struct pmc_dev *pmcdev, struct pmc_dev_info *
>  		if (!pmc->map->lpm_req_guid)
>  			return -ENXIO;
>  
> +		if (pmc_dev_info->ssram_hidden)
> +			devid = pmcdev->pmcs[PMC_IDX_MAIN]->devid;
> +		else
> +			devid = pmc->devid;
> +
> +		pcidev = pci_get_device(PCI_VENDOR_ID_INTEL, devid, NULL);
> +		if (!pcidev)
> +			return -ENODEV;
> +
>  		ep = pmt_telem_find_and_register_endpoint(pcidev, pmc->map->lpm_req_guid, 0);
>  		if (IS_ERR(ep)) {
>  			dev_dbg(&pmcdev->pdev->dev, "couldn't get telem endpoint %pe", ep);
> @@ -1724,6 +1731,7 @@ static int pmc_core_pmc_add(struct pmc_dev *pmcdev, unsigned int pmc_idx)
>  
>  	pmc->map = map;
>  	pmc->base_addr = pmc_ssram_telemetry.base_addr;
> +	pmc->devid = pmc_ssram_telemetry.devid;
>  	pmc->regbase = ioremap(pmc->base_addr, pmc->map->regmap_length);
>  
>  	if (!pmc->regbase) {
> diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h
> index 829b1dee3f636..31fe71b01120b 100644
> --- a/drivers/platform/x86/intel/pmc/core.h
> +++ b/drivers/platform/x86/intel/pmc/core.h
> @@ -425,6 +425,7 @@ struct pmc_info {
>   * @ltr_ign:		Holds LTR ignore data while suspended
>   * @num_lpm_modes:	Count of enabled modes
>   * @lpm_en_modes:	Array of enabled modes from lowest to highest priority
> + * @devid:		Device ID of the SSRAM device
>   *
>   * pmc contains info about one power management controller device.
>   */
> @@ -436,6 +437,7 @@ struct pmc {
>  	u32 ltr_ign;
>  	u8 num_lpm_modes;
>  	u8 lpm_en_modes[LPM_MAX_NUM_MODES];
> +	u16 devid;
>  };
>  
>  /**
> @@ -495,7 +497,6 @@ enum pmc_index {
>  
>  /**
>   * struct pmc_dev_info - Structure to keep PMC device info
> - * @pci_func:		Function number of the primary PMC
>   * @dmu_guids:		List of Die Management Unit GUID
>   * @pc_guid:		GUID for telemetry region to read PKGC blocker info
>   * @pkgc_ltr_blocker_offset: Offset to PKGC LTR blockers in telemetry region
> @@ -512,9 +513,9 @@ enum pmc_index {
>   * @resume:		Function to perform platform specific resume
>   * @init:		Function to perform platform specific init action
>   * @sub_req:		Function to achieve low power mode substate requirements
> + * @ssram_hidden:	Flag to indicate whether SSRAM is hidden

I'd elaborate this as some of the SSRAM devices are hidden in this case.

IMO, the "Flag to indicate whether" is pretty pointless, the C type 
information pretty much indicates it's a flag.

>   */
>  struct pmc_dev_info {
> -	u8 pci_func;
>  	u32 *dmu_guids;
>  	u32 pc_guid;
>  	u32 pkgc_ltr_blocker_offset;
> @@ -528,6 +529,7 @@ struct pmc_dev_info {
>  	int (*resume)(struct pmc_dev *pmcdev);
>  	int (*init)(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info);
>  	int (*sub_req)(struct pmc_dev *pmcdev, struct pmc *pmc, struct telem_endpoint *ep);
> +	bool ssram_hidden;
>  };
>  
>  extern const struct pmc_bit_map msr_map[];
> diff --git a/drivers/platform/x86/intel/pmc/lnl.c b/drivers/platform/x86/intel/pmc/lnl.c
> index 1cd81ee54dcf8..18f303af328e3 100644
> --- a/drivers/platform/x86/intel/pmc/lnl.c
> +++ b/drivers/platform/x86/intel/pmc/lnl.c
> @@ -571,7 +571,6 @@ static int lnl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_in
>  }
>  
>  struct pmc_dev_info lnl_pmc_dev = {
> -	.pci_func = 2,
>  	.regmap_list = lnl_pmc_info_list,
>  	.map = &lnl_socm_reg_map,
>  	.sub_req_show = &pmc_core_substate_req_regs_fops,
> @@ -579,4 +578,5 @@ struct pmc_dev_info lnl_pmc_dev = {
>  	.resume = lnl_resume,
>  	.init = lnl_core_init,
>  	.sub_req = pmc_core_pmt_get_lpm_req,
> +	.ssram_hidden = true,
>  };
> diff --git a/drivers/platform/x86/intel/pmc/mtl.c b/drivers/platform/x86/intel/pmc/mtl.c
> index 57508cbf9cd42..193ebbe584023 100644
> --- a/drivers/platform/x86/intel/pmc/mtl.c
> +++ b/drivers/platform/x86/intel/pmc/mtl.c
> @@ -994,7 +994,6 @@ static int mtl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_in
>  
>  static u32 MTL_PMT_DMU_GUIDS[] = {MTL_PMT_DMU_GUID, 0x0};
>  struct pmc_dev_info mtl_pmc_dev = {
> -	.pci_func = 2,
>  	.dmu_guids = MTL_PMT_DMU_GUIDS,
>  	.regmap_list = mtl_pmc_info_list,
>  	.map = &mtl_socm_reg_map,
> @@ -1003,4 +1002,5 @@ struct pmc_dev_info mtl_pmc_dev = {
>  	.resume = mtl_resume,
>  	.init = mtl_core_init,
>  	.sub_req = pmc_core_pmt_get_lpm_req,
> +	.ssram_hidden = true,
>  };
> diff --git a/drivers/platform/x86/intel/pmc/ptl.c b/drivers/platform/x86/intel/pmc/ptl.c
> index 1f48e2bbc699f..6c68772e738c8 100644
> --- a/drivers/platform/x86/intel/pmc/ptl.c
> +++ b/drivers/platform/x86/intel/pmc/ptl.c
> @@ -569,7 +569,6 @@ static int ptl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_in
>  }
>  
>  struct pmc_dev_info ptl_pmc_dev = {
> -	.pci_func = 2,
>  	.regmap_list = ptl_pmc_info_list,
>  	.map = &ptl_pcdp_reg_map,
>  	.sub_req_show = &pmc_core_substate_blk_req_fops,
> @@ -577,4 +576,5 @@ struct pmc_dev_info ptl_pmc_dev = {
>  	.resume = ptl_resume,
>  	.init = ptl_core_init,
>  	.sub_req = pmc_core_pmt_get_blk_sub_req,
> +	.ssram_hidden = true,
>  };
> diff --git a/drivers/platform/x86/intel/pmc/wcl.c b/drivers/platform/x86/intel/pmc/wcl.c
> index a45707e6364f2..b55069945e9e7 100644
> --- a/drivers/platform/x86/intel/pmc/wcl.c
> +++ b/drivers/platform/x86/intel/pmc/wcl.c
> @@ -493,7 +493,6 @@ static int wcl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_in
>  }
>  
>  struct pmc_dev_info wcl_pmc_dev = {
> -	.pci_func = 2,
>  	.regmap_list = wcl_pmc_info_list,
>  	.map = &wcl_pcdn_reg_map,
>  	.sub_req_show = &pmc_core_substate_blk_req_fops,
> @@ -501,4 +500,5 @@ struct pmc_dev_info wcl_pmc_dev = {
>  	.resume = wcl_resume,
>  	.init = wcl_core_init,
>  	.sub_req = pmc_core_pmt_get_blk_sub_req,
> +	.ssram_hidden = true,
>  };
> 

-- 
 i.

[PATCH 4/6] platform/x86/intel/pmc: Add support for variable DMU offsets

[Xi Pardee]

Add support for handling different DMU Die C6 offsets across platforms.
The previous implementation assumed a uniform DMU Die C6 offset for all
platforms, which is no longer valid.

Signed-off-by: Xi Pardee <xi.pardee@linux.intel.com>
---
 drivers/platform/x86/intel/pmc/arl.c  | 2 ++
 drivers/platform/x86/intel/pmc/core.c | 2 +-
 drivers/platform/x86/intel/pmc/core.h | 2 ++
 drivers/platform/x86/intel/pmc/mtl.c  | 1 +
 4 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/platform/x86/intel/pmc/arl.c b/drivers/platform/x86/intel/pmc/arl.c
index 95372a0807acf..4d91ee010f6d0 100644
--- a/drivers/platform/x86/intel/pmc/arl.c
+++ b/drivers/platform/x86/intel/pmc/arl.c
@@ -729,6 +729,7 @@ struct pmc_dev_info arl_pmc_dev = {
 	.init = arl_core_init,
 	.sub_req = pmc_core_pmt_get_lpm_req,
 	.ssram_hidden = true,
+	.die_c6_offset = MTL_PMT_DMU_DIE_C6_OFFSET,
 };
 
 static u32 ARL_H_PMT_DMU_GUIDS[] = {ARL_PMT_DMU_GUID, ARL_H_PMT_DMU_GUID, 0x0};
@@ -742,4 +743,5 @@ struct pmc_dev_info arl_h_pmc_dev = {
 	.init = arl_h_core_init,
 	.sub_req = pmc_core_pmt_get_lpm_req,
 	.ssram_hidden = true,
+	.die_c6_offset = MTL_PMT_DMU_DIE_C6_OFFSET,
 };
diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c
index 7670970c995b9..7bd0e1eaa32e2 100644
--- a/drivers/platform/x86/intel/pmc/core.c
+++ b/drivers/platform/x86/intel/pmc/core.c
@@ -1387,7 +1387,7 @@ void pmc_core_punit_pmt_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_de
 		}
 
 		pmcdev->punit_ep = ep;
-		pmcdev->die_c6_offset = MTL_PMT_DMU_DIE_C6_OFFSET;
+		pmcdev->die_c6_offset = pmc_dev_info->die_c6_offset;
 	}
 
 	if (pmc_dev_info->pc_guid) {
diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h
index 31fe71b01120b..f09791f866223 100644
--- a/drivers/platform/x86/intel/pmc/core.h
+++ b/drivers/platform/x86/intel/pmc/core.h
@@ -514,6 +514,7 @@ enum pmc_index {
  * @init:		Function to perform platform specific init action
  * @sub_req:		Function to achieve low power mode substate requirements
  * @ssram_hidden:	Flag to indicate whether SSRAM is hidden
+ * @die_c6_offseyt:	Telemetry offset to read Die C6 residency
  */
 struct pmc_dev_info {
 	u32 *dmu_guids;
@@ -530,6 +531,7 @@ struct pmc_dev_info {
 	int (*init)(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info);
 	int (*sub_req)(struct pmc_dev *pmcdev, struct pmc *pmc, struct telem_endpoint *ep);
 	bool ssram_hidden;
+	u32 die_c6_offset;
 };
 
 extern const struct pmc_bit_map msr_map[];
diff --git a/drivers/platform/x86/intel/pmc/mtl.c b/drivers/platform/x86/intel/pmc/mtl.c
index 193ebbe584023..b724dd8c34dba 100644
--- a/drivers/platform/x86/intel/pmc/mtl.c
+++ b/drivers/platform/x86/intel/pmc/mtl.c
@@ -1003,4 +1003,5 @@ struct pmc_dev_info mtl_pmc_dev = {
 	.init = mtl_core_init,
 	.sub_req = pmc_core_pmt_get_lpm_req,
 	.ssram_hidden = true,
+	.die_c6_offset = MTL_PMT_DMU_DIE_C6_OFFSET,
 };
-- 
2.43.0

Re: [PATCH 4/6] platform/x86/intel/pmc: Add support for variable DMU offsets

[Ilpo Järvinen]

On Mon, 2 Mar 2026, Xi Pardee wrote:

> Add support for handling different DMU Die C6 offsets across platforms.
> The previous implementation assumed a uniform DMU Die C6 offset for all
> platforms, which is no longer valid.
> 
> Signed-off-by: Xi Pardee <xi.pardee@linux.intel.com>
> ---
>  drivers/platform/x86/intel/pmc/arl.c  | 2 ++
>  drivers/platform/x86/intel/pmc/core.c | 2 +-
>  drivers/platform/x86/intel/pmc/core.h | 2 ++
>  drivers/platform/x86/intel/pmc/mtl.c  | 1 +
>  4 files changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/platform/x86/intel/pmc/arl.c b/drivers/platform/x86/intel/pmc/arl.c
> index 95372a0807acf..4d91ee010f6d0 100644
> --- a/drivers/platform/x86/intel/pmc/arl.c
> +++ b/drivers/platform/x86/intel/pmc/arl.c
> @@ -729,6 +729,7 @@ struct pmc_dev_info arl_pmc_dev = {
>  	.init = arl_core_init,
>  	.sub_req = pmc_core_pmt_get_lpm_req,
>  	.ssram_hidden = true,
> +	.die_c6_offset = MTL_PMT_DMU_DIE_C6_OFFSET,
>  };
>  
>  static u32 ARL_H_PMT_DMU_GUIDS[] = {ARL_PMT_DMU_GUID, ARL_H_PMT_DMU_GUID, 0x0};
> @@ -742,4 +743,5 @@ struct pmc_dev_info arl_h_pmc_dev = {
>  	.init = arl_h_core_init,
>  	.sub_req = pmc_core_pmt_get_lpm_req,
>  	.ssram_hidden = true,
> +	.die_c6_offset = MTL_PMT_DMU_DIE_C6_OFFSET,
>  };
> diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c
> index 7670970c995b9..7bd0e1eaa32e2 100644
> --- a/drivers/platform/x86/intel/pmc/core.c
> +++ b/drivers/platform/x86/intel/pmc/core.c
> @@ -1387,7 +1387,7 @@ void pmc_core_punit_pmt_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_de
>  		}
>  
>  		pmcdev->punit_ep = ep;
> -		pmcdev->die_c6_offset = MTL_PMT_DMU_DIE_C6_OFFSET;
> +		pmcdev->die_c6_offset = pmc_dev_info->die_c6_offset;
>  	}
>  
>  	if (pmc_dev_info->pc_guid) {
> diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h
> index 31fe71b01120b..f09791f866223 100644
> --- a/drivers/platform/x86/intel/pmc/core.h
> +++ b/drivers/platform/x86/intel/pmc/core.h
> @@ -514,6 +514,7 @@ enum pmc_index {
>   * @init:		Function to perform platform specific init action
>   * @sub_req:		Function to achieve low power mode substate requirements
>   * @ssram_hidden:	Flag to indicate whether SSRAM is hidden
> + * @die_c6_offseyt:	Telemetry offset to read Die C6 residency

Typo (-t)

>   */
>  struct pmc_dev_info {
>  	u32 *dmu_guids;
> @@ -530,6 +531,7 @@ struct pmc_dev_info {
>  	int (*init)(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info);
>  	int (*sub_req)(struct pmc_dev *pmcdev, struct pmc *pmc, struct telem_endpoint *ep);
>  	bool ssram_hidden;
> +	u32 die_c6_offset;
>  };
>  
>  extern const struct pmc_bit_map msr_map[];
> diff --git a/drivers/platform/x86/intel/pmc/mtl.c b/drivers/platform/x86/intel/pmc/mtl.c
> index 193ebbe584023..b724dd8c34dba 100644
> --- a/drivers/platform/x86/intel/pmc/mtl.c
> +++ b/drivers/platform/x86/intel/pmc/mtl.c
> @@ -1003,4 +1003,5 @@ struct pmc_dev_info mtl_pmc_dev = {
>  	.init = mtl_core_init,
>  	.sub_req = pmc_core_pmt_get_lpm_req,
>  	.ssram_hidden = true,
> +	.die_c6_offset = MTL_PMT_DMU_DIE_C6_OFFSET,
>  };
> 

-- 
 i.

[PATCH 5/6] platform/x86/intel/pmc: Retrieve PMC info only for available PMCs

[Xi Pardee]

Update the Intel PMC Core driver to fetch PMC information only for
available PMCs. Previously, the driver attempted to retrieve PMC info
even when the corresponding PMC was not present.

This change aligns with recent updates to the Intel SSRAM Telemetry
driver. Starting with NVL, the SSRAM Telemetry driver is probed for
each individual SSRAM device. The prior implementation could not
differentiate between an unavailable PMC and one that had not yet
completed information retrieval. To resolve this, the PMC Core driver
now skips obtaining PMC info for unavailable PMCs.

Signed-off-by: Xi Pardee <xi.pardee@linux.intel.com>
---
 drivers/platform/x86/intel/pmc/arl.c  |  5 +++++
 drivers/platform/x86/intel/pmc/core.c | 19 +++++++++++--------
 drivers/platform/x86/intel/pmc/core.h |  2 ++
 drivers/platform/x86/intel/pmc/lnl.c  |  3 +++
 drivers/platform/x86/intel/pmc/mtl.c  |  3 +++
 drivers/platform/x86/intel/pmc/ptl.c  |  3 +++
 drivers/platform/x86/intel/pmc/wcl.c  |  3 +++
 7 files changed, 30 insertions(+), 8 deletions(-)

diff --git a/drivers/platform/x86/intel/pmc/arl.c b/drivers/platform/x86/intel/pmc/arl.c
index 4d91ee010f6d0..34506542c94da 100644
--- a/drivers/platform/x86/intel/pmc/arl.c
+++ b/drivers/platform/x86/intel/pmc/arl.c
@@ -672,6 +672,9 @@ static struct pmc_info arl_pmc_info_list[] = {
 	{}
 };
 
+static u8 arl_pmc_list[] = {PMC_IDX_MAIN, PMC_IDX_IOE, PMC_IDX_PCH, PMC_IDX_MAX};
+static u8 arl_h_pmc_list[] = {PMC_IDX_MAIN, PMC_IDX_IOE, PMC_IDX_MAX};
+
 #define ARL_NPU_PCI_DEV			0xad1d
 #define ARL_GNA_PCI_DEV			0xae4c
 #define ARL_H_NPU_PCI_DEV		0x7d1d
@@ -721,6 +724,7 @@ static int arl_h_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_
 static u32 ARL_PMT_DMU_GUIDS[] = {ARL_PMT_DMU_GUID, 0x0};
 struct pmc_dev_info arl_pmc_dev = {
 	.dmu_guids = ARL_PMT_DMU_GUIDS,
+	.pmc_list = arl_pmc_list,
 	.regmap_list = arl_pmc_info_list,
 	.map = &arl_socs_reg_map,
 	.sub_req_show = &pmc_core_substate_req_regs_fops,
@@ -735,6 +739,7 @@ struct pmc_dev_info arl_pmc_dev = {
 static u32 ARL_H_PMT_DMU_GUIDS[] = {ARL_PMT_DMU_GUID, ARL_H_PMT_DMU_GUID, 0x0};
 struct pmc_dev_info arl_h_pmc_dev = {
 	.dmu_guids = ARL_H_PMT_DMU_GUIDS,
+	.pmc_list = arl_h_pmc_list,
 	.regmap_list = arl_pmc_info_list,
 	.map = &mtl_socm_reg_map,
 	.sub_req_show = &pmc_core_substate_req_regs_fops,
diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c
index 7bd0e1eaa32e2..85fff5e3abe0d 100644
--- a/drivers/platform/x86/intel/pmc/core.c
+++ b/drivers/platform/x86/intel/pmc/core.c
@@ -1744,16 +1744,19 @@ static int pmc_core_pmc_add(struct pmc_dev *pmcdev, unsigned int pmc_idx)
 	return 0;
 }
 
-static int pmc_core_ssram_get_reg_base(struct pmc_dev *pmcdev)
+static int pmc_core_ssram_get_reg_base(struct pmc_dev *pmcdev, u8 *pmc_list)
 {
+	unsigned int i;
 	int ret;
 
-	ret = pmc_core_pmc_add(pmcdev, PMC_IDX_MAIN);
-	if (ret)
-		return ret;
-
-	pmc_core_pmc_add(pmcdev, PMC_IDX_IOE);
-	pmc_core_pmc_add(pmcdev, PMC_IDX_PCH);
+	for (i = 0; pmc_list[i] != PMC_IDX_MAX; ++i) {
+		if (pmc_list[i] == PMC_IDX_MAIN) {
+			ret = pmc_core_pmc_add(pmcdev, pmc_list[i]);
+			if (ret)
+				return ret;
+		} else
+			pmc_core_pmc_add(pmcdev, pmc_list[i]);
+	}
 
 	return 0;
 }
@@ -1775,7 +1778,7 @@ int generic_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info)
 	ssram = pmc_dev_info->regmap_list != NULL;
 	if (ssram) {
 		pmcdev->regmap_list = pmc_dev_info->regmap_list;
-		ret = pmc_core_ssram_get_reg_base(pmcdev);
+		ret = pmc_core_ssram_get_reg_base(pmcdev, pmc_dev_info->pmc_list);
 		/*
 		 * EAGAIN error code indicates Intel PMC SSRAM Telemetry driver
 		 * has not finished probe and PMC info is not available yet. Try
diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h
index f09791f866223..c4984e44f7b80 100644
--- a/drivers/platform/x86/intel/pmc/core.h
+++ b/drivers/platform/x86/intel/pmc/core.h
@@ -501,6 +501,7 @@ enum pmc_index {
  * @pc_guid:		GUID for telemetry region to read PKGC blocker info
  * @pkgc_ltr_blocker_offset: Offset to PKGC LTR blockers in telemetry region
  * @pkgc_blocker_offset:Offset to PKGC blocker in telemetry region
+ * @pmc_list:		Index list of available PMC
  * @regmap_list:	Pointer to a list of pmc_info structure that could be
  *			available for the platform. When set, this field implies
  *			SSRAM support.
@@ -521,6 +522,7 @@ struct pmc_dev_info {
 	u32 pc_guid;
 	u32 pkgc_ltr_blocker_offset;
 	u32 pkgc_blocker_offset;
+	u8 *pmc_list;
 	struct pmc_info *regmap_list;
 	const struct pmc_reg_map *map;
 	const struct file_operations *sub_req_show;
diff --git a/drivers/platform/x86/intel/pmc/lnl.c b/drivers/platform/x86/intel/pmc/lnl.c
index 18f303af328e3..7b09b59e1326c 100644
--- a/drivers/platform/x86/intel/pmc/lnl.c
+++ b/drivers/platform/x86/intel/pmc/lnl.c
@@ -544,6 +544,8 @@ static struct pmc_info lnl_pmc_info_list[] = {
 	{}
 };
 
+static u8 lnl_pmc_list[] = {PMC_IDX_MAIN, PMC_IDX_MAX};
+
 #define LNL_NPU_PCI_DEV		0x643e
 #define LNL_IPU_PCI_DEV		0x645d
 
@@ -571,6 +573,7 @@ static int lnl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_in
 }
 
 struct pmc_dev_info lnl_pmc_dev = {
+	.pmc_list = lnl_pmc_list,
 	.regmap_list = lnl_pmc_info_list,
 	.map = &lnl_socm_reg_map,
 	.sub_req_show = &pmc_core_substate_req_regs_fops,
diff --git a/drivers/platform/x86/intel/pmc/mtl.c b/drivers/platform/x86/intel/pmc/mtl.c
index b724dd8c34dba..6438fca266392 100644
--- a/drivers/platform/x86/intel/pmc/mtl.c
+++ b/drivers/platform/x86/intel/pmc/mtl.c
@@ -965,6 +965,8 @@ static struct pmc_info mtl_pmc_info_list[] = {
 	{}
 };
 
+static u8 mtl_pmc_list[] = {PMC_IDX_MAIN, PMC_IDX_IOE, PMC_IDX_MAX};
+
 #define MTL_GNA_PCI_DEV	0x7e4c
 #define MTL_IPU_PCI_DEV	0x7d19
 #define MTL_VPU_PCI_DEV	0x7d1d
@@ -995,6 +997,7 @@ static int mtl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_in
 static u32 MTL_PMT_DMU_GUIDS[] = {MTL_PMT_DMU_GUID, 0x0};
 struct pmc_dev_info mtl_pmc_dev = {
 	.dmu_guids = MTL_PMT_DMU_GUIDS,
+	.pmc_list = mtl_pmc_list,
 	.regmap_list = mtl_pmc_info_list,
 	.map = &mtl_socm_reg_map,
 	.sub_req_show = &pmc_core_substate_req_regs_fops,
diff --git a/drivers/platform/x86/intel/pmc/ptl.c b/drivers/platform/x86/intel/pmc/ptl.c
index 6c68772e738c8..538ca5ae2e9ec 100644
--- a/drivers/platform/x86/intel/pmc/ptl.c
+++ b/drivers/platform/x86/intel/pmc/ptl.c
@@ -543,6 +543,8 @@ static struct pmc_info ptl_pmc_info_list[] = {
 	{}
 };
 
+static u8 ptl_pmc_list[] = {PMC_IDX_MAIN, PMC_IDX_MAX};
+
 #define PTL_NPU_PCI_DEV                0xb03e
 #define PTL_IPU_PCI_DEV                0xb05d
 
@@ -569,6 +571,7 @@ static int ptl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_in
 }
 
 struct pmc_dev_info ptl_pmc_dev = {
+	.pmc_list = ptl_pmc_list,
 	.regmap_list = ptl_pmc_info_list,
 	.map = &ptl_pcdp_reg_map,
 	.sub_req_show = &pmc_core_substate_blk_req_fops,
diff --git a/drivers/platform/x86/intel/pmc/wcl.c b/drivers/platform/x86/intel/pmc/wcl.c
index b55069945e9e7..429f53f22a89f 100644
--- a/drivers/platform/x86/intel/pmc/wcl.c
+++ b/drivers/platform/x86/intel/pmc/wcl.c
@@ -469,6 +469,8 @@ static struct pmc_info wcl_pmc_info_list[] = {
 	{}
 };
 
+static u8 wcl_pmc_list[] = {PMC_IDX_MAIN, PMC_IDX_MAX};
+
 #define WCL_NPU_PCI_DEV                0xfd3e
 
 /*
@@ -494,6 +496,7 @@ static int wcl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_in
 
 struct pmc_dev_info wcl_pmc_dev = {
 	.regmap_list = wcl_pmc_info_list,
+	.pmc_list = wcl_pmc_list,
 	.map = &wcl_pcdn_reg_map,
 	.sub_req_show = &pmc_core_substate_blk_req_fops,
 	.suspend = cnl_suspend,
-- 
2.43.0

Re: [PATCH 5/6] platform/x86/intel/pmc: Retrieve PMC info only for available PMCs

[Ilpo Järvinen]

On Mon, 2 Mar 2026, Xi Pardee wrote:

> Update the Intel PMC Core driver to fetch PMC information only for
> available PMCs. Previously, the driver attempted to retrieve PMC info
> even when the corresponding PMC was not present.
> 
> This change aligns with recent updates to the Intel SSRAM Telemetry
> driver. Starting with NVL, the SSRAM Telemetry driver is probed for
> each individual SSRAM device. The prior implementation could not
> differentiate between an unavailable PMC and one that had not yet
> completed information retrieval. To resolve this, the PMC Core driver
> now skips obtaining PMC info for unavailable PMCs.
> 
> Signed-off-by: Xi Pardee <xi.pardee@linux.intel.com>
> ---
>  drivers/platform/x86/intel/pmc/arl.c  |  5 +++++
>  drivers/platform/x86/intel/pmc/core.c | 19 +++++++++++--------
>  drivers/platform/x86/intel/pmc/core.h |  2 ++
>  drivers/platform/x86/intel/pmc/lnl.c  |  3 +++
>  drivers/platform/x86/intel/pmc/mtl.c  |  3 +++
>  drivers/platform/x86/intel/pmc/ptl.c  |  3 +++
>  drivers/platform/x86/intel/pmc/wcl.c  |  3 +++
>  7 files changed, 30 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/platform/x86/intel/pmc/arl.c b/drivers/platform/x86/intel/pmc/arl.c
> index 4d91ee010f6d0..34506542c94da 100644
> --- a/drivers/platform/x86/intel/pmc/arl.c
> +++ b/drivers/platform/x86/intel/pmc/arl.c
> @@ -672,6 +672,9 @@ static struct pmc_info arl_pmc_info_list[] = {
>  	{}
>  };
>  
> +static u8 arl_pmc_list[] = {PMC_IDX_MAIN, PMC_IDX_IOE, PMC_IDX_PCH, PMC_IDX_MAX};
> +static u8 arl_h_pmc_list[] = {PMC_IDX_MAIN, PMC_IDX_IOE, PMC_IDX_MAX};

This seems a bit dangerous approach if somebody forgets to add that
PMC_IDX_MAX. It would be better to do it with sizeof() for safety).

> +
>  #define ARL_NPU_PCI_DEV			0xad1d
>  #define ARL_GNA_PCI_DEV			0xae4c
>  #define ARL_H_NPU_PCI_DEV		0x7d1d
> @@ -721,6 +724,7 @@ static int arl_h_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_
>  static u32 ARL_PMT_DMU_GUIDS[] = {ARL_PMT_DMU_GUID, 0x0};
>  struct pmc_dev_info arl_pmc_dev = {
>  	.dmu_guids = ARL_PMT_DMU_GUIDS,
> +	.pmc_list = arl_pmc_list,
>  	.regmap_list = arl_pmc_info_list,
>  	.map = &arl_socs_reg_map,
>  	.sub_req_show = &pmc_core_substate_req_regs_fops,
> @@ -735,6 +739,7 @@ struct pmc_dev_info arl_pmc_dev = {
>  static u32 ARL_H_PMT_DMU_GUIDS[] = {ARL_PMT_DMU_GUID, ARL_H_PMT_DMU_GUID, 0x0};
>  struct pmc_dev_info arl_h_pmc_dev = {
>  	.dmu_guids = ARL_H_PMT_DMU_GUIDS,
> +	.pmc_list = arl_h_pmc_list,
>  	.regmap_list = arl_pmc_info_list,
>  	.map = &mtl_socm_reg_map,
>  	.sub_req_show = &pmc_core_substate_req_regs_fops,
> diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c
> index 7bd0e1eaa32e2..85fff5e3abe0d 100644
> --- a/drivers/platform/x86/intel/pmc/core.c
> +++ b/drivers/platform/x86/intel/pmc/core.c
> @@ -1744,16 +1744,19 @@ static int pmc_core_pmc_add(struct pmc_dev *pmcdev, unsigned int pmc_idx)
>  	return 0;
>  }
>  
> -static int pmc_core_ssram_get_reg_base(struct pmc_dev *pmcdev)
> +static int pmc_core_ssram_get_reg_base(struct pmc_dev *pmcdev, u8 *pmc_list)
>  {
> +	unsigned int i;
>  	int ret;
>  
> -	ret = pmc_core_pmc_add(pmcdev, PMC_IDX_MAIN);
> -	if (ret)
> -		return ret;
> -
> -	pmc_core_pmc_add(pmcdev, PMC_IDX_IOE);
> -	pmc_core_pmc_add(pmcdev, PMC_IDX_PCH);
> +	for (i = 0; pmc_list[i] != PMC_IDX_MAX; ++i) {
> +		if (pmc_list[i] == PMC_IDX_MAIN) {
> +			ret = pmc_core_pmc_add(pmcdev, pmc_list[i]);
> +			if (ret)
> +				return ret;
> +		} else
> +			pmc_core_pmc_add(pmcdev, pmc_list[i]);

Isn't this same as:

		/* Non-MAIN PMCs are allowed to fail */
		ret = pmc_core_pmc_add(pmcdev, pmc_list[i]);
		if (ret && (pmc_list[i] == PMC_IDX_MAIN))
			return ret;



> +	}
>  
>  	return 0;
>  }
> @@ -1775,7 +1778,7 @@ int generic_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info)
>  	ssram = pmc_dev_info->regmap_list != NULL;
>  	if (ssram) {
>  		pmcdev->regmap_list = pmc_dev_info->regmap_list;
> -		ret = pmc_core_ssram_get_reg_base(pmcdev);
> +		ret = pmc_core_ssram_get_reg_base(pmcdev, pmc_dev_info->pmc_list);
>  		/*
>  		 * EAGAIN error code indicates Intel PMC SSRAM Telemetry driver
>  		 * has not finished probe and PMC info is not available yet. Try
> diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h
> index f09791f866223..c4984e44f7b80 100644
> --- a/drivers/platform/x86/intel/pmc/core.h
> +++ b/drivers/platform/x86/intel/pmc/core.h
> @@ -501,6 +501,7 @@ enum pmc_index {
>   * @pc_guid:		GUID for telemetry region to read PKGC blocker info
>   * @pkgc_ltr_blocker_offset: Offset to PKGC LTR blockers in telemetry region
>   * @pkgc_blocker_offset:Offset to PKGC blocker in telemetry region
> + * @pmc_list:		Index list of available PMC
>   * @regmap_list:	Pointer to a list of pmc_info structure that could be
>   *			available for the platform. When set, this field implies
>   *			SSRAM support.
> @@ -521,6 +522,7 @@ struct pmc_dev_info {
>  	u32 pc_guid;
>  	u32 pkgc_ltr_blocker_offset;
>  	u32 pkgc_blocker_offset;
> +	u8 *pmc_list;
>  	struct pmc_info *regmap_list;
>  	const struct pmc_reg_map *map;
>  	const struct file_operations *sub_req_show;
> diff --git a/drivers/platform/x86/intel/pmc/lnl.c b/drivers/platform/x86/intel/pmc/lnl.c
> index 18f303af328e3..7b09b59e1326c 100644
> --- a/drivers/platform/x86/intel/pmc/lnl.c
> +++ b/drivers/platform/x86/intel/pmc/lnl.c
> @@ -544,6 +544,8 @@ static struct pmc_info lnl_pmc_info_list[] = {
>  	{}
>  };
>  
> +static u8 lnl_pmc_list[] = {PMC_IDX_MAIN, PMC_IDX_MAX};
> +
>  #define LNL_NPU_PCI_DEV		0x643e
>  #define LNL_IPU_PCI_DEV		0x645d
>  
> @@ -571,6 +573,7 @@ static int lnl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_in
>  }
>  
>  struct pmc_dev_info lnl_pmc_dev = {
> +	.pmc_list = lnl_pmc_list,
>  	.regmap_list = lnl_pmc_info_list,
>  	.map = &lnl_socm_reg_map,
>  	.sub_req_show = &pmc_core_substate_req_regs_fops,
> diff --git a/drivers/platform/x86/intel/pmc/mtl.c b/drivers/platform/x86/intel/pmc/mtl.c
> index b724dd8c34dba..6438fca266392 100644
> --- a/drivers/platform/x86/intel/pmc/mtl.c
> +++ b/drivers/platform/x86/intel/pmc/mtl.c
> @@ -965,6 +965,8 @@ static struct pmc_info mtl_pmc_info_list[] = {
>  	{}
>  };
>  
> +static u8 mtl_pmc_list[] = {PMC_IDX_MAIN, PMC_IDX_IOE, PMC_IDX_MAX};
> +
>  #define MTL_GNA_PCI_DEV	0x7e4c
>  #define MTL_IPU_PCI_DEV	0x7d19
>  #define MTL_VPU_PCI_DEV	0x7d1d
> @@ -995,6 +997,7 @@ static int mtl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_in
>  static u32 MTL_PMT_DMU_GUIDS[] = {MTL_PMT_DMU_GUID, 0x0};
>  struct pmc_dev_info mtl_pmc_dev = {
>  	.dmu_guids = MTL_PMT_DMU_GUIDS,
> +	.pmc_list = mtl_pmc_list,
>  	.regmap_list = mtl_pmc_info_list,
>  	.map = &mtl_socm_reg_map,
>  	.sub_req_show = &pmc_core_substate_req_regs_fops,
> diff --git a/drivers/platform/x86/intel/pmc/ptl.c b/drivers/platform/x86/intel/pmc/ptl.c
> index 6c68772e738c8..538ca5ae2e9ec 100644
> --- a/drivers/platform/x86/intel/pmc/ptl.c
> +++ b/drivers/platform/x86/intel/pmc/ptl.c
> @@ -543,6 +543,8 @@ static struct pmc_info ptl_pmc_info_list[] = {
>  	{}
>  };
>  
> +static u8 ptl_pmc_list[] = {PMC_IDX_MAIN, PMC_IDX_MAX};
> +
>  #define PTL_NPU_PCI_DEV                0xb03e
>  #define PTL_IPU_PCI_DEV                0xb05d
>  
> @@ -569,6 +571,7 @@ static int ptl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_in
>  }
>  
>  struct pmc_dev_info ptl_pmc_dev = {
> +	.pmc_list = ptl_pmc_list,
>  	.regmap_list = ptl_pmc_info_list,
>  	.map = &ptl_pcdp_reg_map,
>  	.sub_req_show = &pmc_core_substate_blk_req_fops,
> diff --git a/drivers/platform/x86/intel/pmc/wcl.c b/drivers/platform/x86/intel/pmc/wcl.c
> index b55069945e9e7..429f53f22a89f 100644
> --- a/drivers/platform/x86/intel/pmc/wcl.c
> +++ b/drivers/platform/x86/intel/pmc/wcl.c
> @@ -469,6 +469,8 @@ static struct pmc_info wcl_pmc_info_list[] = {
>  	{}
>  };
>  
> +static u8 wcl_pmc_list[] = {PMC_IDX_MAIN, PMC_IDX_MAX};
> +
>  #define WCL_NPU_PCI_DEV                0xfd3e
>  
>  /*
> @@ -494,6 +496,7 @@ static int wcl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_in
>  
>  struct pmc_dev_info wcl_pmc_dev = {
>  	.regmap_list = wcl_pmc_info_list,
> +	.pmc_list = wcl_pmc_list,
>  	.map = &wcl_pcdn_reg_map,
>  	.sub_req_show = &pmc_core_substate_blk_req_fops,
>  	.suspend = cnl_suspend,
> 

-- 
 i.

[PATCH 6/6] platform/x86/intel/pmc: Add Nova Lake support to intel_pmc_core driver

[Xi Pardee]

Add Nova Lake support in intel_pmc_core driver

Signed-off-by: Xi Pardee <xi.pardee@linux.intel.com>
---
 drivers/platform/x86/intel/pmc/Makefile |    2 +-
 drivers/platform/x86/intel/pmc/core.c   |    2 +
 drivers/platform/x86/intel/pmc/core.h   |   31 +
 drivers/platform/x86/intel/pmc/nvl.c    | 1537 +++++++++++++++++++++++
 drivers/platform/x86/intel/pmc/ptl.c    |    2 +-
 5 files changed, 1572 insertions(+), 2 deletions(-)
 create mode 100644 drivers/platform/x86/intel/pmc/nvl.c

diff --git a/drivers/platform/x86/intel/pmc/Makefile b/drivers/platform/x86/intel/pmc/Makefile
index bb960c8721d77..53e4a60dcf3cc 100644
--- a/drivers/platform/x86/intel/pmc/Makefile
+++ b/drivers/platform/x86/intel/pmc/Makefile
@@ -4,7 +4,7 @@
 #
 
 intel_pmc_core-y			:= core.o spt.o cnp.o icl.o \
-					   tgl.o adl.o mtl.o arl.o lnl.o ptl.o wcl.o
+					   tgl.o adl.o mtl.o arl.o lnl.o ptl.o wcl.o nvl.o
 obj-$(CONFIG_INTEL_PMC_CORE)		+= intel_pmc_core.o
 intel_pmc_core_pltdrv-y			:= pltdrv.o
 obj-$(CONFIG_INTEL_PMC_CORE)		+= intel_pmc_core_pltdrv.o
diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c
index 85fff5e3abe0d..81e1f55bb7916 100644
--- a/drivers/platform/x86/intel/pmc/core.c
+++ b/drivers/platform/x86/intel/pmc/core.c
@@ -1859,6 +1859,8 @@ static const struct x86_cpu_id intel_pmc_core_ids[] = {
 	X86_MATCH_VFM(INTEL_LUNARLAKE_M,	&lnl_pmc_dev),
 	X86_MATCH_VFM(INTEL_PANTHERLAKE_L,	&ptl_pmc_dev),
 	X86_MATCH_VFM(INTEL_WILDCATLAKE_L,	&wcl_pmc_dev),
+	X86_MATCH_VFM(INTEL_NOVALAKE,		&nvl_s_pmc_dev),
+	X86_MATCH_VFM(INTEL_NOVALAKE_L,		&nvl_h_pmc_dev),
 	{}
 };
 
diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h
index c4984e44f7b80..ccfde1dc10d30 100644
--- a/drivers/platform/x86/intel/pmc/core.h
+++ b/drivers/platform/x86/intel/pmc/core.h
@@ -307,6 +307,29 @@ enum ppfear_regs {
 #define WCL_NUM_S0IX_BLOCKER			94
 #define WCL_BLK_REQ_OFFSET			50
 
+/* Nova Lake */
+#define NVL_PCDH_PPFEAR_NUM_ENTRIES		13
+#define NVL_PCDH_PMC_MMIO_REG_LEN		0x363C
+#define NVL_PCDS_PMC_MMIO_REG_LEN		0x3118
+#define NVL_PCHS_PMC_MMIO_REG_LEN		0x30D8
+#define NVL_LPM_PRI_OFFSET			0x17A4
+#define NVL_LPM_EN_OFFSET			0x17A0
+#define NVL_LPM_RESIDENCY_OFFSET		0x17A8
+#define NVL_LPM_LIVE_STATUS_OFFSET		0x1760
+#define NVL_LPM_NUM_MAPS			15
+#define NVL_PCDH_NUM_S0IX_BLOCKER		107
+#define NVL_PCDS_NUM_S0IX_BLOCKER		71
+#define NVL_PCHS_NUM_S0IX_BLOCKER		54
+#define NVL_PCDS_PMC_LTR_RESERVED		0x1BAC
+#define NVL_PCDH_BLK_REQ_OFFSET			53
+#define NVL_PCDS_BLK_REQ_OFFSET			18
+#define NVL_PCHS_BLK_REQ_OFFSET			46
+#define NVL_PMT_PC_GUID				0x13000101
+#define NVL_PMT_DMU_GUID			0x1A000101
+#define NVL_LTR_BLK_OFFSET			64
+#define NVL_PKGC_BLK_OFFSET			4
+#define NVL_PMT_DMU_DIE_C6_OFFSET		25
+
 /* SSRAM PMC Device ID */
 /* LNL */
 #define PMC_DEVID_LNL_SOCM	0xa87f
@@ -329,6 +352,11 @@ enum ppfear_regs {
 #define PMC_DEVID_MTL_IOEP	0x7ecf
 #define PMC_DEVID_MTL_IOEM	0x7ebf
 
+/* NVL */
+#define PMC_DEVID_NVL_PCDH	0xd37e
+#define PMC_DEVID_NVL_PCDS	0xd47e
+#define PMC_DEVID_NVL_PCHS	0x6e27
+
 extern const char *pmc_lpm_modes[];
 
 struct pmc_bit_map {
@@ -556,6 +584,7 @@ extern const struct pmc_reg_map mtl_ioep_reg_map;
 extern const struct pmc_bit_map ptl_pcdp_clocksource_status_map[];
 extern const struct pmc_bit_map ptl_pcdp_vnn_req_status_3_map[];
 extern const struct pmc_bit_map ptl_pcdp_signal_status_map[];
+extern const struct pmc_bit_map ptl_pcdp_ltr_show_map[];
 
 void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev);
 int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value, int ignore);
@@ -579,6 +608,8 @@ extern struct pmc_dev_info arl_h_pmc_dev;
 extern struct pmc_dev_info lnl_pmc_dev;
 extern struct pmc_dev_info ptl_pmc_dev;
 extern struct pmc_dev_info wcl_pmc_dev;
+extern struct pmc_dev_info nvl_s_pmc_dev;
+extern struct pmc_dev_info nvl_h_pmc_dev;
 
 void cnl_suspend(struct pmc_dev *pmcdev);
 int cnl_resume(struct pmc_dev *pmcdev);
diff --git a/drivers/platform/x86/intel/pmc/nvl.c b/drivers/platform/x86/intel/pmc/nvl.c
new file mode 100644
index 0000000000000..ae338a4de2257
--- /dev/null
+++ b/drivers/platform/x86/intel/pmc/nvl.c
@@ -0,0 +1,1537 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * This file contains platform specific structure definitions
+ * and init function used by Nova Lake PCH.
+ *
+ * Copyright (c) 2026, Intel Corporation.
+ */
+
+#include <linux/pci.h>
+
+#include "core.h"
+
+/* PMC SSRAM PMT Telemetry GUIDS */
+#define PCDH_LPM_REQ_GUID 0x01093101
+#define PCHS_LPM_REQ_GUID 0x01092101
+#define PCDS_LPM_REQ_GUID 0x01091102
+
+/*
+ * Die Mapping to Product.
+ * Product PCDDie PCHDie
+ * NVL-H   PCD-H  None
+ * NVL-S   PCD-S  PCH-S
+ */
+
+static const struct pmc_bit_map nvl_pcdh_pfear_map[] = {
+	{"PMC_PGD0",                 BIT(0)},
+	{"FUSE_OSSE_PGD0",           BIT(1)},
+	{"SPI_PGD0",                 BIT(2)},
+	{"XHCI_PGD0",                BIT(3)},
+	{"SPA_PGD0",                 BIT(4)},
+	{"SPB_PGD0",                 BIT(5)},
+	{"MPFPW2_PGD0",              BIT(6)},
+	{"GBE_PGD0",                 BIT(7)},
+
+	{"SBR16B20_PGD0",            BIT(0)},
+	{"DBG_SBR_PGD0",             BIT(1)},
+	{"SBR16B7_PGD0",             BIT(2)},
+	{"STRC_PGD0",                BIT(3)},
+	{"SBR16B8_PGD0",             BIT(4)},
+	{"D2D_DISP_PGD1",            BIT(5)},
+	{"LPSS_PGD0",                BIT(6)},
+	{"LPC_PGD0",                 BIT(7)},
+
+	{"SMB_PGD0",                 BIT(0)},
+	{"ISH_PGD0",                 BIT(1)},
+	{"SBR16B2_PGD0",             BIT(2)},
+	{"NPK_PGD0",                 BIT(3)},
+	{"D2D_NOC_PGD1",             BIT(4)},
+	{"DBG_SBR16B_PGD0",          BIT(5)},
+	{"FUSE_PGD0",                BIT(6)},
+	{"SBR16B0_PGD0",             BIT(7)},
+
+	{"P2SB0_PGD0",               BIT(0)},
+	{"OTG_PGD0",                 BIT(1)},
+	{"EXI_PGD0",                 BIT(2)},
+	{"CSE_PGD0",                 BIT(3)},
+	{"CSME_KVM_PGD0",            BIT(4)},
+	{"CSME_PMT_PGD0",            BIT(5)},
+	{"CSME_CLINK_PGD0",          BIT(6)},
+	{"SBR16B21_PGD0",            BIT(7)},
+
+	{"CSME_USBR_PGD0",           BIT(0)},
+	{"SBR16B22_PGD0",            BIT(1)},
+	{"CSME_SMT1_PGD0",           BIT(2)},
+	{"MPFPW1_PGD0",              BIT(3)},
+	{"CSME_SMS2_PGD0",           BIT(4)},
+	{"CSME_SMS_PGD0",            BIT(5)},
+	{"CSME_RTC_PGD0",            BIT(6)},
+	{"CSMEPSF_PGD0",             BIT(7)},
+
+	{"D2D_NOC_PGD0",             BIT(0)},
+	{"ESE_PGD0",                 BIT(1)},
+	{"SBR16B6_PGD0",             BIT(2)},
+	{"P2SB1_PGD0",               BIT(3)},
+	{"SBR16B3_PGD0",             BIT(4)},
+	{"OSSE_SMT1_PGD0",           BIT(5)},
+	{"D2D_DISP_PGD0",            BIT(6)},
+	{"SNPS_USB2_A_PGD0",         BIT(7)},
+
+	{"U3FPW1_PGD0",              BIT(0)},
+	{"FIA_X_PGD0",               BIT(1)},
+	{"PSF4_PGD0",                BIT(2)},
+	{"CNVI_PGD0",                BIT(3)},
+	{"UFSX2_PGD0",               BIT(4)},
+	{"ENDBG_PGD0",               BIT(5)},
+	{"DBC_PGD0",                 BIT(6)},
+	{"FIA_PG_PGD0",              BIT(7)},
+
+	{"D2D_IPU_PGD0",             BIT(0)},
+	{"NPK_PGD1",                 BIT(1)},
+	{"FIACPCB_X_PGD0",           BIT(2)},
+	{"SBR8B4_PGD0",              BIT(3)},
+	{"DBG_PSF_PGD0",             BIT(4)},
+	{"PSF6_PGD0",                BIT(5)},
+	{"UFSPW1_PGD0",              BIT(6)},
+	{"FIA_U_PGD0",               BIT(7)},
+
+	{"PSF8_PGD0",                BIT(0)},
+	{"SBR16B9_PGD0",             BIT(1)},
+	{"PSF0_PGD0",                BIT(2)},
+	{"FIACPCB_U_PGD0",           BIT(3)},
+	{"TAM_PGD0",                 BIT(4)},
+	{"D2D_NOC_PGD2",             BIT(5)},
+	{"SBR8B2_PGD0",              BIT(6)},
+	{"THC0_PGD0",                BIT(7)},
+
+	{"THC1_PGD0",                BIT(0)},
+	{"PMC_PGD1",                 BIT(1)},
+	{"DISP_PGA1_PGD0",           BIT(2)},
+	{"TCSS_PGD0",                BIT(3)},
+	{"DISP_PGA_PGD0",            BIT(4)},
+	{"SBR16B1_PGD0",             BIT(5)},
+	{"SBRG_PGD0",                BIT(6)},
+	{"PSF5_PGD0",                BIT(7)},
+
+	{"SBR8B3_PGD0",              BIT(0)},
+	{"ACE_PGD0",                 BIT(1)},
+	{"ACE_PGD1",                 BIT(2)},
+	{"ACE_PGD2",                 BIT(3)},
+	{"ACE_PGD3",                 BIT(4)},
+	{"ACE_PGD4",                 BIT(5)},
+	{"ACE_PGD5",                 BIT(6)},
+	{"ACE_PGD6",                 BIT(7)},
+
+	{"ACE_PGD7",                 BIT(0)},
+	{"ACE_PGD8",                 BIT(1)},
+	{"ACE_PGD9",                 BIT(2)},
+	{"ACE_PGD10",                BIT(3)},
+	{"FIACPCB_PG_PGD0",          BIT(4)},
+	{"SNPS_USB2_B_PGD0",         BIT(5)},
+	{"OSSE_PGD0",                BIT(6)},
+	{"SBR8B0_PGD0",              BIT(7)},
+
+	{"SBR16B4_PGD0",             BIT(0)},
+	{"CSME_PTIO_PGD0",           BIT(1)},
+	{}
+};
+
+static const struct pmc_bit_map *ext_nvl_pcdh_pfear_map[] = {
+	nvl_pcdh_pfear_map,
+	NULL
+};
+
+const struct pmc_bit_map nvl_pcdh_clocksource_status_map[] = {
+	{"AON2_OFF_STS",                 BIT(0),	1},
+	{"AON3_OFF_STS",                 BIT(1),	0},
+	{"AON4_OFF_STS",                 BIT(2),	1},
+	{"AON5_OFF_STS",                 BIT(3),	1},
+	{"AON1_OFF_STS",                 BIT(4),	0},
+	{"XTAL_LVM_OFF_STS",             BIT(5),	0},
+	{"MPFPW1_0_PLL_OFF_STS",         BIT(6),	1},
+	{"D2D_PLL_OFF_STS",              BIT(7),	1},
+	{"USB3_PLL_OFF_STS",             BIT(8),	1},
+	{"AON3_SPL_OFF_STS",             BIT(9),	1},
+	{"MPFPW2_0_PLL_OFF_STS",         BIT(12),	1},
+	{"XTAL_AGGR_OFF_STS",            BIT(17),	1},
+	{"USB2_PLL_OFF_STS",             BIT(18),	0},
+	{"DDI2_PLL_OFF_STS",             BIT(19),	1},
+	{"SE_TCSS_PLL_OFF_STS",          BIT(20),	1},
+	{"DDI_PLL_OFF_STS",              BIT(21),	1},
+	{"FILTER_PLL_OFF_STS",           BIT(22),	1},
+	{"ACE_PLL_OFF_STS",              BIT(24),	0},
+	{"FABRIC_PLL_OFF_STS",           BIT(25),	1},
+	{"SOC_PLL_OFF_STS",              BIT(26),	1},
+	{"REF_PLL_OFF_STS",              BIT(28),	1},
+	{"IMG_PLL_OFF_STS",              BIT(29),	1},
+	{"GENLOCK_FILTER_PLL_OFF_STS",   BIT(30),	1},
+	{"RTC_PLL_OFF_STS",              BIT(31),	0},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pcdh_power_gating_status_0_map[] = {
+	{"PMC_PGD0_PG_STS",              BIT(0),	0},
+	{"FUSE_OSSE_PGD0_PG_STS",	 BIT(1),	0},
+	{"ESPISPI_PGD0_PG_STS",          BIT(2),	0},
+	{"XHCI_PGD0_PG_STS",             BIT(3),	1},
+	{"SPA_PGD0_PG_STS",              BIT(4),	1},
+	{"SPB_PGD0_PG_STS",              BIT(5),	1},
+	{"MPFPW2_PGD0_PG_STS",           BIT(6),	0},
+	{"GBE_PGD0_PG_STS",              BIT(7),	1},
+	{"SBR16B20_PGD0_PG_STS",         BIT(8),	0},
+	{"DBG_PGD0_PG_STS",              BIT(9),	0},
+	{"SBR16B7_PGD0_PG_STS",          BIT(10),	0},
+	{"STRC_PGD0_PG_STS",             BIT(11),	0},
+	{"SBR16B8_PGD0_PG_STS",          BIT(12),	0},
+	{"D2D_DISP_PGD1_PG_STS",         BIT(13),	1},
+	{"LPSS_PGD0_PG_STS",             BIT(14),	1},
+	{"LPC_PGD0_PG_STS",              BIT(15),	0},
+	{"SMB_PGD0_PG_STS",              BIT(16),	0},
+	{"ISH_PGD0_PG_STS",              BIT(17),	0},
+	{"SBR16B2_PGD0_PG_STS",          BIT(18),	0},
+	{"NPK_PGD0_PG_STS",              BIT(19),	0},
+	{"D2D_NOC_PGD1_PG_STS",          BIT(20),	1},
+	{"DBG_SBR16B_PGD0_PG_STS",       BIT(21),	0},
+	{"FUSE_PGD0_PG_STS",             BIT(22),	0},
+	{"SBR16B0_PGD0_PG_STS",          BIT(23),	0},
+	{"P2SB0_PGD0_PG_STS",            BIT(24),	1},
+	{"XDCI_PGD0_PG_STS",             BIT(25),	1},
+	{"EXI_PGD0_PG_STS",              BIT(26),	0},
+	{"CSE_PGD0_PG_STS",              BIT(27),	1},
+	{"KVMCC_PGD0_PG_STS",            BIT(28),	1},
+	{"PMT_PGD0_PG_STS",              BIT(29),	1},
+	{"CLINK_PGD0_PG_STS",            BIT(30),	1},
+	{"SBR16B21_PGD0_PG_STS",         BIT(31),	0},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pcdh_power_gating_status_1_map[] = {
+	{"USBR0_PGD0_PG_STS",            BIT(0),	1},
+	{"SBR16B22_PGD0_PG_STS",         BIT(1),	0},
+	{"SMT1_PGD0_PG_STS",             BIT(2),	1},
+	{"MPFPW1_PGD0_PG_STS",           BIT(3),	0},
+	{"SMS2_PGD0_PG_STS",             BIT(4),	1},
+	{"SMS1_PGD0_PG_STS",             BIT(5),	1},
+	{"CSMERTC_PGD0_PG_STS",          BIT(6),	0},
+	{"CSMEPSF_PGD0_PG_STS",          BIT(7),	0},
+	{"D2D_NOC_PGD0_PG_STS",          BIT(8),	0},
+	{"ESE_PGD0_PG_STS",              BIT(9),	1},
+	{"SBR16B6_PGD0_PG_STS",          BIT(10),	0},
+	{"P2SB1_PGD0_PG_STS",            BIT(11),	1},
+	{"SBR16B3_PGD0_PG_STS",          BIT(12),	0},
+	{"OSSE_SMT1_PGD0_PG_STS",        BIT(13),	1},
+	{"D2D_DISP_PGD0_PG_STS",         BIT(14),	1},
+	{"SNPA_USB2_A_PGD0_PG_STS",      BIT(15),	0},
+	{"U3FPW1_PGD0_PG_STS",           BIT(16),	0},
+	{"FIA_X_PGD0_PG_STS",            BIT(17),	0},
+	{"PSF4_PGD0_PG_STS",             BIT(18),	0},
+	{"CNVI_PGD0_PG_STS",             BIT(19),	0},
+	{"UFSX2_PGD0_PG_STS",            BIT(20),	1},
+	{"ENDBG_PGD0_PG_STS",            BIT(21),	0},
+	{"DBC_PGD0_PG_STS",              BIT(22),	0},
+	{"FIA_PG_PGD0_PG_STS",           BIT(23),	0},
+	{"D2D_IPU_PGD0_PG_STS",          BIT(24),	1},
+	{"NPK_PGD1_PG_STS",              BIT(25),	0},
+	{"FIACPCB_X_PGD0_PG_STS",        BIT(26),	0},
+	{"SBR8B4_PGD0_PG_STS",           BIT(27),	0},
+	{"DBG_PSF_PGD0_PG_STS",          BIT(28),	0},
+	{"PSF6_PGD0_PG_STS",             BIT(29),	0},
+	{"UFSPW1_PGD0_PG_STS",           BIT(30),	0},
+	{"FIA_U_PGD0_PG_STS",            BIT(31),	0},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pcdh_power_gating_status_2_map[] = {
+	{"PSF8_PGD0_PG_STS",             BIT(0),	0},
+	{"SBR16B9_PGD0_PG_STS",          BIT(1),	0},
+	{"PSF0_PGD0_PG_STS",             BIT(2),	0},
+	{"FIACPCB_U_PGD0_PG_STS",        BIT(3),	0},
+	{"TAM_PGD0_PG_STS",              BIT(4),	1},
+	{"D2D_NOC_PGD2_PG_STS",          BIT(5),	1},
+	{"SBR8B2_PGD0_PG_STS",           BIT(6),	0},
+	{"THC0_PGD0_PG_STS",             BIT(7),	1},
+	{"THC1_PGD0_PG_STS",             BIT(8),	1},
+	{"PMC_PGD1_PG_STS",              BIT(9),	0},
+	{"DISP_PGA1_PGD0_PG_STS",        BIT(10),	0},
+	{"TCSS_PGD0_PG_STS",             BIT(11),	0},
+	{"DISP_PGA_PGD0_PG_STS",         BIT(12),	0},
+	{"SBR16B1_PGD0_PG_STS",          BIT(13),	0},
+	{"SBRG_PGD0_PG_STS",             BIT(14),	0},
+	{"PSF5_PGD0_PG_STS",             BIT(15),	0},
+	{"SBR8B3_PGD0_PG_STS",           BIT(16),	0},
+	{"ACE_PGD0_PG_STS",              BIT(17),	0},
+	{"ACE_PGD1_PG_STS",              BIT(18),	0},
+	{"ACE_PGD2_PG_STS",              BIT(19),	0},
+	{"ACE_PGD3_PG_STS",              BIT(20),	0},
+	{"ACE_PGD4_PG_STS",              BIT(21),	0},
+	{"ACE_PGD5_PG_STS",              BIT(22),	0},
+	{"ACE_PGD6_PG_STS",              BIT(23),	0},
+	{"ACE_PGD7_PG_STS",              BIT(24),	0},
+	{"ACE_PGD8_PG_STS",              BIT(25),	0},
+	{"ACE_PGD9_PG_STS",              BIT(26),	0},
+	{"ACE_PGD10_PG_STS",             BIT(27),	0},
+	{"FIACPCB_PG_PGD0_PG_STS",       BIT(28),	0},
+	{"SNPS_USB2_B_PGD0_PG_STS",      BIT(29),	0},
+	{"OSSE_PGD0_PG_STS",             BIT(30),	1},
+	{"SBR8B0_PGD0_PG_STS",           BIT(31),	0},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pcdh_power_gating_status_3_map[] = {
+	{"SBR16B4_PGD0_PG_STS",          BIT(0),	0},
+	{"PTIO_PGD0_PG_STS",             BIT(1),	1},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pcdh_d3_status_0_map[] = {
+	{"LPSS_D3_STS",                  BIT(3),	1},
+	{"XDCI_D3_STS",                  BIT(4),	1},
+	{"XHCI_D3_STS",                  BIT(5),	1},
+	{"OSSE_D3_STS",                  BIT(6),	0},
+	{"SPA_D3_STS",                   BIT(12),	0},
+	{"SPB_D3_STS",                   BIT(13),	0},
+	{"ESPISPI_D3_STS",               BIT(18),	0},
+	{"PSTH_D3_STS",                  BIT(21),	0},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pcdh_d3_status_1_map[] = {
+	{"OSSE_SMT1_D3_STS",             BIT(0),	0},
+	{"GBE_D3_STS",                   BIT(19),	0},
+	{"ITSS_D3_STS",                  BIT(23),	0},
+	{"CNVI_D3_STS",                  BIT(27),	0},
+	{"UFSX2_D3_STS",                 BIT(28),	0},
+	{"ESE_D3_STS",                   BIT(29),	0},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pcdh_d3_status_2_map[] = {
+	{"CSMERTC_D3_STS",               BIT(1),	0},
+	{"CSE_D3_STS",                   BIT(4),	0},
+	{"KVMCC_D3_STS",                 BIT(5),	0},
+	{"USBR0_D3_STS",                 BIT(6),	0},
+	{"ISH_D3_STS",                   BIT(7),	0},
+	{"SMT1_D3_STS",                  BIT(8),	0},
+	{"SMT2_D3_STS",                  BIT(9),	0},
+	{"SMT3_D3_STS",                  BIT(10),	0},
+	{"OSSE_SMT2_D3_STS",             BIT(11),	0},
+	{"CLINK_D3_STS",                 BIT(14),	0},
+	{"PTIO_D3_STS",                  BIT(16),	0},
+	{"PMT_D3_STS",                   BIT(17),	0},
+	{"SMS1_D3_STS",                  BIT(18),	0},
+	{"SMS2_D3_STS",                  BIT(19),	0},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pcdh_d3_status_3_map[] = {
+	{"THC0_D3_STS",                  BIT(14),	1},
+	{"THC1_D3_STS",                  BIT(15),	1},
+	{"OSSE_SMT3_D3_STS",             BIT(16),	0},
+	{"ACE_D3_STS",                   BIT(23),	0},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pcdh_vnn_req_status_0_map[] = {
+	{"LPSS_VNN_REQ_STS",             BIT(3),	1},
+	{"OSSE_VNN_REQ_STS",             BIT(6),	1},
+	{"ESPISPI_VNN_REQ_STS",          BIT(18),	1},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pcdh_vnn_req_status_1_map[] = {
+	{"OSSE_SMT1_VNN_REQ_STS",        BIT(0),	1},
+	{"NPK_VNN_REQ_STS",              BIT(4),	1},
+	{"DFXAGG_VNN_REQ_STS",           BIT(8),	0},
+	{"EXI_VNN_REQ_STS",              BIT(9),	1},
+	{"P2D_VNN_REQ_STS",              BIT(18),	1},
+	{"GBE_VNN_REQ_STS",              BIT(19),	1},
+	{"SMB_VNN_REQ_STS",              BIT(25),	1},
+	{"LPC_VNN_REQ_STS",              BIT(26),	0},
+	{"ESE_VNN_REQ_STS",              BIT(29),	1},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pcdh_vnn_req_status_2_map[] = {
+	{"CSMERTC_VNN_REQ_STS",          BIT(1),	1},
+	{"CSE_VNN_REQ_STS",              BIT(4),	1},
+	{"ISH_VNN_REQ_STS",              BIT(7),	1},
+	{"SMT1_VNN_REQ_STS",             BIT(8),	1},
+	{"CLINK_VNN_REQ_STS",            BIT(14),	1},
+	{"SMS1_VNN_REQ_STS",             BIT(18),	1},
+	{"SMS2_VNN_REQ_STS",             BIT(19),	1},
+	{"GPIOCOM4_VNN_REQ_STS",         BIT(20),	1},
+	{"GPIOCOM3_VNN_REQ_STS",         BIT(21),	1},
+	{"DISP_SHIM_VNN_REQ_STS",        BIT(22),	1},
+	{"GPIOCOM1_VNN_REQ_STS",         BIT(23),	1},
+	{"GPIOCOM0_VNN_REQ_STS",         BIT(24),	1},
+	{}
+};
+
+const struct pmc_bit_map nvl_pcdh_vnn_req_status_3_map[] = {
+	{"DTS0_VNN_REQ_STS",             BIT(7),	0},
+	{"GPIOCOM5_VNN_REQ_STS",         BIT(11),	1},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pcdh_vnn_misc_status_map[] = {
+	{"CPU_C10_REQ_STS",              BIT(0),	0},
+	{"TS_OFF_REQ_STS",               BIT(1),	0},
+	{"PNDE_MET_REQ_STS",             BIT(2),	1},
+	{"PG5_PMA0_REQ_STS",             BIT(3),	1},
+	{"FW_THROTTLE_ALLOWED_REQ_STS",  BIT(4),	0},
+	{"VNN_SOC_REQ_STS",              BIT(6),	1},
+	{"ISH_VNNAON_REQ_STS",           BIT(7),	0},
+	{"D2D_NOC_CFI_QACTIVE_REQ_STS",	 BIT(8),	1},
+	{"D2D_NOC_GPSB_QACTIVE_REQ_STS", BIT(9),	1},
+	{"D2D_IPU_QACTIVE_REQ_STS",      BIT(10),	1},
+	{"PLT_GREATER_REQ_STS",          BIT(11),	1},
+	{"ALL_SBR_IDLE_REQ_STS",         BIT(12),	0},
+	{"PMC_IDLE_FB_OCP_REQ_STS",      BIT(13),	0},
+	{"PM_SYNC_STATES_REQ_STS",       BIT(14),	0},
+	{"EA_REQ_STS",                   BIT(15),	0},
+	{"MPHY_CORE_OFF_REQ_STS",        BIT(16),	0},
+	{"BRK_EV_EN_REQ_STS",            BIT(17),	0},
+	{"AUTO_DEMO_EN_REQ_STS",         BIT(18),	0},
+	{"ITSS_CLK_SRC_REQ_STS",         BIT(19),	1},
+	{"ARC_IDLE_REQ_STS",             BIT(21),	0},
+	{"PG5_PMA1_REQ_STS",             BIT(22),	1},
+	{"FIA_DEEP_PM_REQ_STS",          BIT(23),	0},
+	{"XDCI_ATTACHED_REQ_STS",        BIT(24),	1},
+	{"ARC_INTERRUPT_WAKE_REQ_STS",   BIT(25),	0},
+	{"D2D_DISP_DDI_QACTIVE_REQ_STS", BIT(26),	1},
+	{"PRE_WAKE0_REQ_STS",            BIT(27),	1},
+	{"PRE_WAKE1_REQ_STS",            BIT(28),	1},
+	{"PRE_WAKE2_REQ_STS",            BIT(29),	1},
+	{"PG5_PMA2_GVNN",                BIT(30),	1},
+	{"D2D_DISP_EDP_QACTIVE_REQ_STS", BIT(31),	1},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pcdh_rsc_status_map[] = {
+	{"CORE",		0,		1},
+	{"Memory",		0,		1},
+	{"PRIM_D2D",		0,		1},
+	{"PSF0",		0,		1},
+	{"PSF4",		0,		1},
+	{"PSF6",		0,		1},
+	{"PSF8",		0,		1},
+	{"SB",			0,		1},
+	{}
+};
+
+static const struct pmc_bit_map *nvl_pcdh_lpm_maps[] = {
+	nvl_pcdh_clocksource_status_map,
+	nvl_pcdh_power_gating_status_0_map,
+	nvl_pcdh_power_gating_status_1_map,
+	nvl_pcdh_power_gating_status_2_map,
+	nvl_pcdh_power_gating_status_3_map,
+	nvl_pcdh_d3_status_0_map,
+	nvl_pcdh_d3_status_1_map,
+	nvl_pcdh_d3_status_2_map,
+	nvl_pcdh_d3_status_3_map,
+	nvl_pcdh_vnn_req_status_0_map,
+	nvl_pcdh_vnn_req_status_1_map,
+	nvl_pcdh_vnn_req_status_2_map,
+	nvl_pcdh_vnn_req_status_3_map,
+	nvl_pcdh_vnn_misc_status_map,
+	ptl_pcdp_signal_status_map,
+	NULL
+};
+
+static const struct pmc_bit_map *nvl_pcdh_blk_maps[] = {
+	nvl_pcdh_power_gating_status_0_map,
+	nvl_pcdh_power_gating_status_1_map,
+	nvl_pcdh_power_gating_status_2_map,
+	nvl_pcdh_power_gating_status_3_map,
+	nvl_pcdh_rsc_status_map,
+	nvl_pcdh_vnn_req_status_0_map,
+	nvl_pcdh_vnn_req_status_1_map,
+	nvl_pcdh_vnn_req_status_2_map,
+	nvl_pcdh_vnn_req_status_3_map,
+	nvl_pcdh_d3_status_0_map,
+	nvl_pcdh_d3_status_1_map,
+	nvl_pcdh_d3_status_2_map,
+	nvl_pcdh_d3_status_3_map,
+	nvl_pcdh_clocksource_status_map,
+	nvl_pcdh_vnn_misc_status_map,
+	ptl_pcdp_signal_status_map,
+	NULL
+};
+
+static const struct pmc_bit_map nvl_pcds_pfear_map[] = {
+	{"PMC_PGD0",                 BIT(0)},
+	{"FUSE_OSSE_PGD0",           BIT(1)},
+	{"SPI_PGD0",                 BIT(2)},
+	{"XHCI_PGD0",                BIT(3)},
+	{"SPA_PGD0",                 BIT(4)},
+	{"SPB_PGD0",                 BIT(5)},
+	{"RSVD6",                    BIT(6)},
+	{"GBE_PGD0",                 BIT(7)},
+
+	{"RSVD8",                    BIT(0)},
+	{"RSVD9",                    BIT(1)},
+	{"SBR16B7_PGD0",             BIT(2)},
+	{"SBR16B21_PGD0",            BIT(3)},
+	{"RSVD12",                   BIT(4)},
+	{"D2D_DISP_PGD1",            BIT(5)},
+	{"LPSS_PGD0",                BIT(6)},
+	{"LPC_PGD0",                 BIT(7)},
+
+	{"SMB_PGD0",                 BIT(0)},
+	{"ISH_PGD0",                 BIT(1)},
+	{"SBR16B1_PGD0",             BIT(2)},
+	{"NPK_PGD0",                 BIT(3)},
+	{"D2D_NOC_PGD1",             BIT(4)},
+	{"DBG_SBR16B_PGD0",          BIT(5)},
+	{"FUSE_PGD0",                BIT(6)},
+	{"RSVD23",                   BIT(7)},
+
+	{"P2SB0_PGD0",               BIT(0)},
+	{"OTG_PGD0",                 BIT(1)},
+	{"EXI_PGD0",                 BIT(2)},
+	{"CSE_PGD0",                 BIT(3)},
+	{"CSME_KVM_PGD0",            BIT(4)},
+	{"CSME_PMT_PGD0",            BIT(5)},
+	{"CSME_CLINK_PGD0",          BIT(6)},
+	{"CSME_PTIO_PGD0",           BIT(7)},
+
+	{"CSME_USBR_PGD0",           BIT(0)},
+	{"SBR16B22_PGD0",            BIT(1)},
+	{"CSME_SMT1_PGD0",           BIT(2)},
+	{"P2SB1_PGD0",               BIT(3)},
+	{"CSME_SMS2_PGD0",           BIT(4)},
+	{"CSME_SMS_PGD0",            BIT(5)},
+	{"CSME_RTC_PGD0",            BIT(6)},
+	{"CSMEPSF_PGD0",             BIT(7)},
+
+	{"D2D_NOC_PGD0",             BIT(0)},
+	{"RSVD41",                   BIT(1)},
+	{"RSVD42",                   BIT(2)},
+	{"RSVD43",                   BIT(3)},
+	{"SBR16B2_PGD0",             BIT(4)},
+	{"OSSE_SMT1_PGD0",           BIT(5)},
+	{"D2D_DISP_PGD0",            BIT(6)},
+	{"RSVD47_PGD0",              BIT(7)},
+
+	{"RSVD48",                   BIT(0)},
+	{"DBG_PSF_PGD0",             BIT(1)},
+	{"RSVD50",                   BIT(2)},
+	{"CNVI_PGD0",                BIT(3)},
+	{"UFSX2_PGD0",               BIT(4)},
+	{"ENDBG_PGD0",               BIT(5)},
+	{"DBC_PGD0",                 BIT(6)},
+	{"SBR16B4_PGD0",             BIT(7)},
+
+	{"RSVD56",                   BIT(0)},
+	{"NPK_PGD1",                 BIT(1)},
+	{"RSVD58",                   BIT(2)},
+	{"SBR16B20_PGD0",            BIT(3)},
+	{"RSVD60",                   BIT(4)},
+	{"SBR8B20_PGD0",             BIT(5)},
+	{"RSVD62",                   BIT(6)},
+	{"FIA_U_PGD0",               BIT(7)},
+
+	{"PSF8_PGD0",                BIT(0)},
+	{"RSVD65",                   BIT(1)},
+	{"RSVD66",                   BIT(2)},
+	{"FIACPCB_U_PGD0",           BIT(3)},
+	{"TAM_PGD0",                 BIT(4)},
+	{"D2D_NOC_PGD2",             BIT(5)},
+	{"SBR8B2_PGD0",              BIT(6)},
+	{"THC0_PGD0",                BIT(7)},
+
+	{"THC1_PGD0",                BIT(0)},
+	{"PMC_PGD1",                 BIT(1)},
+	{"SBR16B3_PGD0",             BIT(2)},
+	{"TCSS_PGD0",                BIT(3)},
+	{"DISP_PGA_PGD0",            BIT(4)},
+	{"RSVD77",                   BIT(5)},
+	{"RSVD78",                   BIT(6)},
+	{"RSVD79",                   BIT(7)},
+
+	{"SBRG_PGD0",                BIT(0)},
+	{"RSVD81",                   BIT(1)},
+	{"SBR16B0_PGD0",             BIT(2)},
+	{"SBR8B0_PGD0",              BIT(3)},
+	{"PSF7_PGD0",                BIT(4)},
+	{"RSVD85",                   BIT(5)},
+	{"RSVD86",                   BIT(6)},
+	{"RSVD87",                   BIT(7)},
+
+	{"SBR16B6_PGD0",             BIT(0)},
+	{"PSD0_PGD0",                BIT(1)},
+	{"STRC_PGD0",                BIT(2)},
+	{"RSVD91",                   BIT(3)},
+	{"DBG_SBR_PGD0",             BIT(4)},
+	{"RSVD93",                   BIT(5)},
+	{"OSSE_PGD0",                BIT(6)},
+	{"DISP_PGA1_PGD0",           BIT(7)},
+	{}
+};
+
+static const struct pmc_bit_map *ext_nvl_pcds_pfear_map[] = {
+	nvl_pcds_pfear_map,
+	NULL
+};
+
+static const struct pmc_bit_map nvl_pcds_ltr_show_map[] = {
+	{"SOUTHPORT_A",		CNP_PMC_LTR_SPA},
+	{"SOUTHPORT_B",		CNP_PMC_LTR_SPB},
+	{"SATA",		CNP_PMC_LTR_SATA},
+	{"GIGABIT_ETHERNET",	CNP_PMC_LTR_GBE},
+	{"XHCI",		CNP_PMC_LTR_XHCI},
+	{"SOUTHPORT_F",		ADL_PMC_LTR_SPF},
+	{"ME",			CNP_PMC_LTR_ME},
+	{"SATA1",		CNP_PMC_LTR_EVA},
+	{"SOUTHPORT_C",		CNP_PMC_LTR_SPC},
+	{"HD_AUDIO",		CNP_PMC_LTR_AZ},
+	{"CNV",			CNP_PMC_LTR_CNV},
+	{"LPSS",		CNP_PMC_LTR_LPSS},
+	{"SOUTHPORT_D",		CNP_PMC_LTR_SPD},
+	{"SOUTHPORT_E",		CNP_PMC_LTR_SPE},
+	{"SATA2",		PTL_PMC_LTR_SATA2},
+	{"ESPI",		CNP_PMC_LTR_ESPI},
+	{"SCC",			CNP_PMC_LTR_SCC},
+	{"ISH",			CNP_PMC_LTR_ISH},
+	{"UFSX2",		CNP_PMC_LTR_UFSX2},
+	{"EMMC",		CNP_PMC_LTR_EMMC},
+	{"WIGIG",		ICL_PMC_LTR_WIGIG},
+	{"THC0",		TGL_PMC_LTR_THC0},
+	{"THC1",		TGL_PMC_LTR_THC1},
+	{"SOUTHPORT_G",		MTL_PMC_LTR_SPG},
+	{"RSVD",		NVL_PCDS_PMC_LTR_RESERVED},
+	{"IOE_PMC",		MTL_PMC_LTR_IOE_PMC},
+	{"DMI3",		ARL_PMC_LTR_DMI3},
+	{"OSSE",		LNL_PMC_LTR_OSSE},
+
+	/* Below two cannot be used for LTR_IGNORE */
+	{"CURRENT_PLATFORM",	PTL_PMC_LTR_CUR_PLT},
+	{"AGGREGATED_SYSTEM",	PTL_PMC_LTR_CUR_ASLT},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pcds_clocksource_status_map[] = {
+	{"AON2_OFF_STS",                 BIT(0),	1},
+	{"AON3_OFF_STS",                 BIT(1),	0},
+	{"AON4_OFF_STS",                 BIT(2),	1},
+	{"AON5_OFF_STS",                 BIT(3),	1},
+	{"AON1_OFF_STS",                 BIT(4),	0},
+	{"XTAL_LVM_OFF_STS",             BIT(5),	0},
+	{"D2D_OFF_STS",                  BIT(8),	1},
+	{"AON3_SPL_OFF_STS",             BIT(9),	1},
+	{"XTAL_AGGR_OFF_STS",            BIT(17),	1},
+	{"BCLK_EXT_INJ_OFF_STS",         BIT(18),	1},
+	{"DDI2_PLL_OFF_STS",             BIT(19),	1},
+	{"SE_TCSS_PLL_OFF_STS",          BIT(20),	1},
+	{"DDI_PLL_OFF_STS",              BIT(21),	1},
+	{"FILTER_PLL_OFF_STS",           BIT(22),	1},
+	{"PHY_OC_EXT_INJ_OFF_STS",       BIT(23),	1},
+	{"ACE_PLL_OFF_STS",              BIT(24),	0},
+	{"FABRIC_PLL_OFF_STS",           BIT(25),	1},
+	{"SOC_PLL_OFF_STS",              BIT(26),	1},
+	{"REF_PLL_OFF_STS",              BIT(28),	1},
+	{"GENLOCK_FILTER_PLL_OFF_STS",   BIT(30),	1},
+	{"RTC_PLL_OFF_STS",              BIT(31),	0},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pcds_power_gating_status_0_map[] = {
+	{"PMC_PGD0_PG_STS",              BIT(0),	0},
+	{"FUSE_OSSE_PGD0_PG_STS",	 BIT(1),	0},
+	{"ESPISPI_PGD0_PG_STS",          BIT(2),	0},
+	{"XHCI_PGD0_PG_STS",             BIT(3),	0},
+	{"SPA_PGD0_PG_STS",              BIT(4),	0},
+	{"SPB_PGD0_PG_STS",              BIT(5),	0},
+	{"RSVD_6",                       BIT(6),	0},
+	{"GBE_PGD0_PG_STS",              BIT(7),	0},
+	{"RSVD_8",                       BIT(8),	0},
+	{"RSVD_9",                       BIT(9),	0},
+	{"SBR16B7_PGD0_PG_STS",          BIT(10),	0},
+	{"SBR16B21_PGD0_PG_STS",         BIT(11),	0},
+	{"RSVD_12",                      BIT(12),	0},
+	{"D2D_DISP_PGD1_PG_STS",         BIT(13),	1},
+	{"LPSS_PGD0_PG_STS",             BIT(14),	0},
+	{"LPC_PGD0_PG_STS",              BIT(15),	0},
+	{"SMB_PGD0_PG_STS",              BIT(16),	0},
+	{"ISH_PGD0_PG_STS",              BIT(17),	0},
+	{"SBR16B1_PGD0_PG_STS",          BIT(18),	0},
+	{"NPK_PGD0_PG_STS",              BIT(19),	0},
+	{"D2D_NOC_PGD1_PG_STS",          BIT(20),	1},
+	{"DBG_SBR16B_PGD0_PG_STS",       BIT(21),	0},
+	{"FUSE_PGD0_PG_STS",             BIT(22),	0},
+	{"RSVD_23",                      BIT(23),	0},
+	{"P2SB0_PGD0_PG_STS",            BIT(24),	1},
+	{"XDCI_PGD0_PG_STS",             BIT(25),	0},
+	{"EXI_PGD0_PG_STS",              BIT(26),	0},
+	{"CSE_PGD0_PG_STS",              BIT(27),	1},
+	{"KVMCC_PGD0_PG_STS",            BIT(28),	0},
+	{"PMT_PGD0_PG_STS",              BIT(29),	0},
+	{"CLINK_PGD0_PG_STS",            BIT(30),	0},
+	{"PTIO_PGD0_PG_STS",             BIT(31),	0},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pcds_power_gating_status_1_map[] = {
+	{"USBR0_PGD0_PG_STS",            BIT(0),	0},
+	{"SBR16B22_PGD0_PG_STS",         BIT(1),	0},
+	{"SMT1_PGD0_PG_STS",             BIT(2),	0},
+	{"P2SB1_PGD0_PG_STS",            BIT(3),	1},
+	{"SMS2_PGD0_PG_STS",             BIT(4),	0},
+	{"SMS1_PGD0_PG_STS",             BIT(5),	0},
+	{"CSMERTC_PGD0_PG_STS",          BIT(6),	0},
+	{"CSMEPSF_PGD0_PG_STS",          BIT(7),	0},
+	{"D2D_NOC_PGD0_PG_STS",          BIT(8),	0},
+	{"RSVD_9",                       BIT(9),	0},
+	{"RSVD_10",                      BIT(10),	0},
+	{"RSVD_11",                      BIT(11),	0},
+	{"SBR16B2_PGD0_PG_STS",          BIT(12),	0},
+	{"OSSE_SMT1_PGD0_PG_STS",        BIT(13),	1},
+	{"D2D_DISP_PGD0_PG_STS",         BIT(14),	1},
+	{"RSVD_15",                      BIT(15),	0},
+	{"RSVD_16",                      BIT(16),	0},
+	{"DBG_PSF_PGD0_PG_STS",          BIT(17),	0},
+	{"RSVD_18",                      BIT(18),	0},
+	{"CNVI_PGD0_PG_STS",             BIT(19),	0},
+	{"UFSX2_PGD0_PG_STS",            BIT(20),	0},
+	{"ENDBG_PGD0_PG_STS",            BIT(21),	0},
+	{"DBC_PGD0_PG_STS",              BIT(22),	0},
+	{"SBR16B4_PGD0_PG_STS",          BIT(23),	0},
+	{"RSVD_24",                      BIT(24),	0},
+	{"NPK_PGD1_PG_STS",              BIT(25),	0},
+	{"RSVD_26",                      BIT(26),	0},
+	{"SBR16B20_PGD0_PG_STS",         BIT(27),	0},
+	{"RSVD_28",                      BIT(28),	0},
+	{"SBR8B20_PGD0_PG_STS",          BIT(29),	0},
+	{"RSVD_30",                      BIT(30),	0},
+	{"FIA_U_PGD0_PG_STS",            BIT(31),	0},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pcds_power_gating_status_2_map[] = {
+	{"PSF8_PGD0_PG_STS",             BIT(0),	0},
+	{"RSVD_1",                       BIT(1),	0},
+	{"RSVD_2",                       BIT(2),	0},
+	{"FIACPCB_U_PGD0_PG_STS",        BIT(3),	0},
+	{"TAM_PGD0_PG_STS",              BIT(4),	1},
+	{"D2D_NOC_PGD2_PG_STS",          BIT(5),	1},
+	{"SBR8B2_PGD0_PG_STS",           BIT(6),	0},
+	{"THC0_PGD0_PG_STS",             BIT(7),	0},
+	{"THC1_PGD0_PG_STS",             BIT(8),	0},
+	{"PMC_PGD1_PG_STS",              BIT(9),	0},
+	{"SBR16B3_PGD0_PG_STS",          BIT(10),	0},
+	{"TCSS_PGD0_PG_STS",             BIT(11),	0},
+	{"DISP_PGA_PGD0_PG_STS",         BIT(12),	0},
+	{"RSVD_13",                      BIT(13),	0},
+	{"RSVD_14",                      BIT(14),	0},
+	{"RSVD_15",                      BIT(15),	0},
+	{"SBRG_PGD0_PG_STS",             BIT(16),	0},
+	{"RSVD_17",                      BIT(17),	0},
+	{"SBR16B0_PGD0_PG_STS",          BIT(18),	0},
+	{"SBR8B0_PGD0_PG_STS",           BIT(19),	0},
+	{"PSF7_PGD0_PG_STS",             BIT(20),	0},
+	{"RSVD_21",                      BIT(21),	0},
+	{"RSVD_22",                      BIT(22),	0},
+	{"RSVD_23",                      BIT(23),	0},
+	{"SBR16B6_PGD0_PG_STS",          BIT(24),	0},
+	{"PSF0_PGD0_PG_STS",             BIT(25),	0},
+	{"STRC_PGD0_PG_STS",             BIT(26),	0},
+	{"RSVD_27",                      BIT(27),	0},
+	{"DBG_SBR_PGD0_PG_STS",          BIT(28),	0},
+	{"RSVD_29",                      BIT(29),	0},
+	{"OSSE_PGD0_PG_STS",             BIT(30),	1},
+	{"DISP_PGA1_PGD0_PG_STS",        BIT(31),	0},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pcds_d3_status_0_map[] = {
+	{"LPSS_D3_STS",                  BIT(3),	1},
+	{"XDCI_D3_STS",                  BIT(4),	1},
+	{"XHCI_D3_STS",                  BIT(5),	1},
+	{"SPA_D3_STS",                   BIT(12),	0},
+	{"SPB_D3_STS",                   BIT(13),	0},
+	{"ESPISPI_D3_STS",               BIT(18),	0},
+	{"PSTH_D3_STS",                  BIT(21),	0},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pcds_d3_status_1_map[] = {
+	{"OSSE_D3_STS",                  BIT(14),	0},
+	{"GBE_D3_STS",                   BIT(19),	0},
+	{"ITSS_D3_STS",                  BIT(23),	0},
+	{"CNVI_D3_STS",                  BIT(27),	0},
+	{"UFSX2_D3_STS",                 BIT(28),	0},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pcds_d3_status_2_map[] = {
+	{"CSMERTC_D3_STS",               BIT(1),	0},
+	{"CSE_D3_STS",                   BIT(4),	0},
+	{"KVMCC_D3_STS",                 BIT(5),	0},
+	{"USBR0_D3_STS",                 BIT(6),	0},
+	{"ISH_D3_STS",                   BIT(7),	0},
+	{"SMT1_D3_STS",                  BIT(8),	0},
+	{"SMT2_D3_STS",                  BIT(9),	0},
+	{"SMT3_D3_STS",                  BIT(10),	0},
+	{"OSSE_SMT1_D3_STS",             BIT(12),	0},
+	{"CLINK_D3_STS",                 BIT(14),	0},
+	{"PTIO_D3_STS",                  BIT(16),	0},
+	{"PMT_D3_STS",                   BIT(17),	0},
+	{"SMS1_D3_STS",                  BIT(18),	0},
+	{"SMS2_D3_STS",                  BIT(19),	0},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pcds_d3_status_3_map[] = {
+	{"OSSE_SMT2_D3_STS",             BIT(0),	0},
+	{"THC0_D3_STS",                  BIT(14),	1},
+	{"THC1_D3_STS",                  BIT(15),	1},
+	{"OSSE_SMT3_D3_STS",             BIT(19),	0},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pcds_vnn_req_status_0_map[] = {
+	{"LPSS_VNN_REQ_STS",             BIT(3),	0},
+	{"ESPISPI_VNN_REQ_STS",          BIT(18),	1},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pcds_vnn_req_status_1_map[] = {
+	{"NPK_VNN_REQ_STS",              BIT(4),	1},
+	{"DFXAGG_VNN_REQ_STS",           BIT(8),	0},
+	{"EXI_VNN_REQ_STS",              BIT(9),	1},
+	{"OSSE_VNN_REQ_STS",             BIT(14),	1},
+	{"P2D_VNN_REQ_STS",              BIT(18),	1},
+	{"GBE_VNN_REQ_STS",              BIT(19),	0},
+	{"SMB_VNN_REQ_STS",              BIT(25),	1},
+	{"LPC_VNN_REQ_STS",              BIT(26),	0},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pcds_vnn_req_status_2_map[] = {
+	{"CSMERTC_VNN_REQ_STS",          BIT(1),	0},
+	{"CSE_VNN_REQ_STS",              BIT(4),	1},
+	{"ISH_VNN_REQ_STS",              BIT(7),	0},
+	{"SMT1_VNN_REQ_STS",             BIT(8),	0},
+	{"OSSE_SMT1_VNN_REQ_STS",        BIT(12),	1},
+	{"CLINK_VNN_REQ_STS",            BIT(14),	0},
+	{"SMS1_VNN_REQ_STS",             BIT(18),	0},
+	{"SMS2_VNN_REQ_STS",             BIT(19),	0},
+	{"GPIOCOM4_VNN_REQ_STS",         BIT(20),	0},
+	{"GPIOCOM3_VNN_REQ_STS",         BIT(21),	1},
+	{"GPIOCOM1_VNN_REQ_STS",         BIT(23),	1},
+	{"GPIOCOM0_VNN_REQ_STS",         BIT(24),	1},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pcds_vnn_req_status_3_map[] = {
+	{"DISP_SHIM_VNN_REQ_STS",        BIT(4),	1},
+	{"DTS0_VNN_REQ_STS",             BIT(7),	0},
+	{"GPIOCOM5_VNN_REQ_STS",         BIT(11),	0},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pcds_vnn_misc_status_map[] = {
+	{"CPU_C10_REQ_STS",              BIT(0),	0},
+	{"TS_OFF_REQ_STS",               BIT(1),	0},
+	{"PNDE_MET_REQ_STS",             BIT(2),	1},
+	{"PG5_PMA0_REQ_STS",             BIT(3),	1},
+	{"FW_THROTTLE_ALLOWED_REQ_STS",  BIT(4),	0},
+	{"VNN_SOC_REQ_STS",              BIT(6),	1},
+	{"ISH_VNNAON_REQ_STS",           BIT(7),	0},
+	{"D2D_NOC_CFI_QACTIVE_REQ_STS",	 BIT(8),	1},
+	{"D2D_NOC_GPSB_QACTIVE_REQ_STS", BIT(9),	1},
+	{"PLT_GREATER_REQ_STS",          BIT(11),	1},
+	{"ALL_SBR_IDLE_REQ_STS",         BIT(12),	0},
+	{"PMC_IDLE_FB_OCP_REQ_STS",      BIT(13),	0},
+	{"PM_SYNC_STATES_REQ_STS",       BIT(14),	0},
+	{"EA_REQ_STS",                   BIT(15),	0},
+	{"MPHY_CORE_OFF_REQ_STS",        BIT(16),	0},
+	{"BRK_EV_EN_REQ_STS",            BIT(17),	0},
+	{"AUTO_DEMO_EN_REQ_STS",         BIT(18),	0},
+	{"ITSS_CLK_SRC_REQ_STS",         BIT(19),	1},
+	{"ARC_IDLE_REQ_STS",             BIT(21),	0},
+	{"PG5_PMA1_REQ_STS",             BIT(22),	1},
+	{"DG5_PMA0_REQ_STS",             BIT(23),	1},
+	{"ARC_INTERRUPT_WAKE_REQ_STS",   BIT(25),	0},
+	{"D2D_DISP_DDI_QACTIVE_REQ_STS", BIT(26),	1},
+	{"PRE_WAKE0_REQ_STS",            BIT(27),	1},
+	{"PRE_WAKE1_REQ_STS",            BIT(28),	1},
+	{"PRE_WAKE2_REQ_STS",            BIT(29),	1},
+	{"D2D_DISP_EDP_QACTIVE_REQ_STS", BIT(31),	1},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pcds_rsc_status_map[] = {
+	{"CORE",		0,		1},
+	{"Memory",		0,		1},
+	{"PRIM_D2D",		0,		1},
+	{"PSF0",		0,		1},
+	{"SB",			0,		1},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pcds_signal_status_map[] = {
+	{"LSX_Wake0_STS",		 BIT(0),	0},
+	{"LSX_Wake1_STS",		 BIT(1),	0},
+	{"LSX_Wake2_STS",		 BIT(2),	0},
+	{"LSX_Wake3_STS",		 BIT(3),	0},
+	{"LSX_Wake4_STS",		 BIT(4),	0},
+	{"LSX_Wake5_STS",		 BIT(5),	0},
+	{"LSX_Wake6_STS",		 BIT(6),	0},
+	{"LSX_Wake7_STS",		 BIT(7),	0},
+	{"LPSS_Wake0_STS",		 BIT(8),	1},
+	{"LPSS_Wake1_STS",		 BIT(9),	1},
+	{"Int_Timer_SS_Wake0_STS",	 BIT(10),	1},
+	{"Int_Timer_SS_Wake1_STS",	 BIT(11),	1},
+	{"Int_Timer_SS_Wake2_STS",	 BIT(12),	1},
+	{"Int_Timer_SS_Wake3_STS",	 BIT(13),	1},
+	{"Int_Timer_SS_Wake4_STS",	 BIT(14),	1},
+	{"Int_Timer_SS_Wake5_STS",	 BIT(15),	1},
+	{}
+};
+
+static const struct pmc_bit_map *nvl_pcds_lpm_maps[] = {
+	nvl_pcds_clocksource_status_map,
+	nvl_pcds_power_gating_status_0_map,
+	nvl_pcds_power_gating_status_1_map,
+	nvl_pcds_power_gating_status_2_map,
+	nvl_pcds_d3_status_0_map,
+	nvl_pcds_d3_status_1_map,
+	nvl_pcds_d3_status_2_map,
+	nvl_pcds_d3_status_3_map,
+	nvl_pcds_vnn_req_status_0_map,
+	nvl_pcds_vnn_req_status_1_map,
+	nvl_pcds_vnn_req_status_2_map,
+	nvl_pcds_vnn_req_status_3_map,
+	nvl_pcds_vnn_misc_status_map,
+	nvl_pcds_signal_status_map,
+	NULL
+};
+
+static const struct pmc_bit_map *nvl_pcds_blk_maps[] = {
+	nvl_pcds_power_gating_status_0_map,
+	nvl_pcds_power_gating_status_1_map,
+	nvl_pcds_power_gating_status_2_map,
+	nvl_pcds_rsc_status_map,
+	nvl_pcds_vnn_req_status_0_map,
+	nvl_pcds_vnn_req_status_1_map,
+	nvl_pcds_vnn_req_status_2_map,
+	nvl_pcds_vnn_req_status_3_map,
+	nvl_pcds_d3_status_0_map,
+	nvl_pcds_d3_status_1_map,
+	nvl_pcds_d3_status_2_map,
+	nvl_pcds_d3_status_3_map,
+	nvl_pcds_clocksource_status_map,
+	nvl_pcds_vnn_misc_status_map,
+	nvl_pcds_signal_status_map,
+	NULL
+};
+
+static const struct pmc_bit_map nvl_pchs_pfear_map[] = {
+	{"PMC_PGD0",                 BIT(0)},
+	{"FIA_D_PGD0",               BIT(1)},
+	{"SPI_PGD0",                 BIT(2)},
+	{"XHCI_PGD0",                BIT(3)},
+	{"SPA_PGD0",                 BIT(4)},
+	{"SPB_PGD0",                 BIT(5)},
+	{"MPFPW2_PGD0",              BIT(6)},
+	{"GBE_PGD0",                 BIT(7)},
+
+	{"RSVD8",                    BIT(0)},
+	{"PSF3_PGD0",                BIT(1)},
+	{"SBR5_PGD0",                BIT(2)},
+	{"SBR0_PGD0",                BIT(3)},
+	{"RSVD12",                   BIT(4)},
+	{"D2D_DISP_PGD1",            BIT(5)},
+	{"LPSS_PGD0",                BIT(6)},
+	{"LPC_PGD0",                 BIT(7)},
+
+	{"SMB_PGD0",                 BIT(0)},
+	{"ISH_PGD0",                 BIT(1)},
+	{"P2SB_PGD0",                BIT(2)},
+	{"NPK_PGD0",                 BIT(3)},
+	{"D2D_NOC_PGD1",             BIT(4)},
+	{"EAH_PGD0",                 BIT(5)},
+	{"FUSE_PGD0",                BIT(6)},
+	{"SBR8_PGD0",                BIT(7)},
+
+	{"PSF7_PGD0",                BIT(0)},
+	{"OTG_PGD0",                 BIT(1)},
+	{"EXI_PGD0",                 BIT(2)},
+	{"CSE_PGD0",                 BIT(3)},
+	{"CSME_KVM_PGD0",            BIT(4)},
+	{"CSME_PMT_PGD0",            BIT(5)},
+	{"CSME_CLINK_PGD0",          BIT(6)},
+	{"CSME_PTIO_PGD0",           BIT(7)},
+
+	{"CSME_USBR_PGD0",           BIT(0)},
+	{"SBR1_PGD0",                BIT(1)},
+	{"CSME_SMT1_PGD0",           BIT(2)},
+	{"MPFPW1_PGD0",              BIT(3)},
+	{"CSME_SMS2_PGD0",           BIT(4)},
+	{"CSME_SMS_PGD0",            BIT(5)},
+	{"CSME_RTC_PGD0",            BIT(6)},
+	{"CSMEPSF_PGD0",             BIT(7)},
+
+	{"D2D_NOC_PGD0",             BIT(0)},
+	{"ESE_PGD0",                 BIT(1)},
+	{"SBR2_PGD0",                BIT(2)},
+	{"SBR3_PGD0",                BIT(3)},
+	{"SBR4_PGD0",                BIT(4)},
+	{"RSVD45",                   BIT(5)},
+	{"D2D_DISP_PGD0",            BIT(6)},
+	{"PSF1_PGD0",                BIT(7)},
+
+	{"U3FPW1_PGD0",              BIT(0)},
+	{"DMI3FPW_PGD0",             BIT(1)},
+	{"PSF4_PGD0",                BIT(2)},
+	{"CNVI_PGD0",                BIT(3)},
+	{"RSVD52",                   BIT(4)},
+	{"ENDBG_PGD0",               BIT(5)},
+	{"DBC_PGD0",                 BIT(6)},
+	{"SMT4_PGD0",                BIT(7)},
+
+	{"RSVD56",                   BIT(0)},
+	{"NPK_PGD1",                 BIT(1)},
+	{"RSVD58",                   BIT(2)},
+	{"DMI3_PGD0",                BIT(3)},
+	{"RSVD60",                   BIT(4)},
+	{"FIACPCB_D_PGD0",           BIT(5)},
+	{"RSVD62",                   BIT(6)},
+	{"FIA_U_PGD0",               BIT(7)},
+
+	{"FIACPCB_PGS_PGD0",         BIT(0)},
+	{"FIA_PGS_PGD0",             BIT(1)},
+	{"RSVD66",                   BIT(2)},
+	{"FIACPCB_U_PGD0",           BIT(3)},
+	{"TAM_PGD0",                 BIT(4)},
+	{"D2D_NOC_PGD2",             BIT(5)},
+	{"PSF2_PGD0",                BIT(6)},
+	{"THC0_PGD0",                BIT(7)},
+
+	{"THC1_PGD0",                BIT(0)},
+	{"PMC_PGD1",                 BIT(1)},
+	{"SBR9_PGD0",                BIT(2)},
+	{"U3FPW2_PGD0",              BIT(3)},
+	{"RSVD76",                   BIT(4)},
+	{"DBG_PSF_PGD0",             BIT(5)},
+	{"DBG_SBR_PGD0",             BIT(6)},
+	{"SBR6_PGD0",                BIT(7)},
+
+	{"SPC_PGD0",                 BIT(0)},
+	{"ACE_PGD0",                 BIT(1)},
+	{"ACE_PGD1",                 BIT(2)},
+	{"ACE_PGD2",                 BIT(3)},
+	{"ACE_PGD3",                 BIT(4)},
+	{"ACE_PGD4",                 BIT(5)},
+	{"ACE_PGD5",                 BIT(6)},
+	{"ACE_PGD6",                 BIT(7)},
+
+	{"ACE_PGD7",                 BIT(0)},
+	{"ACE_PGD8",                 BIT(1)},
+	{"ACE_PGD9",                 BIT(2)},
+	{"ACE_PGD10",                BIT(3)},
+	{"U3FPW3_PGD0",              BIT(4)},
+	{"SBR7_PGD0",                BIT(5)},
+	{"OSSE_PGD0",                BIT(6)},
+	{"ST_PGD0",                  BIT(7)},
+	{}
+};
+
+static const struct pmc_bit_map *ext_nvl_pchs_pfear_map[] = {
+	nvl_pchs_pfear_map,
+	NULL
+};
+
+static const struct pmc_bit_map nvl_pchs_clocksource_status_map[] = {
+	{"AON2_OFF_STS",                 BIT(0),	1},
+	{"AON3_OFF_STS",                 BIT(1),	0},
+	{"AON4_OFF_STS",                 BIT(2),	0},
+	{"AON2_SPL_OFF_STS",             BIT(3),	0},
+	{"AONL_OFF_STS",                 BIT(4),	0},
+	{"XTAL_LVM_OFF_STS",             BIT(5),	0},
+	{"AON5_OFF_STS",                 BIT(6),	0},
+	{"USB3_PLL_OFF_STS",             BIT(8),	1},
+	{"MAIN_CRO_OFF_STS",             BIT(11),	0},
+	{"MAIN_DIVIDER_OFF_STS",         BIT(12),	1},
+	{"REF_PLL_NON_OC_OFF_STS",       BIT(13),	1},
+	{"DMI_PLL_OFF_STS",              BIT(14),	1},
+	{"PHY_EXT_INJ_OFF_STS",          BIT(15),	1},
+	{"AON6_MCRO_OFF_STS",            BIT(16),	0},
+	{"XTAL_AGGR_OFF_STS",            BIT(17),	0},
+	{"USB2_PLL_OFF_STS",             BIT(18),	1},
+	{"GBE_PLL_OFF_STS",              BIT(21),	1},
+	{"SATA_PLL_OFF_STS",             BIT(22),	1},
+	{"PCIE0_PLL_OFF_STS",            BIT(23),	1},
+	{"PCIE1_PLL_OFF_STS",            BIT(24),	1},
+	{"FABRIC_PLL_OFF_STS",           BIT(25),	1},
+	{"PCIE2_PLL_OFF_STS",            BIT(26),	1},
+	{"REF_PLL_OFF_STS",              BIT(28),	1},
+	{"REF38P4_PLL_OFF_STS",          BIT(31),	1},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pchs_power_gating_status_0_map[] = {
+	{"PMC_PGD0_PG_STS",              BIT(0),	0},
+	{"FIA_D_PGD0_PG_STS",            BIT(1),	0},
+	{"ESPISPI_PGD0_PG_STS",          BIT(2),	0},
+	{"XHCI_PGD0_PG_STS",             BIT(3),	0},
+	{"SPA_PGD0_PG_STS",              BIT(4),	1},
+	{"SPB_PGD0_PG_STS",              BIT(5),	1},
+	{"MPFPW2_PGD0_PG_STS",           BIT(6),	0},
+	{"GBE_PGD0_PG_STS",              BIT(7),	1},
+	{"RSVD_8",                       BIT(8),	0},
+	{"PSF3_PGD0_PG_STS",             BIT(9),	0},
+	{"SBR5_PGD0_PG_STS",             BIT(10),	0},
+	{"SBR0_PGD0_PG_STS",             BIT(11),	0},
+	{"RSVD_12",                      BIT(12),	0},
+	{"D2D_DISP_PGD1_PG_STS",         BIT(13),	0},
+	{"LPSS_PGD0_PG_STS",             BIT(14),	1},
+	{"LPC_PGD0_PG_STS",              BIT(15),	0},
+	{"SMB_PGD0_PG_STS",              BIT(16),	0},
+	{"ISH_PGD0_PG_STS",              BIT(17),	0},
+	{"P2S_PGD0_PG_STS",              BIT(18),	0},
+	{"NPK_PGD0_PG_STS",              BIT(19),	0},
+	{"D2D_NOC_PGD1_PG_STS",          BIT(20),	0},
+	{"EAH_PGD0_PG_STS",              BIT(21),	0},
+	{"FUSE_PGD0_PG_STS",             BIT(22),	0},
+	{"SBR8_PGD0_PG_STS",             BIT(23),	0},
+	{"PSF7_PGD0_PG_STS",             BIT(24),	0},
+	{"XDCI_PGD0_PG_STS",             BIT(25),	1},
+	{"EXI_PGD0_PG_STS",              BIT(26),	0},
+	{"CSE_PGD0_PG_STS",              BIT(27),	1},
+	{"KVMCC_PGD0_PG_STS",            BIT(28),	1},
+	{"PMT_PGD0_PG_STS",              BIT(29),	1},
+	{"CLINK_PGD0_PG_STS",            BIT(30),	1},
+	{"PTIO_PGD0_PG_STS",             BIT(31),	1},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pchs_power_gating_status_1_map[] = {
+	{"USBR0_PGD0_PG_STS",            BIT(0),	1},
+	{"SBR1_PGD0_PG_STS",             BIT(1),	0},
+	{"SMT1_PGD0_PG_STS",             BIT(2),	1},
+	{"MPFPW1_PGD0_PG_STS",           BIT(3),	0},
+	{"SMS2_PGD0_PG_STS",             BIT(4),	1},
+	{"SMS1_PGD0_PG_STS",             BIT(5),	1},
+	{"CSMERTC_PGD0_PG_STS",          BIT(6),	0},
+	{"CSMEPSF_PGD0_PG_STS",          BIT(7),	0},
+	{"D2D_NOC_PGD0_PG_STS",          BIT(8),	0},
+	{"ESE_PGD0_PG_STS",              BIT(9),	1},
+	{"SBR2_PGD0_PG_STS",             BIT(10),	0},
+	{"SBR3_PGD0_PG_STS",             BIT(11),	0},
+	{"SBR4_PGD0_PG_STS",             BIT(12),	0},
+	{"RSVD_13",                      BIT(13),	0},
+	{"D2D_DISP_PGD0_PG_STS",         BIT(14),	0},
+	{"PSF1_PGD0_PG_STS",             BIT(15),	0},
+	{"U3FPW1_PGD0_PG_STS",           BIT(16),	0},
+	{"DMI3FPW_PGD0_PG_STS",          BIT(17),	0},
+	{"PSF4_PGD0_PG_STS",             BIT(18),	0},
+	{"CNVI_PGD0_PG_STS",             BIT(19),	0},
+	{"RSVD_20",                      BIT(20),	0},
+	{"ENDBG_PGD0_PG_STS",            BIT(21),	0},
+	{"DBC_PGD0_PG_STS",              BIT(22),	0},
+	{"SMT4_PGD0_PG_STS",             BIT(23),	1},
+	{"RSVD_24",                      BIT(24),	0},
+	{"NPK_PGD1_PG_STS",              BIT(25),	0},
+	{"RSVD_26",                      BIT(26),	0},
+	{"DMI3_PGD0_PG_STS",             BIT(27),	1},
+	{"RSVD_28",                      BIT(28),	0},
+	{"FIACPCB_D_PGD0_PG_STS",        BIT(29),	0},
+	{"RSVD_30",                      BIT(30),	0},
+	{"FIA_U_PGD0_PG_STS",            BIT(31),	0},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pchs_power_gating_status_2_map[] = {
+	{"FIACPCB_PGS_PGD0_PG_STS",      BIT(0),	0},
+	{"FIA_PGS_PGD0_PG_STS",          BIT(1),	0},
+	{"RSVD_2",                       BIT(2),	0},
+	{"FIACPCB_U_PGD0_PG_STS",        BIT(3),	0},
+	{"TAM_PGD0_PG_STS",              BIT(4),	0},
+	{"D2D_NOC_PGD2_PG_STS",          BIT(5),	0},
+	{"PSF2_PGD0_PG_STS",             BIT(6),	0},
+	{"THC0_PGD0_PG_STS",             BIT(7),	1},
+	{"THC1_PGD0_PG_STS",             BIT(8),	1},
+	{"PMC_PGD1_PG_STS",              BIT(9),	0},
+	{"SBR9_PGA0_PGD0_PG_STS",        BIT(10),	0},
+	{"U3FPW2_PGD0_PG_STS",           BIT(11),	0},
+	{"RSVD_12",                      BIT(12),	0},
+	{"DBG_PSF_PGD0_PG_STS",          BIT(13),	0},
+	{"DBG_SBR_PGD0_PG_STS",          BIT(14),	0},
+	{"SBR6_PGD0_PG_STS",             BIT(15),	0},
+	{"SPC_PGD0_PG_STS",              BIT(16),	1},
+	{"ACE_PGD0_PG_STS",              BIT(17),	0},
+	{"ACE_PGD1_PG_STS",              BIT(18),	0},
+	{"ACE_PGD2_PG_STS",              BIT(19),	0},
+	{"ACE_PGD3_PG_STS",              BIT(20),	0},
+	{"ACE_PGD4_PG_STS",              BIT(21),	0},
+	{"ACE_PGD5_PG_STS",              BIT(22),	0},
+	{"ACE_PGD6_PG_STS",              BIT(23),	0},
+	{"ACE_PGD7_PG_STS",              BIT(24),	0},
+	{"ACE_PGD8_PG_STS",              BIT(25),	0},
+	{"ACE_PGD9_PG_STS",              BIT(26),	0},
+	{"ACE_PGD10_PG_STS",             BIT(27),	0},
+	{"U3FPW3_PGD0_PG_STS",           BIT(28),	0},
+	{"SBR7_PGD0_PG_STS",             BIT(29),	0},
+	{"OSSE_PGD0_PG_STS",             BIT(30),	0},
+	{"SATA_PGD0_PG_STS",             BIT(31),	1},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pchs_d3_status_0_map[] = {
+	{"LPSS_D3_STS",                  BIT(3),	1},
+	{"XDCI_D3_STS",                  BIT(4),	1},
+	{"XHCI_D3_STS",                  BIT(5),	0},
+	{"SPA_D3_STS",                   BIT(12),	0},
+	{"SPB_D3_STS",                   BIT(13),	0},
+	{"SPC_D3_STS",                   BIT(14),	0},
+	{"ESPISPI_D3_STS",               BIT(18),	0},
+	{"SATA_D3_STS",                  BIT(20),	1},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pchs_d3_status_1_map[] = {
+	{"OSSE_D3_STS",                  BIT(6),	0},
+	{"GBE_D3_STS",                   BIT(19),	0},
+	{"ITSS_D3_STS",                  BIT(23),	0},
+	{"P2S_D3_STS",                   BIT(24),	0},
+	{"CNVI_D3_STS",                  BIT(27),	0},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pchs_d3_status_2_map[] = {
+	{"CSMERTC_D3_STS",               BIT(1),	0},
+	{"CSE_D3_STS",                   BIT(4),	0},
+	{"KVMCC_D3_STS",                 BIT(5),	0},
+	{"USBR0_D3_STS",                 BIT(6),	0},
+	{"ISH_D3_STS",                   BIT(7),	0},
+	{"SMT1_D3_STS",                  BIT(8),	0},
+	{"SMT2_D3_STS",                  BIT(9),	0},
+	{"SMT3_D3_STS",                  BIT(10),	0},
+	{"SMT4_D3_STS",                  BIT(11),	0},
+	{"SMT5_D3_STS",                  BIT(12),	0},
+	{"SMT6_D3_STS",                  BIT(13),	0},
+	{"CLINK_D3_STS",                 BIT(14),	0},
+	{"PTIO_D3_STS",                  BIT(16),	0},
+	{"PMT_D3_STS",                   BIT(17),	0},
+	{"SMS1_D3_STS",                  BIT(18),	0},
+	{"SMS2_D3_STS",                  BIT(19),	0},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pchs_d3_status_3_map[] = {
+	{"THC0_D3_STS",                  BIT(14),	0},
+	{"THC1_D3_STS",                  BIT(15),	0},
+	{"ACE_D3_STS",                   BIT(23),	0},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pchs_vnn_req_status_1_map[] = {
+	{"NPK_VNN_REQ_STS",              BIT(4),	0},
+	{"OSSE_VNN_REQ_STS",             BIT(6),	0},
+	{"DFXAGG_VNN_REQ_STS",           BIT(8),	0},
+	{"EXI_VNN_REQ_STS",              BIT(9),	0},
+	{"GBE_VNN_REQ_STS",              BIT(19),	0},
+	{"SMB_VNN_REQ_STS",              BIT(25),	0},
+	{"LPC_VNN_REQ_STS",              BIT(26),	0},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pchs_vnn_req_status_2_map[] = {
+	{"CSMERTC_VNN_REQ_STS",          BIT(1),	0},
+	{"CSE_VNN_REQ_STS",              BIT(4),	0},
+	{"ISH_VNN_REQ_STS",              BIT(7),	0},
+	{"SMT1_VNN_REQ_STS",             BIT(8),	0},
+	{"SMT4_VNN_REQ_STS",             BIT(11),	0},
+	{"CLINK_VNN_REQ_STS",            BIT(14),	0},
+	{"SMS1_VNN_REQ_STS",             BIT(18),	0},
+	{"SMS2_VNN_REQ_STS",             BIT(19),	0},
+	{"GPIOCOM4_VNN_REQ_STS",         BIT(20),	0},
+	{"GPIOCOM3_VNN_REQ_STS",         BIT(21),	0},
+	{"GPIOCOM2_VNN_REQ_STS",         BIT(22),	0},
+	{"GPIOCOM1_VNN_REQ_STS",         BIT(23),	0},
+	{"GPIOCOM0_VNN_REQ_STS",         BIT(24),	0},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pchs_vnn_misc_status_map[] = {
+	{"CPU_C10_REQ_STS",              BIT(0),	0},
+	{"TS_OFF_REQ_STS",               BIT(1),	0},
+	{"PNDE_MET_REQ_STS",             BIT(2),	1},
+	{"PG5_PMA0_GVNN_REQ_STS",        BIT(3),	1},
+	{"FW_THROTTLE_ALLOWED_REQ_STS",  BIT(4),	0},
+	{"DMI_IN_L1_REQ_STS",            BIT(6),	0},
+	{"ISH_VNNAON_REQ_STS",           BIT(7),	0},
+	{"PLT_GREATER_REQ_STS",          BIT(11),	1},
+	{"ALL_SBR_IDLE_REQ_STS",         BIT(12),	0},
+	{"PMC_IDLE_FB_OCP_REQ_STS",      BIT(13),	0},
+	{"PM_SYNC_STATES_REQ_STS",       BIT(14),	0},
+	{"EA_REQ_STS",                   BIT(15),	0},
+	{"DMI_CLKREQ_B_REQ_STS",         BIT(16),	0},
+	{"BRK_EV_EN_REQ_STS",            BIT(17),	0},
+	{"AUTO_DEMO_EN_REQ_STS",         BIT(18),	0},
+	{"ITSS_CLK_SRC_REQ_STS",         BIT(19),	1},
+	{"ARC_IDLE_REQ_STS",             BIT(21),	0},
+	{"PG5_PMA1_GVNN_REQ_STS",        BIT(22),	1},
+	{"FIA_DEEP_PM_REQ_STS",          BIT(23),	0},
+	{"XDCI_ATTACHED_REQ_STS",        BIT(24),	0},
+	{"ARC_INTERRUPT_WAKE_REQ_STS",   BIT(25),	0},
+	{"PRE_WAKE0_REQ_STS",            BIT(27),	1},
+	{"PRE_WAKE1_REQ_STS",            BIT(28),	1},
+	{"PRE_WAKE2_EN_REQ_STS",         BIT(29),	0},
+	{"PG5_PMA2_GVNN_REQ_STS",        BIT(30),	1},
+	{}
+};
+
+static const struct pmc_bit_map nvl_pchs_rsc_status_map[] = {
+	{"Memory",		0,		1},
+	{"Memory_NS",		0,		1},
+	{"PSF1",		0,		1},
+	{"PSF2",		0,		1},
+	{"PSF3",		0,		1},
+	{"REF_PLL",		0,		1},
+	{"SB",			0,		1},
+	{}
+};
+
+static const struct pmc_bit_map *nvl_pchs_lpm_maps[] = {
+	nvl_pchs_clocksource_status_map,
+	nvl_pchs_power_gating_status_0_map,
+	nvl_pchs_power_gating_status_1_map,
+	nvl_pchs_power_gating_status_2_map,
+	nvl_pchs_d3_status_0_map,
+	nvl_pchs_d3_status_1_map,
+	nvl_pchs_d3_status_2_map,
+	nvl_pchs_d3_status_3_map,
+	nvl_pcds_vnn_req_status_0_map,
+	nvl_pchs_vnn_req_status_1_map,
+	nvl_pchs_vnn_req_status_2_map,
+	nvl_pcdh_vnn_req_status_3_map,
+	nvl_pchs_vnn_misc_status_map,
+	ptl_pcdp_signal_status_map,
+	NULL
+};
+
+static const struct pmc_bit_map *nvl_pchs_blk_maps[] = {
+	nvl_pchs_power_gating_status_0_map,
+	nvl_pchs_power_gating_status_1_map,
+	nvl_pchs_power_gating_status_2_map,
+	nvl_pchs_rsc_status_map,
+	nvl_pchs_d3_status_0_map,
+	nvl_pchs_clocksource_status_map,
+	nvl_pchs_vnn_misc_status_map,
+	NULL
+};
+
+static const struct pmc_reg_map nvl_pcdh_reg_map = {
+	.pfear_sts = ext_nvl_pcdh_pfear_map,
+	.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
+	.slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
+	.ltr_show_sts = ptl_pcdp_ltr_show_map,
+	.msr_sts = msr_map,
+	.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
+	.regmap_length = NVL_PCDH_PMC_MMIO_REG_LEN,
+	.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
+	.ppfear_buckets = NVL_PCDH_PPFEAR_NUM_ENTRIES,
+	.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
+	.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
+	.lpm_num_maps = NVL_LPM_NUM_MAPS,
+	.ltr_ignore_max = LNL_NUM_IP_IGN_ALLOWED,
+	.lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
+	.etr3_offset = ETR3_OFFSET,
+	.lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET,
+	.lpm_priority_offset = NVL_LPM_PRI_OFFSET,
+	.lpm_en_offset = NVL_LPM_EN_OFFSET,
+	.lpm_residency_offset = NVL_LPM_RESIDENCY_OFFSET,
+	.lpm_sts = nvl_pcdh_lpm_maps,
+	.lpm_status_offset = MTL_LPM_STATUS_OFFSET,
+	.lpm_live_status_offset = NVL_LPM_LIVE_STATUS_OFFSET,
+	.s0ix_blocker_maps = nvl_pcdh_blk_maps,
+	.s0ix_blocker_offset = LNL_S0IX_BLOCKER_OFFSET,
+	.num_s0ix_blocker = NVL_PCDH_NUM_S0IX_BLOCKER,
+	.blocker_req_offset = NVL_PCDH_BLK_REQ_OFFSET,
+	.lpm_req_guid = PCDH_LPM_REQ_GUID,
+};
+
+static const struct pmc_reg_map nvl_pcds_reg_map = {
+	.pfear_sts = ext_nvl_pcds_pfear_map,
+	.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
+	.slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
+	.ltr_show_sts = nvl_pcds_ltr_show_map,
+	.msr_sts = msr_map,
+	.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
+	.regmap_length = NVL_PCDS_PMC_MMIO_REG_LEN,
+	.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
+	.ppfear_buckets = LNL_PPFEAR_NUM_ENTRIES,
+	.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
+	.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
+	.lpm_num_maps = PTL_LPM_NUM_MAPS,
+	.ltr_ignore_max = LNL_NUM_IP_IGN_ALLOWED,
+	.lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
+	.etr3_offset = ETR3_OFFSET,
+	.lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET,
+	.lpm_priority_offset = MTL_LPM_PRI_OFFSET,
+	.lpm_en_offset = MTL_LPM_EN_OFFSET,
+	.lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET,
+	.lpm_sts = nvl_pcds_lpm_maps,
+	.lpm_status_offset = MTL_LPM_STATUS_OFFSET,
+	.lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,
+	.s0ix_blocker_maps = nvl_pcds_blk_maps,
+	.s0ix_blocker_offset = LNL_S0IX_BLOCKER_OFFSET,
+	.num_s0ix_blocker = NVL_PCDS_NUM_S0IX_BLOCKER,
+	.lpm_req_guid = PCDS_LPM_REQ_GUID,
+	.blocker_req_offset = NVL_PCDS_BLK_REQ_OFFSET,
+};
+
+static const struct pmc_reg_map nvl_pchs_reg_map = {
+	.pfear_sts = ext_nvl_pchs_pfear_map,
+	.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
+	.slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
+	.ltr_show_sts = ptl_pcdp_ltr_show_map,
+	.msr_sts = msr_map,
+	.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
+	.regmap_length = NVL_PCHS_PMC_MMIO_REG_LEN,
+	.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
+	.ppfear_buckets = LNL_PPFEAR_NUM_ENTRIES,
+	.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
+	.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
+	.lpm_num_maps = PTL_LPM_NUM_MAPS,
+	.ltr_ignore_max = LNL_NUM_IP_IGN_ALLOWED,
+	.lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
+	.etr3_offset = ETR3_OFFSET,
+	.lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET,
+	.lpm_priority_offset = MTL_LPM_PRI_OFFSET,
+	.lpm_en_offset = MTL_LPM_EN_OFFSET,
+	.lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET,
+	.lpm_sts = nvl_pchs_lpm_maps,
+	.lpm_status_offset = MTL_LPM_STATUS_OFFSET,
+	.lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,
+	.s0ix_blocker_maps = nvl_pchs_blk_maps,
+	.s0ix_blocker_offset = LNL_S0IX_BLOCKER_OFFSET,
+	.num_s0ix_blocker = NVL_PCHS_NUM_S0IX_BLOCKER,
+	.blocker_req_offset = NVL_PCHS_BLK_REQ_OFFSET,
+	.lpm_req_guid = PCHS_LPM_REQ_GUID,
+};
+
+static struct pmc_info nvl_pmc_info_list[] = {
+	{
+		.devid	= PMC_DEVID_NVL_PCDH,
+		.map	= &nvl_pcdh_reg_map,
+	},
+	{
+		.devid  = PMC_DEVID_NVL_PCDS,
+		.map    = &nvl_pcds_reg_map,
+	},
+	{
+		.devid  = PMC_DEVID_NVL_PCHS,
+		.map    = &nvl_pchs_reg_map,
+	},
+	{}
+};
+
+const char *nvl_ltr_block_counter_arr[] = {
+	"PKGC_PREVENT_LTR_IADOMAIN",
+	"PKGC_PREVENT_LTR_GDIE",
+	"PKGC_PREVENT_LTR_PCH",
+	"PKGC_PREVENT_LTR_DISPLAY",
+	"PKGC_PREVENT_LTR_IPU",
+	NULL
+};
+
+const char *nvl_pkgc_blocker_residency[] = {
+	"PKGC_BLOCK_RESIDENCY_INVALID",
+	"PKGC_BLOCK_RESIDENCY_MISC",
+	"PKGC_BLOCK_RESIDENCY_CDIE_MISC",
+	"PKGC_BLOCK_RESIDENCY_MEDIA_MISC",
+	"PKGC_BLOCK_RESIDENCY_GT_MISC",
+	"PKGC_BLOCK_RESIDENCY_HUBATOM_MISC",
+	"PKGC_BLOCK_RESIDENCY_IPU_BUSY",
+	"PKGC_BLOCK_RESIDENCY_IPU_LTR",
+	"PKGC_BLOCK_RESIDENCY_IPU_TIMER",
+	"PKGC_BLOCK_RESIDENCY_DISP_BUSY",
+	"PKGC_BLOCK_RESIDENCY_DISP_LTR",
+	"PKGC_BLOCK_RESIDENCY_DISP_TIMER",
+	"PKGC_BLOCK_RESIDENCY_VPU_BUSY",
+	"PKGC_BLOCK_RESIDENCY_VPU_TIMER",
+	"PKGC_BLOCK_RESIDENCY_PMC_BUSY",
+	"PKGC_BLOCK_RESIDENCY_PMC_LTR",
+	"PKGC_BLOCK_RESIDENCY_PMC_TIMER",
+	"PKGC_BLOCK_RESIDENCY_HUBATOM_ARAT",
+	"PKGC_BLOCK_RESIDENCY_CDIE0_ARAT",
+	"PKGC_BLOCK_RESIDENCY_CDIE1_ARAT",
+	"PKGC_BLOCK_RESIDENCY_GT_ARAT",
+	"PKGC_BLOCK_RESIDENCY_MEDIA_ARAT",
+	"PKGC_BLOCK_RESIDENCY_DEMOTION",
+	"PKGC_BLOCK_RESIDENCY_THERMALS",
+	"PKGC_BLOCK_RESIDENCY_SNCU",
+	"PKGC_BLOCK_RESIDENCY_SVTU",
+	"PKGC_BLOCK_RESIDENCY_IAA",
+	"PKGC_BLOCK_RESIDENCY_IOC",
+	NULL,
+};
+
+static u8 nvl_pmc_list[] = {PMC_IDX_MAIN, PMC_IDX_PCH, PMC_IDX_MAX};
+static u8 nvl_h_pmc_list[] = {PMC_IDX_MAIN, PMC_IDX_PCH, PMC_IDX_MAX};
+
+#define NVL_NPU_PCI_DEV                0xd71d
+
+/*
+ * Set power state of select devices that do not have drivers to D3
+ * so that they do not block Package C entry.
+ */
+static void nvl_d3_fixup(void)
+{
+	pmc_core_set_device_d3(NVL_NPU_PCI_DEV);
+}
+
+static int nvl_resume(struct pmc_dev *pmcdev)
+{
+	nvl_d3_fixup();
+	return cnl_resume(pmcdev);
+}
+
+static int nvl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info)
+{
+	nvl_d3_fixup();
+	return generic_core_init(pmcdev, pmc_dev_info);
+}
+
+static u32 NVL_PMT_DMU_GUIDS[] = {NVL_PMT_DMU_GUID, 0x0};
+struct pmc_dev_info nvl_s_pmc_dev = {
+	.pmc_list = nvl_pmc_list,
+	.regmap_list = nvl_pmc_info_list,
+	.map = &nvl_pcds_reg_map,
+	.sub_req_show = &pmc_core_substate_blk_req_fops,
+	.suspend = cnl_suspend,
+	.resume = nvl_resume,
+	.init = nvl_core_init,
+	.sub_req = pmc_core_pmt_get_blk_sub_req,
+	.dmu_guids = NVL_PMT_DMU_GUIDS,
+	.pc_guid = NVL_PMT_PC_GUID,
+	.pkgc_ltr_blocker_offset = NVL_LTR_BLK_OFFSET,
+	.pkgc_ltr_blocker_counters = nvl_ltr_block_counter_arr,
+	.pkgc_blocker_offset = NVL_PKGC_BLK_OFFSET,
+	.pkgc_blocker_counters = nvl_pkgc_blocker_residency,
+	.ssram_hidden = false,
+	.die_c6_offset = NVL_PMT_DMU_DIE_C6_OFFSET,
+};
+
+struct pmc_dev_info nvl_h_pmc_dev = {
+	.pmc_list = nvl_h_pmc_list,
+	.regmap_list = nvl_pmc_info_list,
+	.map = &nvl_pcdh_reg_map,
+	.sub_req_show = &pmc_core_substate_blk_req_fops,
+	.suspend = cnl_suspend,
+	.resume = nvl_resume,
+	.init = nvl_core_init,
+	.sub_req = pmc_core_pmt_get_blk_sub_req,
+	.dmu_guids = NVL_PMT_DMU_GUIDS,
+	.pc_guid = NVL_PMT_PC_GUID,
+	.pkgc_ltr_blocker_offset = NVL_LTR_BLK_OFFSET,
+	.pkgc_ltr_blocker_counters = nvl_ltr_block_counter_arr,
+	.pkgc_blocker_offset = NVL_PKGC_BLK_OFFSET,
+	.pkgc_blocker_counters = nvl_pkgc_blocker_residency,
+	.ssram_hidden = false,
+	.die_c6_offset = NVL_PMT_DMU_DIE_C6_OFFSET,
+};
diff --git a/drivers/platform/x86/intel/pmc/ptl.c b/drivers/platform/x86/intel/pmc/ptl.c
index 538ca5ae2e9ec..d39ae842ddd57 100644
--- a/drivers/platform/x86/intel/pmc/ptl.c
+++ b/drivers/platform/x86/intel/pmc/ptl.c
@@ -137,7 +137,7 @@ static const struct pmc_bit_map *ext_ptl_pcdp_pfear_map[] = {
 	NULL
 };
 
-static const struct pmc_bit_map ptl_pcdp_ltr_show_map[] = {
+const struct pmc_bit_map ptl_pcdp_ltr_show_map[] = {
 	{"SOUTHPORT_A",		CNP_PMC_LTR_SPA},
 	{"SOUTHPORT_B",		CNP_PMC_LTR_SPB},
 	{"SATA",		CNP_PMC_LTR_SATA},
-- 
2.43.0

Re: [PATCH 6/6] platform/x86/intel/pmc: Add Nova Lake support to intel_pmc_core driver

[Ilpo Järvinen]

On Mon, 2 Mar 2026, Xi Pardee wrote:

> Add Nova Lake support in intel_pmc_core driver
> 
> Signed-off-by: Xi Pardee <xi.pardee@linux.intel.com>
> ---
>  drivers/platform/x86/intel/pmc/Makefile |    2 +-
>  drivers/platform/x86/intel/pmc/core.c   |    2 +
>  drivers/platform/x86/intel/pmc/core.h   |   31 +
>  drivers/platform/x86/intel/pmc/nvl.c    | 1537 +++++++++++++++++++++++
>  drivers/platform/x86/intel/pmc/ptl.c    |    2 +-
>  5 files changed, 1572 insertions(+), 2 deletions(-)
>  create mode 100644 drivers/platform/x86/intel/pmc/nvl.c
> 
> diff --git a/drivers/platform/x86/intel/pmc/Makefile b/drivers/platform/x86/intel/pmc/Makefile
> index bb960c8721d77..53e4a60dcf3cc 100644
> --- a/drivers/platform/x86/intel/pmc/Makefile
> +++ b/drivers/platform/x86/intel/pmc/Makefile
> @@ -4,7 +4,7 @@
>  #
>  
>  intel_pmc_core-y			:= core.o spt.o cnp.o icl.o \
> -					   tgl.o adl.o mtl.o arl.o lnl.o ptl.o wcl.o
> +					   tgl.o adl.o mtl.o arl.o lnl.o ptl.o wcl.o nvl.o

Perhaps split to three lines as this starts to grow a bit long.

>  obj-$(CONFIG_INTEL_PMC_CORE)		+= intel_pmc_core.o
>  intel_pmc_core_pltdrv-y			:= pltdrv.o
>  obj-$(CONFIG_INTEL_PMC_CORE)		+= intel_pmc_core_pltdrv.o
> diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c
> index 85fff5e3abe0d..81e1f55bb7916 100644
> --- a/drivers/platform/x86/intel/pmc/core.c
> +++ b/drivers/platform/x86/intel/pmc/core.c
> @@ -1859,6 +1859,8 @@ static const struct x86_cpu_id intel_pmc_core_ids[] = {
>  	X86_MATCH_VFM(INTEL_LUNARLAKE_M,	&lnl_pmc_dev),
>  	X86_MATCH_VFM(INTEL_PANTHERLAKE_L,	&ptl_pmc_dev),
>  	X86_MATCH_VFM(INTEL_WILDCATLAKE_L,	&wcl_pmc_dev),
> +	X86_MATCH_VFM(INTEL_NOVALAKE,		&nvl_s_pmc_dev),
> +	X86_MATCH_VFM(INTEL_NOVALAKE_L,		&nvl_h_pmc_dev),
>  	{}
>  };
>  
> diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h
> index c4984e44f7b80..ccfde1dc10d30 100644
> --- a/drivers/platform/x86/intel/pmc/core.h
> +++ b/drivers/platform/x86/intel/pmc/core.h
> @@ -307,6 +307,29 @@ enum ppfear_regs {
>  #define WCL_NUM_S0IX_BLOCKER			94
>  #define WCL_BLK_REQ_OFFSET			50
>  
> +/* Nova Lake */
> +#define NVL_PCDH_PPFEAR_NUM_ENTRIES		13
> +#define NVL_PCDH_PMC_MMIO_REG_LEN		0x363C
> +#define NVL_PCDS_PMC_MMIO_REG_LEN		0x3118
> +#define NVL_PCHS_PMC_MMIO_REG_LEN		0x30D8
> +#define NVL_LPM_PRI_OFFSET			0x17A4
> +#define NVL_LPM_EN_OFFSET			0x17A0
> +#define NVL_LPM_RESIDENCY_OFFSET		0x17A8
> +#define NVL_LPM_LIVE_STATUS_OFFSET		0x1760
> +#define NVL_LPM_NUM_MAPS			15
> +#define NVL_PCDH_NUM_S0IX_BLOCKER		107
> +#define NVL_PCDS_NUM_S0IX_BLOCKER		71
> +#define NVL_PCHS_NUM_S0IX_BLOCKER		54
> +#define NVL_PCDS_PMC_LTR_RESERVED		0x1BAC
> +#define NVL_PCDH_BLK_REQ_OFFSET			53
> +#define NVL_PCDS_BLK_REQ_OFFSET			18
> +#define NVL_PCHS_BLK_REQ_OFFSET			46
> +#define NVL_PMT_PC_GUID				0x13000101
> +#define NVL_PMT_DMU_GUID			0x1A000101

It would be nice to progress towards consistent capitalization of hex 
letters. This patch isn't even consistent within itself. My preference is 
lowercase as it avoids the LONG CAPS BLOCK effect that is pretty imposing.

> +#define NVL_LTR_BLK_OFFSET			64
> +#define NVL_PKGC_BLK_OFFSET			4
> +#define NVL_PMT_DMU_DIE_C6_OFFSET		25
> +
>  /* SSRAM PMC Device ID */
>  /* LNL */
>  #define PMC_DEVID_LNL_SOCM	0xa87f
> @@ -329,6 +352,11 @@ enum ppfear_regs {
>  #define PMC_DEVID_MTL_IOEP	0x7ecf
>  #define PMC_DEVID_MTL_IOEM	0x7ebf
>  
> +/* NVL */
> +#define PMC_DEVID_NVL_PCDH	0xd37e
> +#define PMC_DEVID_NVL_PCDS	0xd47e
> +#define PMC_DEVID_NVL_PCHS	0x6e27
> +
>  extern const char *pmc_lpm_modes[];
>  
>  struct pmc_bit_map {
> @@ -556,6 +584,7 @@ extern const struct pmc_reg_map mtl_ioep_reg_map;
>  extern const struct pmc_bit_map ptl_pcdp_clocksource_status_map[];
>  extern const struct pmc_bit_map ptl_pcdp_vnn_req_status_3_map[];
>  extern const struct pmc_bit_map ptl_pcdp_signal_status_map[];
> +extern const struct pmc_bit_map ptl_pcdp_ltr_show_map[];
>  
>  void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev);
>  int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value, int ignore);
> @@ -579,6 +608,8 @@ extern struct pmc_dev_info arl_h_pmc_dev;
>  extern struct pmc_dev_info lnl_pmc_dev;
>  extern struct pmc_dev_info ptl_pmc_dev;
>  extern struct pmc_dev_info wcl_pmc_dev;
> +extern struct pmc_dev_info nvl_s_pmc_dev;
> +extern struct pmc_dev_info nvl_h_pmc_dev;
>  
>  void cnl_suspend(struct pmc_dev *pmcdev);
>  int cnl_resume(struct pmc_dev *pmcdev);
> diff --git a/drivers/platform/x86/intel/pmc/nvl.c b/drivers/platform/x86/intel/pmc/nvl.c
> new file mode 100644
> index 0000000000000..ae338a4de2257
> --- /dev/null
> +++ b/drivers/platform/x86/intel/pmc/nvl.c
> @@ -0,0 +1,1537 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * This file contains platform specific structure definitions
> + * and init function used by Nova Lake PCH.
> + *
> + * Copyright (c) 2026, Intel Corporation.
> + */
> +
> +#include <linux/pci.h>
> +
> +#include "core.h"
> +
> +/* PMC SSRAM PMT Telemetry GUIDS */
> +#define PCDH_LPM_REQ_GUID 0x01093101
> +#define PCHS_LPM_REQ_GUID 0x01092101
> +#define PCDS_LPM_REQ_GUID 0x01091102
> +
> +/*
> + * Die Mapping to Product.
> + * Product PCDDie PCHDie
> + * NVL-H   PCD-H  None
> + * NVL-S   PCD-S  PCH-S
> + */
> +
> +static const struct pmc_bit_map nvl_pcdh_pfear_map[] = {
> +	{"PMC_PGD0",                 BIT(0)},
> +	{"FUSE_OSSE_PGD0",           BIT(1)},
> +	{"SPI_PGD0",                 BIT(2)},
> +	{"XHCI_PGD0",                BIT(3)},
> +	{"SPA_PGD0",                 BIT(4)},
> +	{"SPB_PGD0",                 BIT(5)},
> +	{"MPFPW2_PGD0",              BIT(6)},
> +	{"GBE_PGD0",                 BIT(7)},
> +
> +	{"SBR16B20_PGD0",            BIT(0)},
> +	{"DBG_SBR_PGD0",             BIT(1)},
> +	{"SBR16B7_PGD0",             BIT(2)},
> +	{"STRC_PGD0",                BIT(3)},
> +	{"SBR16B8_PGD0",             BIT(4)},
> +	{"D2D_DISP_PGD1",            BIT(5)},
> +	{"LPSS_PGD0",                BIT(6)},
> +	{"LPC_PGD0",                 BIT(7)},
> +
> +	{"SMB_PGD0",                 BIT(0)},
> +	{"ISH_PGD0",                 BIT(1)},
> +	{"SBR16B2_PGD0",             BIT(2)},
> +	{"NPK_PGD0",                 BIT(3)},
> +	{"D2D_NOC_PGD1",             BIT(4)},
> +	{"DBG_SBR16B_PGD0",          BIT(5)},
> +	{"FUSE_PGD0",                BIT(6)},
> +	{"SBR16B0_PGD0",             BIT(7)},
> +
> +	{"P2SB0_PGD0",               BIT(0)},
> +	{"OTG_PGD0",                 BIT(1)},
> +	{"EXI_PGD0",                 BIT(2)},
> +	{"CSE_PGD0",                 BIT(3)},
> +	{"CSME_KVM_PGD0",            BIT(4)},
> +	{"CSME_PMT_PGD0",            BIT(5)},
> +	{"CSME_CLINK_PGD0",          BIT(6)},
> +	{"SBR16B21_PGD0",            BIT(7)},
> +
> +	{"CSME_USBR_PGD0",           BIT(0)},
> +	{"SBR16B22_PGD0",            BIT(1)},
> +	{"CSME_SMT1_PGD0",           BIT(2)},
> +	{"MPFPW1_PGD0",              BIT(3)},
> +	{"CSME_SMS2_PGD0",           BIT(4)},
> +	{"CSME_SMS_PGD0",            BIT(5)},
> +	{"CSME_RTC_PGD0",            BIT(6)},
> +	{"CSMEPSF_PGD0",             BIT(7)},
> +
> +	{"D2D_NOC_PGD0",             BIT(0)},
> +	{"ESE_PGD0",                 BIT(1)},
> +	{"SBR16B6_PGD0",             BIT(2)},
> +	{"P2SB1_PGD0",               BIT(3)},
> +	{"SBR16B3_PGD0",             BIT(4)},
> +	{"OSSE_SMT1_PGD0",           BIT(5)},
> +	{"D2D_DISP_PGD0",            BIT(6)},
> +	{"SNPS_USB2_A_PGD0",         BIT(7)},
> +
> +	{"U3FPW1_PGD0",              BIT(0)},
> +	{"FIA_X_PGD0",               BIT(1)},
> +	{"PSF4_PGD0",                BIT(2)},
> +	{"CNVI_PGD0",                BIT(3)},
> +	{"UFSX2_PGD0",               BIT(4)},
> +	{"ENDBG_PGD0",               BIT(5)},
> +	{"DBC_PGD0",                 BIT(6)},
> +	{"FIA_PG_PGD0",              BIT(7)},
> +
> +	{"D2D_IPU_PGD0",             BIT(0)},
> +	{"NPK_PGD1",                 BIT(1)},
> +	{"FIACPCB_X_PGD0",           BIT(2)},
> +	{"SBR8B4_PGD0",              BIT(3)},
> +	{"DBG_PSF_PGD0",             BIT(4)},
> +	{"PSF6_PGD0",                BIT(5)},
> +	{"UFSPW1_PGD0",              BIT(6)},
> +	{"FIA_U_PGD0",               BIT(7)},
> +
> +	{"PSF8_PGD0",                BIT(0)},
> +	{"SBR16B9_PGD0",             BIT(1)},
> +	{"PSF0_PGD0",                BIT(2)},
> +	{"FIACPCB_U_PGD0",           BIT(3)},
> +	{"TAM_PGD0",                 BIT(4)},
> +	{"D2D_NOC_PGD2",             BIT(5)},
> +	{"SBR8B2_PGD0",              BIT(6)},
> +	{"THC0_PGD0",                BIT(7)},
> +
> +	{"THC1_PGD0",                BIT(0)},
> +	{"PMC_PGD1",                 BIT(1)},
> +	{"DISP_PGA1_PGD0",           BIT(2)},
> +	{"TCSS_PGD0",                BIT(3)},
> +	{"DISP_PGA_PGD0",            BIT(4)},
> +	{"SBR16B1_PGD0",             BIT(5)},
> +	{"SBRG_PGD0",                BIT(6)},
> +	{"PSF5_PGD0",                BIT(7)},
> +
> +	{"SBR8B3_PGD0",              BIT(0)},
> +	{"ACE_PGD0",                 BIT(1)},
> +	{"ACE_PGD1",                 BIT(2)},
> +	{"ACE_PGD2",                 BIT(3)},
> +	{"ACE_PGD3",                 BIT(4)},
> +	{"ACE_PGD4",                 BIT(5)},
> +	{"ACE_PGD5",                 BIT(6)},
> +	{"ACE_PGD6",                 BIT(7)},
> +
> +	{"ACE_PGD7",                 BIT(0)},
> +	{"ACE_PGD8",                 BIT(1)},
> +	{"ACE_PGD9",                 BIT(2)},
> +	{"ACE_PGD10",                BIT(3)},
> +	{"FIACPCB_PG_PGD0",          BIT(4)},
> +	{"SNPS_USB2_B_PGD0",         BIT(5)},
> +	{"OSSE_PGD0",                BIT(6)},
> +	{"SBR8B0_PGD0",              BIT(7)},
> +
> +	{"SBR16B4_PGD0",             BIT(0)},
> +	{"CSME_PTIO_PGD0",           BIT(1)},
> +	{}
> +};
> +
> +static const struct pmc_bit_map *ext_nvl_pcdh_pfear_map[] = {
> +	nvl_pcdh_pfear_map,
> +	NULL
> +};
> +
> +const struct pmc_bit_map nvl_pcdh_clocksource_status_map[] = {
> +	{"AON2_OFF_STS",                 BIT(0),	1},
> +	{"AON3_OFF_STS",                 BIT(1),	0},
> +	{"AON4_OFF_STS",                 BIT(2),	1},
> +	{"AON5_OFF_STS",                 BIT(3),	1},
> +	{"AON1_OFF_STS",                 BIT(4),	0},
> +	{"XTAL_LVM_OFF_STS",             BIT(5),	0},
> +	{"MPFPW1_0_PLL_OFF_STS",         BIT(6),	1},
> +	{"D2D_PLL_OFF_STS",              BIT(7),	1},
> +	{"USB3_PLL_OFF_STS",             BIT(8),	1},
> +	{"AON3_SPL_OFF_STS",             BIT(9),	1},
> +	{"MPFPW2_0_PLL_OFF_STS",         BIT(12),	1},
> +	{"XTAL_AGGR_OFF_STS",            BIT(17),	1},
> +	{"USB2_PLL_OFF_STS",             BIT(18),	0},
> +	{"DDI2_PLL_OFF_STS",             BIT(19),	1},
> +	{"SE_TCSS_PLL_OFF_STS",          BIT(20),	1},
> +	{"DDI_PLL_OFF_STS",              BIT(21),	1},
> +	{"FILTER_PLL_OFF_STS",           BIT(22),	1},
> +	{"ACE_PLL_OFF_STS",              BIT(24),	0},
> +	{"FABRIC_PLL_OFF_STS",           BIT(25),	1},
> +	{"SOC_PLL_OFF_STS",              BIT(26),	1},
> +	{"REF_PLL_OFF_STS",              BIT(28),	1},
> +	{"IMG_PLL_OFF_STS",              BIT(29),	1},
> +	{"GENLOCK_FILTER_PLL_OFF_STS",   BIT(30),	1},
> +	{"RTC_PLL_OFF_STS",              BIT(31),	0},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pcdh_power_gating_status_0_map[] = {
> +	{"PMC_PGD0_PG_STS",              BIT(0),	0},
> +	{"FUSE_OSSE_PGD0_PG_STS",	 BIT(1),	0},
> +	{"ESPISPI_PGD0_PG_STS",          BIT(2),	0},
> +	{"XHCI_PGD0_PG_STS",             BIT(3),	1},
> +	{"SPA_PGD0_PG_STS",              BIT(4),	1},
> +	{"SPB_PGD0_PG_STS",              BIT(5),	1},
> +	{"MPFPW2_PGD0_PG_STS",           BIT(6),	0},
> +	{"GBE_PGD0_PG_STS",              BIT(7),	1},
> +	{"SBR16B20_PGD0_PG_STS",         BIT(8),	0},
> +	{"DBG_PGD0_PG_STS",              BIT(9),	0},
> +	{"SBR16B7_PGD0_PG_STS",          BIT(10),	0},
> +	{"STRC_PGD0_PG_STS",             BIT(11),	0},
> +	{"SBR16B8_PGD0_PG_STS",          BIT(12),	0},
> +	{"D2D_DISP_PGD1_PG_STS",         BIT(13),	1},
> +	{"LPSS_PGD0_PG_STS",             BIT(14),	1},
> +	{"LPC_PGD0_PG_STS",              BIT(15),	0},
> +	{"SMB_PGD0_PG_STS",              BIT(16),	0},
> +	{"ISH_PGD0_PG_STS",              BIT(17),	0},
> +	{"SBR16B2_PGD0_PG_STS",          BIT(18),	0},
> +	{"NPK_PGD0_PG_STS",              BIT(19),	0},
> +	{"D2D_NOC_PGD1_PG_STS",          BIT(20),	1},
> +	{"DBG_SBR16B_PGD0_PG_STS",       BIT(21),	0},
> +	{"FUSE_PGD0_PG_STS",             BIT(22),	0},
> +	{"SBR16B0_PGD0_PG_STS",          BIT(23),	0},
> +	{"P2SB0_PGD0_PG_STS",            BIT(24),	1},
> +	{"XDCI_PGD0_PG_STS",             BIT(25),	1},
> +	{"EXI_PGD0_PG_STS",              BIT(26),	0},
> +	{"CSE_PGD0_PG_STS",              BIT(27),	1},
> +	{"KVMCC_PGD0_PG_STS",            BIT(28),	1},
> +	{"PMT_PGD0_PG_STS",              BIT(29),	1},
> +	{"CLINK_PGD0_PG_STS",            BIT(30),	1},
> +	{"SBR16B21_PGD0_PG_STS",         BIT(31),	0},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pcdh_power_gating_status_1_map[] = {
> +	{"USBR0_PGD0_PG_STS",            BIT(0),	1},
> +	{"SBR16B22_PGD0_PG_STS",         BIT(1),	0},
> +	{"SMT1_PGD0_PG_STS",             BIT(2),	1},
> +	{"MPFPW1_PGD0_PG_STS",           BIT(3),	0},
> +	{"SMS2_PGD0_PG_STS",             BIT(4),	1},
> +	{"SMS1_PGD0_PG_STS",             BIT(5),	1},
> +	{"CSMERTC_PGD0_PG_STS",          BIT(6),	0},
> +	{"CSMEPSF_PGD0_PG_STS",          BIT(7),	0},
> +	{"D2D_NOC_PGD0_PG_STS",          BIT(8),	0},
> +	{"ESE_PGD0_PG_STS",              BIT(9),	1},
> +	{"SBR16B6_PGD0_PG_STS",          BIT(10),	0},
> +	{"P2SB1_PGD0_PG_STS",            BIT(11),	1},
> +	{"SBR16B3_PGD0_PG_STS",          BIT(12),	0},
> +	{"OSSE_SMT1_PGD0_PG_STS",        BIT(13),	1},
> +	{"D2D_DISP_PGD0_PG_STS",         BIT(14),	1},
> +	{"SNPA_USB2_A_PGD0_PG_STS",      BIT(15),	0},
> +	{"U3FPW1_PGD0_PG_STS",           BIT(16),	0},
> +	{"FIA_X_PGD0_PG_STS",            BIT(17),	0},
> +	{"PSF4_PGD0_PG_STS",             BIT(18),	0},
> +	{"CNVI_PGD0_PG_STS",             BIT(19),	0},
> +	{"UFSX2_PGD0_PG_STS",            BIT(20),	1},
> +	{"ENDBG_PGD0_PG_STS",            BIT(21),	0},
> +	{"DBC_PGD0_PG_STS",              BIT(22),	0},
> +	{"FIA_PG_PGD0_PG_STS",           BIT(23),	0},
> +	{"D2D_IPU_PGD0_PG_STS",          BIT(24),	1},
> +	{"NPK_PGD1_PG_STS",              BIT(25),	0},
> +	{"FIACPCB_X_PGD0_PG_STS",        BIT(26),	0},
> +	{"SBR8B4_PGD0_PG_STS",           BIT(27),	0},
> +	{"DBG_PSF_PGD0_PG_STS",          BIT(28),	0},
> +	{"PSF6_PGD0_PG_STS",             BIT(29),	0},
> +	{"UFSPW1_PGD0_PG_STS",           BIT(30),	0},
> +	{"FIA_U_PGD0_PG_STS",            BIT(31),	0},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pcdh_power_gating_status_2_map[] = {
> +	{"PSF8_PGD0_PG_STS",             BIT(0),	0},
> +	{"SBR16B9_PGD0_PG_STS",          BIT(1),	0},
> +	{"PSF0_PGD0_PG_STS",             BIT(2),	0},
> +	{"FIACPCB_U_PGD0_PG_STS",        BIT(3),	0},
> +	{"TAM_PGD0_PG_STS",              BIT(4),	1},
> +	{"D2D_NOC_PGD2_PG_STS",          BIT(5),	1},
> +	{"SBR8B2_PGD0_PG_STS",           BIT(6),	0},
> +	{"THC0_PGD0_PG_STS",             BIT(7),	1},
> +	{"THC1_PGD0_PG_STS",             BIT(8),	1},
> +	{"PMC_PGD1_PG_STS",              BIT(9),	0},
> +	{"DISP_PGA1_PGD0_PG_STS",        BIT(10),	0},
> +	{"TCSS_PGD0_PG_STS",             BIT(11),	0},
> +	{"DISP_PGA_PGD0_PG_STS",         BIT(12),	0},
> +	{"SBR16B1_PGD0_PG_STS",          BIT(13),	0},
> +	{"SBRG_PGD0_PG_STS",             BIT(14),	0},
> +	{"PSF5_PGD0_PG_STS",             BIT(15),	0},
> +	{"SBR8B3_PGD0_PG_STS",           BIT(16),	0},
> +	{"ACE_PGD0_PG_STS",              BIT(17),	0},
> +	{"ACE_PGD1_PG_STS",              BIT(18),	0},
> +	{"ACE_PGD2_PG_STS",              BIT(19),	0},
> +	{"ACE_PGD3_PG_STS",              BIT(20),	0},
> +	{"ACE_PGD4_PG_STS",              BIT(21),	0},
> +	{"ACE_PGD5_PG_STS",              BIT(22),	0},
> +	{"ACE_PGD6_PG_STS",              BIT(23),	0},
> +	{"ACE_PGD7_PG_STS",              BIT(24),	0},
> +	{"ACE_PGD8_PG_STS",              BIT(25),	0},
> +	{"ACE_PGD9_PG_STS",              BIT(26),	0},
> +	{"ACE_PGD10_PG_STS",             BIT(27),	0},
> +	{"FIACPCB_PG_PGD0_PG_STS",       BIT(28),	0},
> +	{"SNPS_USB2_B_PGD0_PG_STS",      BIT(29),	0},
> +	{"OSSE_PGD0_PG_STS",             BIT(30),	1},
> +	{"SBR8B0_PGD0_PG_STS",           BIT(31),	0},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pcdh_power_gating_status_3_map[] = {
> +	{"SBR16B4_PGD0_PG_STS",          BIT(0),	0},
> +	{"PTIO_PGD0_PG_STS",             BIT(1),	1},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pcdh_d3_status_0_map[] = {
> +	{"LPSS_D3_STS",                  BIT(3),	1},
> +	{"XDCI_D3_STS",                  BIT(4),	1},
> +	{"XHCI_D3_STS",                  BIT(5),	1},
> +	{"OSSE_D3_STS",                  BIT(6),	0},
> +	{"SPA_D3_STS",                   BIT(12),	0},
> +	{"SPB_D3_STS",                   BIT(13),	0},
> +	{"ESPISPI_D3_STS",               BIT(18),	0},
> +	{"PSTH_D3_STS",                  BIT(21),	0},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pcdh_d3_status_1_map[] = {
> +	{"OSSE_SMT1_D3_STS",             BIT(0),	0},
> +	{"GBE_D3_STS",                   BIT(19),	0},
> +	{"ITSS_D3_STS",                  BIT(23),	0},
> +	{"CNVI_D3_STS",                  BIT(27),	0},
> +	{"UFSX2_D3_STS",                 BIT(28),	0},
> +	{"ESE_D3_STS",                   BIT(29),	0},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pcdh_d3_status_2_map[] = {
> +	{"CSMERTC_D3_STS",               BIT(1),	0},
> +	{"CSE_D3_STS",                   BIT(4),	0},
> +	{"KVMCC_D3_STS",                 BIT(5),	0},
> +	{"USBR0_D3_STS",                 BIT(6),	0},
> +	{"ISH_D3_STS",                   BIT(7),	0},
> +	{"SMT1_D3_STS",                  BIT(8),	0},
> +	{"SMT2_D3_STS",                  BIT(9),	0},
> +	{"SMT3_D3_STS",                  BIT(10),	0},
> +	{"OSSE_SMT2_D3_STS",             BIT(11),	0},
> +	{"CLINK_D3_STS",                 BIT(14),	0},
> +	{"PTIO_D3_STS",                  BIT(16),	0},
> +	{"PMT_D3_STS",                   BIT(17),	0},
> +	{"SMS1_D3_STS",                  BIT(18),	0},
> +	{"SMS2_D3_STS",                  BIT(19),	0},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pcdh_d3_status_3_map[] = {
> +	{"THC0_D3_STS",                  BIT(14),	1},
> +	{"THC1_D3_STS",                  BIT(15),	1},
> +	{"OSSE_SMT3_D3_STS",             BIT(16),	0},
> +	{"ACE_D3_STS",                   BIT(23),	0},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pcdh_vnn_req_status_0_map[] = {
> +	{"LPSS_VNN_REQ_STS",             BIT(3),	1},
> +	{"OSSE_VNN_REQ_STS",             BIT(6),	1},
> +	{"ESPISPI_VNN_REQ_STS",          BIT(18),	1},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pcdh_vnn_req_status_1_map[] = {
> +	{"OSSE_SMT1_VNN_REQ_STS",        BIT(0),	1},
> +	{"NPK_VNN_REQ_STS",              BIT(4),	1},
> +	{"DFXAGG_VNN_REQ_STS",           BIT(8),	0},
> +	{"EXI_VNN_REQ_STS",              BIT(9),	1},
> +	{"P2D_VNN_REQ_STS",              BIT(18),	1},
> +	{"GBE_VNN_REQ_STS",              BIT(19),	1},
> +	{"SMB_VNN_REQ_STS",              BIT(25),	1},
> +	{"LPC_VNN_REQ_STS",              BIT(26),	0},
> +	{"ESE_VNN_REQ_STS",              BIT(29),	1},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pcdh_vnn_req_status_2_map[] = {
> +	{"CSMERTC_VNN_REQ_STS",          BIT(1),	1},
> +	{"CSE_VNN_REQ_STS",              BIT(4),	1},
> +	{"ISH_VNN_REQ_STS",              BIT(7),	1},
> +	{"SMT1_VNN_REQ_STS",             BIT(8),	1},
> +	{"CLINK_VNN_REQ_STS",            BIT(14),	1},
> +	{"SMS1_VNN_REQ_STS",             BIT(18),	1},
> +	{"SMS2_VNN_REQ_STS",             BIT(19),	1},
> +	{"GPIOCOM4_VNN_REQ_STS",         BIT(20),	1},
> +	{"GPIOCOM3_VNN_REQ_STS",         BIT(21),	1},
> +	{"DISP_SHIM_VNN_REQ_STS",        BIT(22),	1},
> +	{"GPIOCOM1_VNN_REQ_STS",         BIT(23),	1},
> +	{"GPIOCOM0_VNN_REQ_STS",         BIT(24),	1},
> +	{}
> +};
> +
> +const struct pmc_bit_map nvl_pcdh_vnn_req_status_3_map[] = {
> +	{"DTS0_VNN_REQ_STS",             BIT(7),	0},
> +	{"GPIOCOM5_VNN_REQ_STS",         BIT(11),	1},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pcdh_vnn_misc_status_map[] = {
> +	{"CPU_C10_REQ_STS",              BIT(0),	0},
> +	{"TS_OFF_REQ_STS",               BIT(1),	0},
> +	{"PNDE_MET_REQ_STS",             BIT(2),	1},
> +	{"PG5_PMA0_REQ_STS",             BIT(3),	1},
> +	{"FW_THROTTLE_ALLOWED_REQ_STS",  BIT(4),	0},
> +	{"VNN_SOC_REQ_STS",              BIT(6),	1},
> +	{"ISH_VNNAON_REQ_STS",           BIT(7),	0},
> +	{"D2D_NOC_CFI_QACTIVE_REQ_STS",	 BIT(8),	1},
> +	{"D2D_NOC_GPSB_QACTIVE_REQ_STS", BIT(9),	1},
> +	{"D2D_IPU_QACTIVE_REQ_STS",      BIT(10),	1},
> +	{"PLT_GREATER_REQ_STS",          BIT(11),	1},
> +	{"ALL_SBR_IDLE_REQ_STS",         BIT(12),	0},
> +	{"PMC_IDLE_FB_OCP_REQ_STS",      BIT(13),	0},
> +	{"PM_SYNC_STATES_REQ_STS",       BIT(14),	0},
> +	{"EA_REQ_STS",                   BIT(15),	0},
> +	{"MPHY_CORE_OFF_REQ_STS",        BIT(16),	0},
> +	{"BRK_EV_EN_REQ_STS",            BIT(17),	0},
> +	{"AUTO_DEMO_EN_REQ_STS",         BIT(18),	0},
> +	{"ITSS_CLK_SRC_REQ_STS",         BIT(19),	1},
> +	{"ARC_IDLE_REQ_STS",             BIT(21),	0},
> +	{"PG5_PMA1_REQ_STS",             BIT(22),	1},
> +	{"FIA_DEEP_PM_REQ_STS",          BIT(23),	0},
> +	{"XDCI_ATTACHED_REQ_STS",        BIT(24),	1},
> +	{"ARC_INTERRUPT_WAKE_REQ_STS",   BIT(25),	0},
> +	{"D2D_DISP_DDI_QACTIVE_REQ_STS", BIT(26),	1},
> +	{"PRE_WAKE0_REQ_STS",            BIT(27),	1},
> +	{"PRE_WAKE1_REQ_STS",            BIT(28),	1},
> +	{"PRE_WAKE2_REQ_STS",            BIT(29),	1},
> +	{"PG5_PMA2_GVNN",                BIT(30),	1},
> +	{"D2D_DISP_EDP_QACTIVE_REQ_STS", BIT(31),	1},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pcdh_rsc_status_map[] = {
> +	{"CORE",		0,		1},
> +	{"Memory",		0,		1},
> +	{"PRIM_D2D",		0,		1},
> +	{"PSF0",		0,		1},
> +	{"PSF4",		0,		1},
> +	{"PSF6",		0,		1},
> +	{"PSF8",		0,		1},
> +	{"SB",			0,		1},
> +	{}
> +};
> +
> +static const struct pmc_bit_map *nvl_pcdh_lpm_maps[] = {
> +	nvl_pcdh_clocksource_status_map,
> +	nvl_pcdh_power_gating_status_0_map,
> +	nvl_pcdh_power_gating_status_1_map,
> +	nvl_pcdh_power_gating_status_2_map,
> +	nvl_pcdh_power_gating_status_3_map,
> +	nvl_pcdh_d3_status_0_map,
> +	nvl_pcdh_d3_status_1_map,
> +	nvl_pcdh_d3_status_2_map,
> +	nvl_pcdh_d3_status_3_map,
> +	nvl_pcdh_vnn_req_status_0_map,
> +	nvl_pcdh_vnn_req_status_1_map,
> +	nvl_pcdh_vnn_req_status_2_map,
> +	nvl_pcdh_vnn_req_status_3_map,
> +	nvl_pcdh_vnn_misc_status_map,
> +	ptl_pcdp_signal_status_map,
> +	NULL
> +};
> +
> +static const struct pmc_bit_map *nvl_pcdh_blk_maps[] = {
> +	nvl_pcdh_power_gating_status_0_map,
> +	nvl_pcdh_power_gating_status_1_map,
> +	nvl_pcdh_power_gating_status_2_map,
> +	nvl_pcdh_power_gating_status_3_map,
> +	nvl_pcdh_rsc_status_map,
> +	nvl_pcdh_vnn_req_status_0_map,
> +	nvl_pcdh_vnn_req_status_1_map,
> +	nvl_pcdh_vnn_req_status_2_map,
> +	nvl_pcdh_vnn_req_status_3_map,
> +	nvl_pcdh_d3_status_0_map,
> +	nvl_pcdh_d3_status_1_map,
> +	nvl_pcdh_d3_status_2_map,
> +	nvl_pcdh_d3_status_3_map,
> +	nvl_pcdh_clocksource_status_map,
> +	nvl_pcdh_vnn_misc_status_map,
> +	ptl_pcdp_signal_status_map,
> +	NULL
> +};
> +
> +static const struct pmc_bit_map nvl_pcds_pfear_map[] = {
> +	{"PMC_PGD0",                 BIT(0)},
> +	{"FUSE_OSSE_PGD0",           BIT(1)},
> +	{"SPI_PGD0",                 BIT(2)},
> +	{"XHCI_PGD0",                BIT(3)},
> +	{"SPA_PGD0",                 BIT(4)},
> +	{"SPB_PGD0",                 BIT(5)},
> +	{"RSVD6",                    BIT(6)},
> +	{"GBE_PGD0",                 BIT(7)},
> +
> +	{"RSVD8",                    BIT(0)},
> +	{"RSVD9",                    BIT(1)},
> +	{"SBR16B7_PGD0",             BIT(2)},
> +	{"SBR16B21_PGD0",            BIT(3)},
> +	{"RSVD12",                   BIT(4)},
> +	{"D2D_DISP_PGD1",            BIT(5)},
> +	{"LPSS_PGD0",                BIT(6)},
> +	{"LPC_PGD0",                 BIT(7)},
> +
> +	{"SMB_PGD0",                 BIT(0)},
> +	{"ISH_PGD0",                 BIT(1)},
> +	{"SBR16B1_PGD0",             BIT(2)},
> +	{"NPK_PGD0",                 BIT(3)},
> +	{"D2D_NOC_PGD1",             BIT(4)},
> +	{"DBG_SBR16B_PGD0",          BIT(5)},
> +	{"FUSE_PGD0",                BIT(6)},
> +	{"RSVD23",                   BIT(7)},
> +
> +	{"P2SB0_PGD0",               BIT(0)},
> +	{"OTG_PGD0",                 BIT(1)},
> +	{"EXI_PGD0",                 BIT(2)},
> +	{"CSE_PGD0",                 BIT(3)},
> +	{"CSME_KVM_PGD0",            BIT(4)},
> +	{"CSME_PMT_PGD0",            BIT(5)},
> +	{"CSME_CLINK_PGD0",          BIT(6)},
> +	{"CSME_PTIO_PGD0",           BIT(7)},
> +
> +	{"CSME_USBR_PGD0",           BIT(0)},
> +	{"SBR16B22_PGD0",            BIT(1)},
> +	{"CSME_SMT1_PGD0",           BIT(2)},
> +	{"P2SB1_PGD0",               BIT(3)},
> +	{"CSME_SMS2_PGD0",           BIT(4)},
> +	{"CSME_SMS_PGD0",            BIT(5)},
> +	{"CSME_RTC_PGD0",            BIT(6)},
> +	{"CSMEPSF_PGD0",             BIT(7)},
> +
> +	{"D2D_NOC_PGD0",             BIT(0)},
> +	{"RSVD41",                   BIT(1)},
> +	{"RSVD42",                   BIT(2)},
> +	{"RSVD43",                   BIT(3)},
> +	{"SBR16B2_PGD0",             BIT(4)},
> +	{"OSSE_SMT1_PGD0",           BIT(5)},
> +	{"D2D_DISP_PGD0",            BIT(6)},
> +	{"RSVD47_PGD0",              BIT(7)},
> +
> +	{"RSVD48",                   BIT(0)},
> +	{"DBG_PSF_PGD0",             BIT(1)},
> +	{"RSVD50",                   BIT(2)},
> +	{"CNVI_PGD0",                BIT(3)},
> +	{"UFSX2_PGD0",               BIT(4)},
> +	{"ENDBG_PGD0",               BIT(5)},
> +	{"DBC_PGD0",                 BIT(6)},
> +	{"SBR16B4_PGD0",             BIT(7)},
> +
> +	{"RSVD56",                   BIT(0)},
> +	{"NPK_PGD1",                 BIT(1)},
> +	{"RSVD58",                   BIT(2)},
> +	{"SBR16B20_PGD0",            BIT(3)},
> +	{"RSVD60",                   BIT(4)},
> +	{"SBR8B20_PGD0",             BIT(5)},
> +	{"RSVD62",                   BIT(6)},
> +	{"FIA_U_PGD0",               BIT(7)},
> +
> +	{"PSF8_PGD0",                BIT(0)},
> +	{"RSVD65",                   BIT(1)},
> +	{"RSVD66",                   BIT(2)},
> +	{"FIACPCB_U_PGD0",           BIT(3)},
> +	{"TAM_PGD0",                 BIT(4)},
> +	{"D2D_NOC_PGD2",             BIT(5)},
> +	{"SBR8B2_PGD0",              BIT(6)},
> +	{"THC0_PGD0",                BIT(7)},
> +
> +	{"THC1_PGD0",                BIT(0)},
> +	{"PMC_PGD1",                 BIT(1)},
> +	{"SBR16B3_PGD0",             BIT(2)},
> +	{"TCSS_PGD0",                BIT(3)},
> +	{"DISP_PGA_PGD0",            BIT(4)},
> +	{"RSVD77",                   BIT(5)},
> +	{"RSVD78",                   BIT(6)},
> +	{"RSVD79",                   BIT(7)},
> +
> +	{"SBRG_PGD0",                BIT(0)},
> +	{"RSVD81",                   BIT(1)},
> +	{"SBR16B0_PGD0",             BIT(2)},
> +	{"SBR8B0_PGD0",              BIT(3)},
> +	{"PSF7_PGD0",                BIT(4)},
> +	{"RSVD85",                   BIT(5)},
> +	{"RSVD86",                   BIT(6)},
> +	{"RSVD87",                   BIT(7)},
> +
> +	{"SBR16B6_PGD0",             BIT(0)},
> +	{"PSD0_PGD0",                BIT(1)},
> +	{"STRC_PGD0",                BIT(2)},
> +	{"RSVD91",                   BIT(3)},
> +	{"DBG_SBR_PGD0",             BIT(4)},
> +	{"RSVD93",                   BIT(5)},
> +	{"OSSE_PGD0",                BIT(6)},
> +	{"DISP_PGA1_PGD0",           BIT(7)},
> +	{}
> +};
> +
> +static const struct pmc_bit_map *ext_nvl_pcds_pfear_map[] = {
> +	nvl_pcds_pfear_map,
> +	NULL
> +};
> +
> +static const struct pmc_bit_map nvl_pcds_ltr_show_map[] = {
> +	{"SOUTHPORT_A",		CNP_PMC_LTR_SPA},
> +	{"SOUTHPORT_B",		CNP_PMC_LTR_SPB},
> +	{"SATA",		CNP_PMC_LTR_SATA},
> +	{"GIGABIT_ETHERNET",	CNP_PMC_LTR_GBE},
> +	{"XHCI",		CNP_PMC_LTR_XHCI},
> +	{"SOUTHPORT_F",		ADL_PMC_LTR_SPF},
> +	{"ME",			CNP_PMC_LTR_ME},
> +	{"SATA1",		CNP_PMC_LTR_EVA},
> +	{"SOUTHPORT_C",		CNP_PMC_LTR_SPC},
> +	{"HD_AUDIO",		CNP_PMC_LTR_AZ},
> +	{"CNV",			CNP_PMC_LTR_CNV},
> +	{"LPSS",		CNP_PMC_LTR_LPSS},
> +	{"SOUTHPORT_D",		CNP_PMC_LTR_SPD},
> +	{"SOUTHPORT_E",		CNP_PMC_LTR_SPE},
> +	{"SATA2",		PTL_PMC_LTR_SATA2},
> +	{"ESPI",		CNP_PMC_LTR_ESPI},
> +	{"SCC",			CNP_PMC_LTR_SCC},
> +	{"ISH",			CNP_PMC_LTR_ISH},
> +	{"UFSX2",		CNP_PMC_LTR_UFSX2},
> +	{"EMMC",		CNP_PMC_LTR_EMMC},
> +	{"WIGIG",		ICL_PMC_LTR_WIGIG},
> +	{"THC0",		TGL_PMC_LTR_THC0},
> +	{"THC1",		TGL_PMC_LTR_THC1},
> +	{"SOUTHPORT_G",		MTL_PMC_LTR_SPG},
> +	{"RSVD",		NVL_PCDS_PMC_LTR_RESERVED},
> +	{"IOE_PMC",		MTL_PMC_LTR_IOE_PMC},
> +	{"DMI3",		ARL_PMC_LTR_DMI3},
> +	{"OSSE",		LNL_PMC_LTR_OSSE},
> +
> +	/* Below two cannot be used for LTR_IGNORE */
> +	{"CURRENT_PLATFORM",	PTL_PMC_LTR_CUR_PLT},
> +	{"AGGREGATED_SYSTEM",	PTL_PMC_LTR_CUR_ASLT},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pcds_clocksource_status_map[] = {
> +	{"AON2_OFF_STS",                 BIT(0),	1},
> +	{"AON3_OFF_STS",                 BIT(1),	0},
> +	{"AON4_OFF_STS",                 BIT(2),	1},
> +	{"AON5_OFF_STS",                 BIT(3),	1},
> +	{"AON1_OFF_STS",                 BIT(4),	0},
> +	{"XTAL_LVM_OFF_STS",             BIT(5),	0},
> +	{"D2D_OFF_STS",                  BIT(8),	1},
> +	{"AON3_SPL_OFF_STS",             BIT(9),	1},
> +	{"XTAL_AGGR_OFF_STS",            BIT(17),	1},
> +	{"BCLK_EXT_INJ_OFF_STS",         BIT(18),	1},
> +	{"DDI2_PLL_OFF_STS",             BIT(19),	1},
> +	{"SE_TCSS_PLL_OFF_STS",          BIT(20),	1},
> +	{"DDI_PLL_OFF_STS",              BIT(21),	1},
> +	{"FILTER_PLL_OFF_STS",           BIT(22),	1},
> +	{"PHY_OC_EXT_INJ_OFF_STS",       BIT(23),	1},
> +	{"ACE_PLL_OFF_STS",              BIT(24),	0},
> +	{"FABRIC_PLL_OFF_STS",           BIT(25),	1},
> +	{"SOC_PLL_OFF_STS",              BIT(26),	1},
> +	{"REF_PLL_OFF_STS",              BIT(28),	1},
> +	{"GENLOCK_FILTER_PLL_OFF_STS",   BIT(30),	1},
> +	{"RTC_PLL_OFF_STS",              BIT(31),	0},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pcds_power_gating_status_0_map[] = {
> +	{"PMC_PGD0_PG_STS",              BIT(0),	0},
> +	{"FUSE_OSSE_PGD0_PG_STS",	 BIT(1),	0},
> +	{"ESPISPI_PGD0_PG_STS",          BIT(2),	0},
> +	{"XHCI_PGD0_PG_STS",             BIT(3),	0},
> +	{"SPA_PGD0_PG_STS",              BIT(4),	0},
> +	{"SPB_PGD0_PG_STS",              BIT(5),	0},
> +	{"RSVD_6",                       BIT(6),	0},
> +	{"GBE_PGD0_PG_STS",              BIT(7),	0},
> +	{"RSVD_8",                       BIT(8),	0},
> +	{"RSVD_9",                       BIT(9),	0},
> +	{"SBR16B7_PGD0_PG_STS",          BIT(10),	0},
> +	{"SBR16B21_PGD0_PG_STS",         BIT(11),	0},
> +	{"RSVD_12",                      BIT(12),	0},
> +	{"D2D_DISP_PGD1_PG_STS",         BIT(13),	1},
> +	{"LPSS_PGD0_PG_STS",             BIT(14),	0},
> +	{"LPC_PGD0_PG_STS",              BIT(15),	0},
> +	{"SMB_PGD0_PG_STS",              BIT(16),	0},
> +	{"ISH_PGD0_PG_STS",              BIT(17),	0},
> +	{"SBR16B1_PGD0_PG_STS",          BIT(18),	0},
> +	{"NPK_PGD0_PG_STS",              BIT(19),	0},
> +	{"D2D_NOC_PGD1_PG_STS",          BIT(20),	1},
> +	{"DBG_SBR16B_PGD0_PG_STS",       BIT(21),	0},
> +	{"FUSE_PGD0_PG_STS",             BIT(22),	0},
> +	{"RSVD_23",                      BIT(23),	0},
> +	{"P2SB0_PGD0_PG_STS",            BIT(24),	1},
> +	{"XDCI_PGD0_PG_STS",             BIT(25),	0},
> +	{"EXI_PGD0_PG_STS",              BIT(26),	0},
> +	{"CSE_PGD0_PG_STS",              BIT(27),	1},
> +	{"KVMCC_PGD0_PG_STS",            BIT(28),	0},
> +	{"PMT_PGD0_PG_STS",              BIT(29),	0},
> +	{"CLINK_PGD0_PG_STS",            BIT(30),	0},
> +	{"PTIO_PGD0_PG_STS",             BIT(31),	0},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pcds_power_gating_status_1_map[] = {
> +	{"USBR0_PGD0_PG_STS",            BIT(0),	0},
> +	{"SBR16B22_PGD0_PG_STS",         BIT(1),	0},
> +	{"SMT1_PGD0_PG_STS",             BIT(2),	0},
> +	{"P2SB1_PGD0_PG_STS",            BIT(3),	1},
> +	{"SMS2_PGD0_PG_STS",             BIT(4),	0},
> +	{"SMS1_PGD0_PG_STS",             BIT(5),	0},
> +	{"CSMERTC_PGD0_PG_STS",          BIT(6),	0},
> +	{"CSMEPSF_PGD0_PG_STS",          BIT(7),	0},
> +	{"D2D_NOC_PGD0_PG_STS",          BIT(8),	0},
> +	{"RSVD_9",                       BIT(9),	0},
> +	{"RSVD_10",                      BIT(10),	0},
> +	{"RSVD_11",                      BIT(11),	0},
> +	{"SBR16B2_PGD0_PG_STS",          BIT(12),	0},
> +	{"OSSE_SMT1_PGD0_PG_STS",        BIT(13),	1},
> +	{"D2D_DISP_PGD0_PG_STS",         BIT(14),	1},
> +	{"RSVD_15",                      BIT(15),	0},
> +	{"RSVD_16",                      BIT(16),	0},
> +	{"DBG_PSF_PGD0_PG_STS",          BIT(17),	0},
> +	{"RSVD_18",                      BIT(18),	0},
> +	{"CNVI_PGD0_PG_STS",             BIT(19),	0},
> +	{"UFSX2_PGD0_PG_STS",            BIT(20),	0},
> +	{"ENDBG_PGD0_PG_STS",            BIT(21),	0},
> +	{"DBC_PGD0_PG_STS",              BIT(22),	0},
> +	{"SBR16B4_PGD0_PG_STS",          BIT(23),	0},
> +	{"RSVD_24",                      BIT(24),	0},
> +	{"NPK_PGD1_PG_STS",              BIT(25),	0},
> +	{"RSVD_26",                      BIT(26),	0},
> +	{"SBR16B20_PGD0_PG_STS",         BIT(27),	0},
> +	{"RSVD_28",                      BIT(28),	0},
> +	{"SBR8B20_PGD0_PG_STS",          BIT(29),	0},
> +	{"RSVD_30",                      BIT(30),	0},
> +	{"FIA_U_PGD0_PG_STS",            BIT(31),	0},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pcds_power_gating_status_2_map[] = {
> +	{"PSF8_PGD0_PG_STS",             BIT(0),	0},
> +	{"RSVD_1",                       BIT(1),	0},
> +	{"RSVD_2",                       BIT(2),	0},
> +	{"FIACPCB_U_PGD0_PG_STS",        BIT(3),	0},
> +	{"TAM_PGD0_PG_STS",              BIT(4),	1},
> +	{"D2D_NOC_PGD2_PG_STS",          BIT(5),	1},
> +	{"SBR8B2_PGD0_PG_STS",           BIT(6),	0},
> +	{"THC0_PGD0_PG_STS",             BIT(7),	0},
> +	{"THC1_PGD0_PG_STS",             BIT(8),	0},
> +	{"PMC_PGD1_PG_STS",              BIT(9),	0},
> +	{"SBR16B3_PGD0_PG_STS",          BIT(10),	0},
> +	{"TCSS_PGD0_PG_STS",             BIT(11),	0},
> +	{"DISP_PGA_PGD0_PG_STS",         BIT(12),	0},
> +	{"RSVD_13",                      BIT(13),	0},
> +	{"RSVD_14",                      BIT(14),	0},
> +	{"RSVD_15",                      BIT(15),	0},
> +	{"SBRG_PGD0_PG_STS",             BIT(16),	0},
> +	{"RSVD_17",                      BIT(17),	0},
> +	{"SBR16B0_PGD0_PG_STS",          BIT(18),	0},
> +	{"SBR8B0_PGD0_PG_STS",           BIT(19),	0},
> +	{"PSF7_PGD0_PG_STS",             BIT(20),	0},
> +	{"RSVD_21",                      BIT(21),	0},
> +	{"RSVD_22",                      BIT(22),	0},
> +	{"RSVD_23",                      BIT(23),	0},
> +	{"SBR16B6_PGD0_PG_STS",          BIT(24),	0},
> +	{"PSF0_PGD0_PG_STS",             BIT(25),	0},
> +	{"STRC_PGD0_PG_STS",             BIT(26),	0},
> +	{"RSVD_27",                      BIT(27),	0},
> +	{"DBG_SBR_PGD0_PG_STS",          BIT(28),	0},
> +	{"RSVD_29",                      BIT(29),	0},
> +	{"OSSE_PGD0_PG_STS",             BIT(30),	1},
> +	{"DISP_PGA1_PGD0_PG_STS",        BIT(31),	0},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pcds_d3_status_0_map[] = {
> +	{"LPSS_D3_STS",                  BIT(3),	1},
> +	{"XDCI_D3_STS",                  BIT(4),	1},
> +	{"XHCI_D3_STS",                  BIT(5),	1},
> +	{"SPA_D3_STS",                   BIT(12),	0},
> +	{"SPB_D3_STS",                   BIT(13),	0},
> +	{"ESPISPI_D3_STS",               BIT(18),	0},
> +	{"PSTH_D3_STS",                  BIT(21),	0},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pcds_d3_status_1_map[] = {
> +	{"OSSE_D3_STS",                  BIT(14),	0},
> +	{"GBE_D3_STS",                   BIT(19),	0},
> +	{"ITSS_D3_STS",                  BIT(23),	0},
> +	{"CNVI_D3_STS",                  BIT(27),	0},
> +	{"UFSX2_D3_STS",                 BIT(28),	0},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pcds_d3_status_2_map[] = {
> +	{"CSMERTC_D3_STS",               BIT(1),	0},
> +	{"CSE_D3_STS",                   BIT(4),	0},
> +	{"KVMCC_D3_STS",                 BIT(5),	0},
> +	{"USBR0_D3_STS",                 BIT(6),	0},
> +	{"ISH_D3_STS",                   BIT(7),	0},
> +	{"SMT1_D3_STS",                  BIT(8),	0},
> +	{"SMT2_D3_STS",                  BIT(9),	0},
> +	{"SMT3_D3_STS",                  BIT(10),	0},
> +	{"OSSE_SMT1_D3_STS",             BIT(12),	0},
> +	{"CLINK_D3_STS",                 BIT(14),	0},
> +	{"PTIO_D3_STS",                  BIT(16),	0},
> +	{"PMT_D3_STS",                   BIT(17),	0},
> +	{"SMS1_D3_STS",                  BIT(18),	0},
> +	{"SMS2_D3_STS",                  BIT(19),	0},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pcds_d3_status_3_map[] = {
> +	{"OSSE_SMT2_D3_STS",             BIT(0),	0},
> +	{"THC0_D3_STS",                  BIT(14),	1},
> +	{"THC1_D3_STS",                  BIT(15),	1},
> +	{"OSSE_SMT3_D3_STS",             BIT(19),	0},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pcds_vnn_req_status_0_map[] = {
> +	{"LPSS_VNN_REQ_STS",             BIT(3),	0},
> +	{"ESPISPI_VNN_REQ_STS",          BIT(18),	1},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pcds_vnn_req_status_1_map[] = {
> +	{"NPK_VNN_REQ_STS",              BIT(4),	1},
> +	{"DFXAGG_VNN_REQ_STS",           BIT(8),	0},
> +	{"EXI_VNN_REQ_STS",              BIT(9),	1},
> +	{"OSSE_VNN_REQ_STS",             BIT(14),	1},
> +	{"P2D_VNN_REQ_STS",              BIT(18),	1},
> +	{"GBE_VNN_REQ_STS",              BIT(19),	0},
> +	{"SMB_VNN_REQ_STS",              BIT(25),	1},
> +	{"LPC_VNN_REQ_STS",              BIT(26),	0},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pcds_vnn_req_status_2_map[] = {
> +	{"CSMERTC_VNN_REQ_STS",          BIT(1),	0},
> +	{"CSE_VNN_REQ_STS",              BIT(4),	1},
> +	{"ISH_VNN_REQ_STS",              BIT(7),	0},
> +	{"SMT1_VNN_REQ_STS",             BIT(8),	0},
> +	{"OSSE_SMT1_VNN_REQ_STS",        BIT(12),	1},
> +	{"CLINK_VNN_REQ_STS",            BIT(14),	0},
> +	{"SMS1_VNN_REQ_STS",             BIT(18),	0},
> +	{"SMS2_VNN_REQ_STS",             BIT(19),	0},
> +	{"GPIOCOM4_VNN_REQ_STS",         BIT(20),	0},
> +	{"GPIOCOM3_VNN_REQ_STS",         BIT(21),	1},
> +	{"GPIOCOM1_VNN_REQ_STS",         BIT(23),	1},
> +	{"GPIOCOM0_VNN_REQ_STS",         BIT(24),	1},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pcds_vnn_req_status_3_map[] = {
> +	{"DISP_SHIM_VNN_REQ_STS",        BIT(4),	1},
> +	{"DTS0_VNN_REQ_STS",             BIT(7),	0},
> +	{"GPIOCOM5_VNN_REQ_STS",         BIT(11),	0},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pcds_vnn_misc_status_map[] = {
> +	{"CPU_C10_REQ_STS",              BIT(0),	0},
> +	{"TS_OFF_REQ_STS",               BIT(1),	0},
> +	{"PNDE_MET_REQ_STS",             BIT(2),	1},
> +	{"PG5_PMA0_REQ_STS",             BIT(3),	1},
> +	{"FW_THROTTLE_ALLOWED_REQ_STS",  BIT(4),	0},
> +	{"VNN_SOC_REQ_STS",              BIT(6),	1},
> +	{"ISH_VNNAON_REQ_STS",           BIT(7),	0},
> +	{"D2D_NOC_CFI_QACTIVE_REQ_STS",	 BIT(8),	1},
> +	{"D2D_NOC_GPSB_QACTIVE_REQ_STS", BIT(9),	1},
> +	{"PLT_GREATER_REQ_STS",          BIT(11),	1},
> +	{"ALL_SBR_IDLE_REQ_STS",         BIT(12),	0},
> +	{"PMC_IDLE_FB_OCP_REQ_STS",      BIT(13),	0},
> +	{"PM_SYNC_STATES_REQ_STS",       BIT(14),	0},
> +	{"EA_REQ_STS",                   BIT(15),	0},
> +	{"MPHY_CORE_OFF_REQ_STS",        BIT(16),	0},
> +	{"BRK_EV_EN_REQ_STS",            BIT(17),	0},
> +	{"AUTO_DEMO_EN_REQ_STS",         BIT(18),	0},
> +	{"ITSS_CLK_SRC_REQ_STS",         BIT(19),	1},
> +	{"ARC_IDLE_REQ_STS",             BIT(21),	0},
> +	{"PG5_PMA1_REQ_STS",             BIT(22),	1},
> +	{"DG5_PMA0_REQ_STS",             BIT(23),	1},
> +	{"ARC_INTERRUPT_WAKE_REQ_STS",   BIT(25),	0},
> +	{"D2D_DISP_DDI_QACTIVE_REQ_STS", BIT(26),	1},
> +	{"PRE_WAKE0_REQ_STS",            BIT(27),	1},
> +	{"PRE_WAKE1_REQ_STS",            BIT(28),	1},
> +	{"PRE_WAKE2_REQ_STS",            BIT(29),	1},
> +	{"D2D_DISP_EDP_QACTIVE_REQ_STS", BIT(31),	1},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pcds_rsc_status_map[] = {
> +	{"CORE",		0,		1},
> +	{"Memory",		0,		1},
> +	{"PRIM_D2D",		0,		1},
> +	{"PSF0",		0,		1},
> +	{"SB",			0,		1},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pcds_signal_status_map[] = {
> +	{"LSX_Wake0_STS",		 BIT(0),	0},
> +	{"LSX_Wake1_STS",		 BIT(1),	0},
> +	{"LSX_Wake2_STS",		 BIT(2),	0},
> +	{"LSX_Wake3_STS",		 BIT(3),	0},
> +	{"LSX_Wake4_STS",		 BIT(4),	0},
> +	{"LSX_Wake5_STS",		 BIT(5),	0},
> +	{"LSX_Wake6_STS",		 BIT(6),	0},
> +	{"LSX_Wake7_STS",		 BIT(7),	0},
> +	{"LPSS_Wake0_STS",		 BIT(8),	1},
> +	{"LPSS_Wake1_STS",		 BIT(9),	1},
> +	{"Int_Timer_SS_Wake0_STS",	 BIT(10),	1},
> +	{"Int_Timer_SS_Wake1_STS",	 BIT(11),	1},
> +	{"Int_Timer_SS_Wake2_STS",	 BIT(12),	1},
> +	{"Int_Timer_SS_Wake3_STS",	 BIT(13),	1},
> +	{"Int_Timer_SS_Wake4_STS",	 BIT(14),	1},
> +	{"Int_Timer_SS_Wake5_STS",	 BIT(15),	1},
> +	{}
> +};
> +
> +static const struct pmc_bit_map *nvl_pcds_lpm_maps[] = {
> +	nvl_pcds_clocksource_status_map,
> +	nvl_pcds_power_gating_status_0_map,
> +	nvl_pcds_power_gating_status_1_map,
> +	nvl_pcds_power_gating_status_2_map,
> +	nvl_pcds_d3_status_0_map,
> +	nvl_pcds_d3_status_1_map,
> +	nvl_pcds_d3_status_2_map,
> +	nvl_pcds_d3_status_3_map,
> +	nvl_pcds_vnn_req_status_0_map,
> +	nvl_pcds_vnn_req_status_1_map,
> +	nvl_pcds_vnn_req_status_2_map,
> +	nvl_pcds_vnn_req_status_3_map,
> +	nvl_pcds_vnn_misc_status_map,
> +	nvl_pcds_signal_status_map,
> +	NULL
> +};
> +
> +static const struct pmc_bit_map *nvl_pcds_blk_maps[] = {
> +	nvl_pcds_power_gating_status_0_map,
> +	nvl_pcds_power_gating_status_1_map,
> +	nvl_pcds_power_gating_status_2_map,
> +	nvl_pcds_rsc_status_map,
> +	nvl_pcds_vnn_req_status_0_map,
> +	nvl_pcds_vnn_req_status_1_map,
> +	nvl_pcds_vnn_req_status_2_map,
> +	nvl_pcds_vnn_req_status_3_map,
> +	nvl_pcds_d3_status_0_map,
> +	nvl_pcds_d3_status_1_map,
> +	nvl_pcds_d3_status_2_map,
> +	nvl_pcds_d3_status_3_map,
> +	nvl_pcds_clocksource_status_map,
> +	nvl_pcds_vnn_misc_status_map,
> +	nvl_pcds_signal_status_map,
> +	NULL
> +};
> +
> +static const struct pmc_bit_map nvl_pchs_pfear_map[] = {
> +	{"PMC_PGD0",                 BIT(0)},
> +	{"FIA_D_PGD0",               BIT(1)},
> +	{"SPI_PGD0",                 BIT(2)},
> +	{"XHCI_PGD0",                BIT(3)},
> +	{"SPA_PGD0",                 BIT(4)},
> +	{"SPB_PGD0",                 BIT(5)},
> +	{"MPFPW2_PGD0",              BIT(6)},
> +	{"GBE_PGD0",                 BIT(7)},
> +
> +	{"RSVD8",                    BIT(0)},
> +	{"PSF3_PGD0",                BIT(1)},
> +	{"SBR5_PGD0",                BIT(2)},
> +	{"SBR0_PGD0",                BIT(3)},
> +	{"RSVD12",                   BIT(4)},
> +	{"D2D_DISP_PGD1",            BIT(5)},
> +	{"LPSS_PGD0",                BIT(6)},
> +	{"LPC_PGD0",                 BIT(7)},
> +
> +	{"SMB_PGD0",                 BIT(0)},
> +	{"ISH_PGD0",                 BIT(1)},
> +	{"P2SB_PGD0",                BIT(2)},
> +	{"NPK_PGD0",                 BIT(3)},
> +	{"D2D_NOC_PGD1",             BIT(4)},
> +	{"EAH_PGD0",                 BIT(5)},
> +	{"FUSE_PGD0",                BIT(6)},
> +	{"SBR8_PGD0",                BIT(7)},
> +
> +	{"PSF7_PGD0",                BIT(0)},
> +	{"OTG_PGD0",                 BIT(1)},
> +	{"EXI_PGD0",                 BIT(2)},
> +	{"CSE_PGD0",                 BIT(3)},
> +	{"CSME_KVM_PGD0",            BIT(4)},
> +	{"CSME_PMT_PGD0",            BIT(5)},
> +	{"CSME_CLINK_PGD0",          BIT(6)},
> +	{"CSME_PTIO_PGD0",           BIT(7)},
> +
> +	{"CSME_USBR_PGD0",           BIT(0)},
> +	{"SBR1_PGD0",                BIT(1)},
> +	{"CSME_SMT1_PGD0",           BIT(2)},
> +	{"MPFPW1_PGD0",              BIT(3)},
> +	{"CSME_SMS2_PGD0",           BIT(4)},
> +	{"CSME_SMS_PGD0",            BIT(5)},
> +	{"CSME_RTC_PGD0",            BIT(6)},
> +	{"CSMEPSF_PGD0",             BIT(7)},
> +
> +	{"D2D_NOC_PGD0",             BIT(0)},
> +	{"ESE_PGD0",                 BIT(1)},
> +	{"SBR2_PGD0",                BIT(2)},
> +	{"SBR3_PGD0",                BIT(3)},
> +	{"SBR4_PGD0",                BIT(4)},
> +	{"RSVD45",                   BIT(5)},
> +	{"D2D_DISP_PGD0",            BIT(6)},
> +	{"PSF1_PGD0",                BIT(7)},
> +
> +	{"U3FPW1_PGD0",              BIT(0)},
> +	{"DMI3FPW_PGD0",             BIT(1)},
> +	{"PSF4_PGD0",                BIT(2)},
> +	{"CNVI_PGD0",                BIT(3)},
> +	{"RSVD52",                   BIT(4)},
> +	{"ENDBG_PGD0",               BIT(5)},
> +	{"DBC_PGD0",                 BIT(6)},
> +	{"SMT4_PGD0",                BIT(7)},
> +
> +	{"RSVD56",                   BIT(0)},
> +	{"NPK_PGD1",                 BIT(1)},
> +	{"RSVD58",                   BIT(2)},
> +	{"DMI3_PGD0",                BIT(3)},
> +	{"RSVD60",                   BIT(4)},
> +	{"FIACPCB_D_PGD0",           BIT(5)},
> +	{"RSVD62",                   BIT(6)},
> +	{"FIA_U_PGD0",               BIT(7)},
> +
> +	{"FIACPCB_PGS_PGD0",         BIT(0)},
> +	{"FIA_PGS_PGD0",             BIT(1)},
> +	{"RSVD66",                   BIT(2)},
> +	{"FIACPCB_U_PGD0",           BIT(3)},
> +	{"TAM_PGD0",                 BIT(4)},
> +	{"D2D_NOC_PGD2",             BIT(5)},
> +	{"PSF2_PGD0",                BIT(6)},
> +	{"THC0_PGD0",                BIT(7)},
> +
> +	{"THC1_PGD0",                BIT(0)},
> +	{"PMC_PGD1",                 BIT(1)},
> +	{"SBR9_PGD0",                BIT(2)},
> +	{"U3FPW2_PGD0",              BIT(3)},
> +	{"RSVD76",                   BIT(4)},
> +	{"DBG_PSF_PGD0",             BIT(5)},
> +	{"DBG_SBR_PGD0",             BIT(6)},
> +	{"SBR6_PGD0",                BIT(7)},
> +
> +	{"SPC_PGD0",                 BIT(0)},
> +	{"ACE_PGD0",                 BIT(1)},
> +	{"ACE_PGD1",                 BIT(2)},
> +	{"ACE_PGD2",                 BIT(3)},
> +	{"ACE_PGD3",                 BIT(4)},
> +	{"ACE_PGD4",                 BIT(5)},
> +	{"ACE_PGD5",                 BIT(6)},
> +	{"ACE_PGD6",                 BIT(7)},
> +
> +	{"ACE_PGD7",                 BIT(0)},
> +	{"ACE_PGD8",                 BIT(1)},
> +	{"ACE_PGD9",                 BIT(2)},
> +	{"ACE_PGD10",                BIT(3)},
> +	{"U3FPW3_PGD0",              BIT(4)},
> +	{"SBR7_PGD0",                BIT(5)},
> +	{"OSSE_PGD0",                BIT(6)},
> +	{"ST_PGD0",                  BIT(7)},
> +	{}
> +};
> +
> +static const struct pmc_bit_map *ext_nvl_pchs_pfear_map[] = {
> +	nvl_pchs_pfear_map,
> +	NULL
> +};
> +
> +static const struct pmc_bit_map nvl_pchs_clocksource_status_map[] = {
> +	{"AON2_OFF_STS",                 BIT(0),	1},
> +	{"AON3_OFF_STS",                 BIT(1),	0},
> +	{"AON4_OFF_STS",                 BIT(2),	0},
> +	{"AON2_SPL_OFF_STS",             BIT(3),	0},
> +	{"AONL_OFF_STS",                 BIT(4),	0},
> +	{"XTAL_LVM_OFF_STS",             BIT(5),	0},
> +	{"AON5_OFF_STS",                 BIT(6),	0},
> +	{"USB3_PLL_OFF_STS",             BIT(8),	1},
> +	{"MAIN_CRO_OFF_STS",             BIT(11),	0},
> +	{"MAIN_DIVIDER_OFF_STS",         BIT(12),	1},
> +	{"REF_PLL_NON_OC_OFF_STS",       BIT(13),	1},
> +	{"DMI_PLL_OFF_STS",              BIT(14),	1},
> +	{"PHY_EXT_INJ_OFF_STS",          BIT(15),	1},
> +	{"AON6_MCRO_OFF_STS",            BIT(16),	0},
> +	{"XTAL_AGGR_OFF_STS",            BIT(17),	0},
> +	{"USB2_PLL_OFF_STS",             BIT(18),	1},
> +	{"GBE_PLL_OFF_STS",              BIT(21),	1},
> +	{"SATA_PLL_OFF_STS",             BIT(22),	1},
> +	{"PCIE0_PLL_OFF_STS",            BIT(23),	1},
> +	{"PCIE1_PLL_OFF_STS",            BIT(24),	1},
> +	{"FABRIC_PLL_OFF_STS",           BIT(25),	1},
> +	{"PCIE2_PLL_OFF_STS",            BIT(26),	1},
> +	{"REF_PLL_OFF_STS",              BIT(28),	1},
> +	{"REF38P4_PLL_OFF_STS",          BIT(31),	1},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pchs_power_gating_status_0_map[] = {
> +	{"PMC_PGD0_PG_STS",              BIT(0),	0},
> +	{"FIA_D_PGD0_PG_STS",            BIT(1),	0},
> +	{"ESPISPI_PGD0_PG_STS",          BIT(2),	0},
> +	{"XHCI_PGD0_PG_STS",             BIT(3),	0},
> +	{"SPA_PGD0_PG_STS",              BIT(4),	1},
> +	{"SPB_PGD0_PG_STS",              BIT(5),	1},
> +	{"MPFPW2_PGD0_PG_STS",           BIT(6),	0},
> +	{"GBE_PGD0_PG_STS",              BIT(7),	1},
> +	{"RSVD_8",                       BIT(8),	0},
> +	{"PSF3_PGD0_PG_STS",             BIT(9),	0},
> +	{"SBR5_PGD0_PG_STS",             BIT(10),	0},
> +	{"SBR0_PGD0_PG_STS",             BIT(11),	0},
> +	{"RSVD_12",                      BIT(12),	0},
> +	{"D2D_DISP_PGD1_PG_STS",         BIT(13),	0},
> +	{"LPSS_PGD0_PG_STS",             BIT(14),	1},
> +	{"LPC_PGD0_PG_STS",              BIT(15),	0},
> +	{"SMB_PGD0_PG_STS",              BIT(16),	0},
> +	{"ISH_PGD0_PG_STS",              BIT(17),	0},
> +	{"P2S_PGD0_PG_STS",              BIT(18),	0},
> +	{"NPK_PGD0_PG_STS",              BIT(19),	0},
> +	{"D2D_NOC_PGD1_PG_STS",          BIT(20),	0},
> +	{"EAH_PGD0_PG_STS",              BIT(21),	0},
> +	{"FUSE_PGD0_PG_STS",             BIT(22),	0},
> +	{"SBR8_PGD0_PG_STS",             BIT(23),	0},
> +	{"PSF7_PGD0_PG_STS",             BIT(24),	0},
> +	{"XDCI_PGD0_PG_STS",             BIT(25),	1},
> +	{"EXI_PGD0_PG_STS",              BIT(26),	0},
> +	{"CSE_PGD0_PG_STS",              BIT(27),	1},
> +	{"KVMCC_PGD0_PG_STS",            BIT(28),	1},
> +	{"PMT_PGD0_PG_STS",              BIT(29),	1},
> +	{"CLINK_PGD0_PG_STS",            BIT(30),	1},
> +	{"PTIO_PGD0_PG_STS",             BIT(31),	1},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pchs_power_gating_status_1_map[] = {
> +	{"USBR0_PGD0_PG_STS",            BIT(0),	1},
> +	{"SBR1_PGD0_PG_STS",             BIT(1),	0},
> +	{"SMT1_PGD0_PG_STS",             BIT(2),	1},
> +	{"MPFPW1_PGD0_PG_STS",           BIT(3),	0},
> +	{"SMS2_PGD0_PG_STS",             BIT(4),	1},
> +	{"SMS1_PGD0_PG_STS",             BIT(5),	1},
> +	{"CSMERTC_PGD0_PG_STS",          BIT(6),	0},
> +	{"CSMEPSF_PGD0_PG_STS",          BIT(7),	0},
> +	{"D2D_NOC_PGD0_PG_STS",          BIT(8),	0},
> +	{"ESE_PGD0_PG_STS",              BIT(9),	1},
> +	{"SBR2_PGD0_PG_STS",             BIT(10),	0},
> +	{"SBR3_PGD0_PG_STS",             BIT(11),	0},
> +	{"SBR4_PGD0_PG_STS",             BIT(12),	0},
> +	{"RSVD_13",                      BIT(13),	0},
> +	{"D2D_DISP_PGD0_PG_STS",         BIT(14),	0},
> +	{"PSF1_PGD0_PG_STS",             BIT(15),	0},
> +	{"U3FPW1_PGD0_PG_STS",           BIT(16),	0},
> +	{"DMI3FPW_PGD0_PG_STS",          BIT(17),	0},
> +	{"PSF4_PGD0_PG_STS",             BIT(18),	0},
> +	{"CNVI_PGD0_PG_STS",             BIT(19),	0},
> +	{"RSVD_20",                      BIT(20),	0},
> +	{"ENDBG_PGD0_PG_STS",            BIT(21),	0},
> +	{"DBC_PGD0_PG_STS",              BIT(22),	0},
> +	{"SMT4_PGD0_PG_STS",             BIT(23),	1},
> +	{"RSVD_24",                      BIT(24),	0},
> +	{"NPK_PGD1_PG_STS",              BIT(25),	0},
> +	{"RSVD_26",                      BIT(26),	0},
> +	{"DMI3_PGD0_PG_STS",             BIT(27),	1},
> +	{"RSVD_28",                      BIT(28),	0},
> +	{"FIACPCB_D_PGD0_PG_STS",        BIT(29),	0},
> +	{"RSVD_30",                      BIT(30),	0},
> +	{"FIA_U_PGD0_PG_STS",            BIT(31),	0},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pchs_power_gating_status_2_map[] = {
> +	{"FIACPCB_PGS_PGD0_PG_STS",      BIT(0),	0},
> +	{"FIA_PGS_PGD0_PG_STS",          BIT(1),	0},
> +	{"RSVD_2",                       BIT(2),	0},
> +	{"FIACPCB_U_PGD0_PG_STS",        BIT(3),	0},
> +	{"TAM_PGD0_PG_STS",              BIT(4),	0},
> +	{"D2D_NOC_PGD2_PG_STS",          BIT(5),	0},
> +	{"PSF2_PGD0_PG_STS",             BIT(6),	0},
> +	{"THC0_PGD0_PG_STS",             BIT(7),	1},
> +	{"THC1_PGD0_PG_STS",             BIT(8),	1},
> +	{"PMC_PGD1_PG_STS",              BIT(9),	0},
> +	{"SBR9_PGA0_PGD0_PG_STS",        BIT(10),	0},
> +	{"U3FPW2_PGD0_PG_STS",           BIT(11),	0},
> +	{"RSVD_12",                      BIT(12),	0},
> +	{"DBG_PSF_PGD0_PG_STS",          BIT(13),	0},
> +	{"DBG_SBR_PGD0_PG_STS",          BIT(14),	0},
> +	{"SBR6_PGD0_PG_STS",             BIT(15),	0},
> +	{"SPC_PGD0_PG_STS",              BIT(16),	1},
> +	{"ACE_PGD0_PG_STS",              BIT(17),	0},
> +	{"ACE_PGD1_PG_STS",              BIT(18),	0},
> +	{"ACE_PGD2_PG_STS",              BIT(19),	0},
> +	{"ACE_PGD3_PG_STS",              BIT(20),	0},
> +	{"ACE_PGD4_PG_STS",              BIT(21),	0},
> +	{"ACE_PGD5_PG_STS",              BIT(22),	0},
> +	{"ACE_PGD6_PG_STS",              BIT(23),	0},
> +	{"ACE_PGD7_PG_STS",              BIT(24),	0},
> +	{"ACE_PGD8_PG_STS",              BIT(25),	0},
> +	{"ACE_PGD9_PG_STS",              BIT(26),	0},
> +	{"ACE_PGD10_PG_STS",             BIT(27),	0},
> +	{"U3FPW3_PGD0_PG_STS",           BIT(28),	0},
> +	{"SBR7_PGD0_PG_STS",             BIT(29),	0},
> +	{"OSSE_PGD0_PG_STS",             BIT(30),	0},
> +	{"SATA_PGD0_PG_STS",             BIT(31),	1},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pchs_d3_status_0_map[] = {
> +	{"LPSS_D3_STS",                  BIT(3),	1},
> +	{"XDCI_D3_STS",                  BIT(4),	1},
> +	{"XHCI_D3_STS",                  BIT(5),	0},
> +	{"SPA_D3_STS",                   BIT(12),	0},
> +	{"SPB_D3_STS",                   BIT(13),	0},
> +	{"SPC_D3_STS",                   BIT(14),	0},
> +	{"ESPISPI_D3_STS",               BIT(18),	0},
> +	{"SATA_D3_STS",                  BIT(20),	1},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pchs_d3_status_1_map[] = {
> +	{"OSSE_D3_STS",                  BIT(6),	0},
> +	{"GBE_D3_STS",                   BIT(19),	0},
> +	{"ITSS_D3_STS",                  BIT(23),	0},
> +	{"P2S_D3_STS",                   BIT(24),	0},
> +	{"CNVI_D3_STS",                  BIT(27),	0},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pchs_d3_status_2_map[] = {
> +	{"CSMERTC_D3_STS",               BIT(1),	0},
> +	{"CSE_D3_STS",                   BIT(4),	0},
> +	{"KVMCC_D3_STS",                 BIT(5),	0},
> +	{"USBR0_D3_STS",                 BIT(6),	0},
> +	{"ISH_D3_STS",                   BIT(7),	0},
> +	{"SMT1_D3_STS",                  BIT(8),	0},
> +	{"SMT2_D3_STS",                  BIT(9),	0},
> +	{"SMT3_D3_STS",                  BIT(10),	0},
> +	{"SMT4_D3_STS",                  BIT(11),	0},
> +	{"SMT5_D3_STS",                  BIT(12),	0},
> +	{"SMT6_D3_STS",                  BIT(13),	0},
> +	{"CLINK_D3_STS",                 BIT(14),	0},
> +	{"PTIO_D3_STS",                  BIT(16),	0},
> +	{"PMT_D3_STS",                   BIT(17),	0},
> +	{"SMS1_D3_STS",                  BIT(18),	0},
> +	{"SMS2_D3_STS",                  BIT(19),	0},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pchs_d3_status_3_map[] = {
> +	{"THC0_D3_STS",                  BIT(14),	0},
> +	{"THC1_D3_STS",                  BIT(15),	0},
> +	{"ACE_D3_STS",                   BIT(23),	0},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pchs_vnn_req_status_1_map[] = {
> +	{"NPK_VNN_REQ_STS",              BIT(4),	0},
> +	{"OSSE_VNN_REQ_STS",             BIT(6),	0},
> +	{"DFXAGG_VNN_REQ_STS",           BIT(8),	0},
> +	{"EXI_VNN_REQ_STS",              BIT(9),	0},
> +	{"GBE_VNN_REQ_STS",              BIT(19),	0},
> +	{"SMB_VNN_REQ_STS",              BIT(25),	0},
> +	{"LPC_VNN_REQ_STS",              BIT(26),	0},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pchs_vnn_req_status_2_map[] = {
> +	{"CSMERTC_VNN_REQ_STS",          BIT(1),	0},
> +	{"CSE_VNN_REQ_STS",              BIT(4),	0},
> +	{"ISH_VNN_REQ_STS",              BIT(7),	0},
> +	{"SMT1_VNN_REQ_STS",             BIT(8),	0},
> +	{"SMT4_VNN_REQ_STS",             BIT(11),	0},
> +	{"CLINK_VNN_REQ_STS",            BIT(14),	0},
> +	{"SMS1_VNN_REQ_STS",             BIT(18),	0},
> +	{"SMS2_VNN_REQ_STS",             BIT(19),	0},
> +	{"GPIOCOM4_VNN_REQ_STS",         BIT(20),	0},
> +	{"GPIOCOM3_VNN_REQ_STS",         BIT(21),	0},
> +	{"GPIOCOM2_VNN_REQ_STS",         BIT(22),	0},
> +	{"GPIOCOM1_VNN_REQ_STS",         BIT(23),	0},
> +	{"GPIOCOM0_VNN_REQ_STS",         BIT(24),	0},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pchs_vnn_misc_status_map[] = {
> +	{"CPU_C10_REQ_STS",              BIT(0),	0},
> +	{"TS_OFF_REQ_STS",               BIT(1),	0},
> +	{"PNDE_MET_REQ_STS",             BIT(2),	1},
> +	{"PG5_PMA0_GVNN_REQ_STS",        BIT(3),	1},
> +	{"FW_THROTTLE_ALLOWED_REQ_STS",  BIT(4),	0},
> +	{"DMI_IN_L1_REQ_STS",            BIT(6),	0},
> +	{"ISH_VNNAON_REQ_STS",           BIT(7),	0},
> +	{"PLT_GREATER_REQ_STS",          BIT(11),	1},
> +	{"ALL_SBR_IDLE_REQ_STS",         BIT(12),	0},
> +	{"PMC_IDLE_FB_OCP_REQ_STS",      BIT(13),	0},
> +	{"PM_SYNC_STATES_REQ_STS",       BIT(14),	0},
> +	{"EA_REQ_STS",                   BIT(15),	0},
> +	{"DMI_CLKREQ_B_REQ_STS",         BIT(16),	0},
> +	{"BRK_EV_EN_REQ_STS",            BIT(17),	0},
> +	{"AUTO_DEMO_EN_REQ_STS",         BIT(18),	0},
> +	{"ITSS_CLK_SRC_REQ_STS",         BIT(19),	1},
> +	{"ARC_IDLE_REQ_STS",             BIT(21),	0},
> +	{"PG5_PMA1_GVNN_REQ_STS",        BIT(22),	1},
> +	{"FIA_DEEP_PM_REQ_STS",          BIT(23),	0},
> +	{"XDCI_ATTACHED_REQ_STS",        BIT(24),	0},
> +	{"ARC_INTERRUPT_WAKE_REQ_STS",   BIT(25),	0},
> +	{"PRE_WAKE0_REQ_STS",            BIT(27),	1},
> +	{"PRE_WAKE1_REQ_STS",            BIT(28),	1},
> +	{"PRE_WAKE2_EN_REQ_STS",         BIT(29),	0},
> +	{"PG5_PMA2_GVNN_REQ_STS",        BIT(30),	1},
> +	{}
> +};
> +
> +static const struct pmc_bit_map nvl_pchs_rsc_status_map[] = {
> +	{"Memory",		0,		1},
> +	{"Memory_NS",		0,		1},
> +	{"PSF1",		0,		1},
> +	{"PSF2",		0,		1},
> +	{"PSF3",		0,		1},
> +	{"REF_PLL",		0,		1},
> +	{"SB",			0,		1},
> +	{}
> +};
> +
> +static const struct pmc_bit_map *nvl_pchs_lpm_maps[] = {
> +	nvl_pchs_clocksource_status_map,
> +	nvl_pchs_power_gating_status_0_map,
> +	nvl_pchs_power_gating_status_1_map,
> +	nvl_pchs_power_gating_status_2_map,
> +	nvl_pchs_d3_status_0_map,
> +	nvl_pchs_d3_status_1_map,
> +	nvl_pchs_d3_status_2_map,
> +	nvl_pchs_d3_status_3_map,
> +	nvl_pcds_vnn_req_status_0_map,
> +	nvl_pchs_vnn_req_status_1_map,
> +	nvl_pchs_vnn_req_status_2_map,
> +	nvl_pcdh_vnn_req_status_3_map,
> +	nvl_pchs_vnn_misc_status_map,
> +	ptl_pcdp_signal_status_map,
> +	NULL
> +};
> +
> +static const struct pmc_bit_map *nvl_pchs_blk_maps[] = {
> +	nvl_pchs_power_gating_status_0_map,
> +	nvl_pchs_power_gating_status_1_map,
> +	nvl_pchs_power_gating_status_2_map,
> +	nvl_pchs_rsc_status_map,
> +	nvl_pchs_d3_status_0_map,
> +	nvl_pchs_clocksource_status_map,
> +	nvl_pchs_vnn_misc_status_map,
> +	NULL
> +};
> +
> +static const struct pmc_reg_map nvl_pcdh_reg_map = {
> +	.pfear_sts = ext_nvl_pcdh_pfear_map,
> +	.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
> +	.slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
> +	.ltr_show_sts = ptl_pcdp_ltr_show_map,
> +	.msr_sts = msr_map,
> +	.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
> +	.regmap_length = NVL_PCDH_PMC_MMIO_REG_LEN,
> +	.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
> +	.ppfear_buckets = NVL_PCDH_PPFEAR_NUM_ENTRIES,
> +	.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
> +	.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
> +	.lpm_num_maps = NVL_LPM_NUM_MAPS,
> +	.ltr_ignore_max = LNL_NUM_IP_IGN_ALLOWED,
> +	.lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
> +	.etr3_offset = ETR3_OFFSET,
> +	.lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET,
> +	.lpm_priority_offset = NVL_LPM_PRI_OFFSET,
> +	.lpm_en_offset = NVL_LPM_EN_OFFSET,
> +	.lpm_residency_offset = NVL_LPM_RESIDENCY_OFFSET,
> +	.lpm_sts = nvl_pcdh_lpm_maps,
> +	.lpm_status_offset = MTL_LPM_STATUS_OFFSET,
> +	.lpm_live_status_offset = NVL_LPM_LIVE_STATUS_OFFSET,
> +	.s0ix_blocker_maps = nvl_pcdh_blk_maps,
> +	.s0ix_blocker_offset = LNL_S0IX_BLOCKER_OFFSET,
> +	.num_s0ix_blocker = NVL_PCDH_NUM_S0IX_BLOCKER,
> +	.blocker_req_offset = NVL_PCDH_BLK_REQ_OFFSET,
> +	.lpm_req_guid = PCDH_LPM_REQ_GUID,
> +};
> +
> +static const struct pmc_reg_map nvl_pcds_reg_map = {
> +	.pfear_sts = ext_nvl_pcds_pfear_map,
> +	.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
> +	.slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
> +	.ltr_show_sts = nvl_pcds_ltr_show_map,
> +	.msr_sts = msr_map,
> +	.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
> +	.regmap_length = NVL_PCDS_PMC_MMIO_REG_LEN,
> +	.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
> +	.ppfear_buckets = LNL_PPFEAR_NUM_ENTRIES,
> +	.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
> +	.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
> +	.lpm_num_maps = PTL_LPM_NUM_MAPS,
> +	.ltr_ignore_max = LNL_NUM_IP_IGN_ALLOWED,
> +	.lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
> +	.etr3_offset = ETR3_OFFSET,
> +	.lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET,
> +	.lpm_priority_offset = MTL_LPM_PRI_OFFSET,
> +	.lpm_en_offset = MTL_LPM_EN_OFFSET,
> +	.lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET,
> +	.lpm_sts = nvl_pcds_lpm_maps,
> +	.lpm_status_offset = MTL_LPM_STATUS_OFFSET,
> +	.lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,
> +	.s0ix_blocker_maps = nvl_pcds_blk_maps,
> +	.s0ix_blocker_offset = LNL_S0IX_BLOCKER_OFFSET,
> +	.num_s0ix_blocker = NVL_PCDS_NUM_S0IX_BLOCKER,
> +	.lpm_req_guid = PCDS_LPM_REQ_GUID,
> +	.blocker_req_offset = NVL_PCDS_BLK_REQ_OFFSET,
> +};
> +
> +static const struct pmc_reg_map nvl_pchs_reg_map = {
> +	.pfear_sts = ext_nvl_pchs_pfear_map,
> +	.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
> +	.slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
> +	.ltr_show_sts = ptl_pcdp_ltr_show_map,
> +	.msr_sts = msr_map,
> +	.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
> +	.regmap_length = NVL_PCHS_PMC_MMIO_REG_LEN,
> +	.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
> +	.ppfear_buckets = LNL_PPFEAR_NUM_ENTRIES,
> +	.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
> +	.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
> +	.lpm_num_maps = PTL_LPM_NUM_MAPS,
> +	.ltr_ignore_max = LNL_NUM_IP_IGN_ALLOWED,
> +	.lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
> +	.etr3_offset = ETR3_OFFSET,
> +	.lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET,
> +	.lpm_priority_offset = MTL_LPM_PRI_OFFSET,
> +	.lpm_en_offset = MTL_LPM_EN_OFFSET,
> +	.lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET,
> +	.lpm_sts = nvl_pchs_lpm_maps,
> +	.lpm_status_offset = MTL_LPM_STATUS_OFFSET,
> +	.lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,
> +	.s0ix_blocker_maps = nvl_pchs_blk_maps,
> +	.s0ix_blocker_offset = LNL_S0IX_BLOCKER_OFFSET,
> +	.num_s0ix_blocker = NVL_PCHS_NUM_S0IX_BLOCKER,
> +	.blocker_req_offset = NVL_PCHS_BLK_REQ_OFFSET,
> +	.lpm_req_guid = PCHS_LPM_REQ_GUID,
> +};
> +
> +static struct pmc_info nvl_pmc_info_list[] = {
> +	{
> +		.devid	= PMC_DEVID_NVL_PCDH,
> +		.map	= &nvl_pcdh_reg_map,
> +	},
> +	{
> +		.devid  = PMC_DEVID_NVL_PCDS,
> +		.map    = &nvl_pcds_reg_map,
> +	},
> +	{
> +		.devid  = PMC_DEVID_NVL_PCHS,
> +		.map    = &nvl_pchs_reg_map,
> +	},
> +	{}
> +};
> +
> +const char *nvl_ltr_block_counter_arr[] = {
> +	"PKGC_PREVENT_LTR_IADOMAIN",
> +	"PKGC_PREVENT_LTR_GDIE",
> +	"PKGC_PREVENT_LTR_PCH",
> +	"PKGC_PREVENT_LTR_DISPLAY",
> +	"PKGC_PREVENT_LTR_IPU",
> +	NULL
> +};
> +
> +const char *nvl_pkgc_blocker_residency[] = {
> +	"PKGC_BLOCK_RESIDENCY_INVALID",
> +	"PKGC_BLOCK_RESIDENCY_MISC",
> +	"PKGC_BLOCK_RESIDENCY_CDIE_MISC",
> +	"PKGC_BLOCK_RESIDENCY_MEDIA_MISC",
> +	"PKGC_BLOCK_RESIDENCY_GT_MISC",
> +	"PKGC_BLOCK_RESIDENCY_HUBATOM_MISC",
> +	"PKGC_BLOCK_RESIDENCY_IPU_BUSY",
> +	"PKGC_BLOCK_RESIDENCY_IPU_LTR",
> +	"PKGC_BLOCK_RESIDENCY_IPU_TIMER",
> +	"PKGC_BLOCK_RESIDENCY_DISP_BUSY",
> +	"PKGC_BLOCK_RESIDENCY_DISP_LTR",
> +	"PKGC_BLOCK_RESIDENCY_DISP_TIMER",
> +	"PKGC_BLOCK_RESIDENCY_VPU_BUSY",
> +	"PKGC_BLOCK_RESIDENCY_VPU_TIMER",
> +	"PKGC_BLOCK_RESIDENCY_PMC_BUSY",
> +	"PKGC_BLOCK_RESIDENCY_PMC_LTR",
> +	"PKGC_BLOCK_RESIDENCY_PMC_TIMER",
> +	"PKGC_BLOCK_RESIDENCY_HUBATOM_ARAT",
> +	"PKGC_BLOCK_RESIDENCY_CDIE0_ARAT",
> +	"PKGC_BLOCK_RESIDENCY_CDIE1_ARAT",
> +	"PKGC_BLOCK_RESIDENCY_GT_ARAT",
> +	"PKGC_BLOCK_RESIDENCY_MEDIA_ARAT",
> +	"PKGC_BLOCK_RESIDENCY_DEMOTION",
> +	"PKGC_BLOCK_RESIDENCY_THERMALS",
> +	"PKGC_BLOCK_RESIDENCY_SNCU",
> +	"PKGC_BLOCK_RESIDENCY_SVTU",
> +	"PKGC_BLOCK_RESIDENCY_IAA",
> +	"PKGC_BLOCK_RESIDENCY_IOC",
> +	NULL,
> +};
> +
> +static u8 nvl_pmc_list[] = {PMC_IDX_MAIN, PMC_IDX_PCH, PMC_IDX_MAX};
> +static u8 nvl_h_pmc_list[] = {PMC_IDX_MAIN, PMC_IDX_PCH, PMC_IDX_MAX};
> +
> +#define NVL_NPU_PCI_DEV                0xd71d
> +
> +/*
> + * Set power state of select devices that do not have drivers to D3
> + * so that they do not block Package C entry.
> + */
> +static void nvl_d3_fixup(void)
> +{
> +	pmc_core_set_device_d3(NVL_NPU_PCI_DEV);
> +}
> +
> +static int nvl_resume(struct pmc_dev *pmcdev)
> +{
> +	nvl_d3_fixup();
> +	return cnl_resume(pmcdev);
> +}
> +
> +static int nvl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info)
> +{
> +	nvl_d3_fixup();
> +	return generic_core_init(pmcdev, pmc_dev_info);
> +}
> +
> +static u32 NVL_PMT_DMU_GUIDS[] = {NVL_PMT_DMU_GUID, 0x0};

Please use lowercase for the name. Uppercase is reserved for macros.

I seem to have missed the others got added with uppercase. The distinction 
between macros & variables is important so lets try to not muddle waters 
when it comes to that.

> +struct pmc_dev_info nvl_s_pmc_dev = {
> +	.pmc_list = nvl_pmc_list,
> +	.regmap_list = nvl_pmc_info_list,
> +	.map = &nvl_pcds_reg_map,
> +	.sub_req_show = &pmc_core_substate_blk_req_fops,
> +	.suspend = cnl_suspend,
> +	.resume = nvl_resume,
> +	.init = nvl_core_init,
> +	.sub_req = pmc_core_pmt_get_blk_sub_req,
> +	.dmu_guids = NVL_PMT_DMU_GUIDS,
> +	.pc_guid = NVL_PMT_PC_GUID,
> +	.pkgc_ltr_blocker_offset = NVL_LTR_BLK_OFFSET,
> +	.pkgc_ltr_blocker_counters = nvl_ltr_block_counter_arr,
> +	.pkgc_blocker_offset = NVL_PKGC_BLK_OFFSET,
> +	.pkgc_blocker_counters = nvl_pkgc_blocker_residency,
> +	.ssram_hidden = false,
> +	.die_c6_offset = NVL_PMT_DMU_DIE_C6_OFFSET,
> +};
> +
> +struct pmc_dev_info nvl_h_pmc_dev = {
> +	.pmc_list = nvl_h_pmc_list,
> +	.regmap_list = nvl_pmc_info_list,
> +	.map = &nvl_pcdh_reg_map,
> +	.sub_req_show = &pmc_core_substate_blk_req_fops,
> +	.suspend = cnl_suspend,
> +	.resume = nvl_resume,
> +	.init = nvl_core_init,
> +	.sub_req = pmc_core_pmt_get_blk_sub_req,
> +	.dmu_guids = NVL_PMT_DMU_GUIDS,
> +	.pc_guid = NVL_PMT_PC_GUID,
> +	.pkgc_ltr_blocker_offset = NVL_LTR_BLK_OFFSET,
> +	.pkgc_ltr_blocker_counters = nvl_ltr_block_counter_arr,
> +	.pkgc_blocker_offset = NVL_PKGC_BLK_OFFSET,
> +	.pkgc_blocker_counters = nvl_pkgc_blocker_residency,
> +	.ssram_hidden = false,
> +	.die_c6_offset = NVL_PMT_DMU_DIE_C6_OFFSET,
> +};
> diff --git a/drivers/platform/x86/intel/pmc/ptl.c b/drivers/platform/x86/intel/pmc/ptl.c
> index 538ca5ae2e9ec..d39ae842ddd57 100644
> --- a/drivers/platform/x86/intel/pmc/ptl.c
> +++ b/drivers/platform/x86/intel/pmc/ptl.c
> @@ -137,7 +137,7 @@ static const struct pmc_bit_map *ext_ptl_pcdp_pfear_map[] = {
>  	NULL
>  };
>  
> -static const struct pmc_bit_map ptl_pcdp_ltr_show_map[] = {
> +const struct pmc_bit_map ptl_pcdp_ltr_show_map[] = {
>  	{"SOUTHPORT_A",		CNP_PMC_LTR_SPA},
>  	{"SOUTHPORT_B",		CNP_PMC_LTR_SPB},
>  	{"SATA",		CNP_PMC_LTR_SATA},
> 

-- 
 i.