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Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Amit Kucheria , Thara Gopinath , Bjorn Andersson , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Cc: Richard Acayan Subject: [PATCH v2 3/3] arm64: dts: qcom: sdm670: add thermal zones and thermal devices Date: Tue, 3 Mar 2026 20:45:30 -0500 Message-ID: <20260304014530.27775-4-mailingradian@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260304014530.27775-1-mailingradian@gmail.com> References: <20260304014530.27775-1-mailingradian@gmail.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add thermal zones to safeguard from overheating to high temperatures, along with the thermal sensors (TSENS) and CPU frequency limits (LMh). The temperatures are very high, but should still be safeguard for devices that do not specify their own thermal zones. Signed-off-by: Richard Acayan --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 474 +++++++++++++++++++++++++++ 1 file changed, 474 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index f115bc6e64f3..3a55b24ff93b 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -20,6 +20,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -62,6 +63,7 @@ cpu0: cpu@0 { <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&cpu_pd0>; power-domain-names = "psci"; + #cooling-cells = <2>; next-level-cache = <&l2_0>; l2_0: l2-cache { compatible = "cache"; @@ -89,6 +91,7 @@ cpu1: cpu@100 { <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&cpu_pd1>; power-domain-names = "psci"; + #cooling-cells = <2>; next-level-cache = <&l2_100>; l2_100: l2-cache { compatible = "cache"; @@ -111,6 +114,7 @@ cpu2: cpu@200 { <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&cpu_pd2>; power-domain-names = "psci"; + #cooling-cells = <2>; next-level-cache = <&l2_200>; l2_200: l2-cache { compatible = "cache"; @@ -133,6 +137,7 @@ cpu3: cpu@300 { <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&cpu_pd3>; power-domain-names = "psci"; + #cooling-cells = <2>; next-level-cache = <&l2_300>; l2_300: l2-cache { compatible = "cache"; @@ -155,6 +160,7 @@ cpu4: cpu@400 { <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&cpu_pd4>; power-domain-names = "psci"; + #cooling-cells = <2>; next-level-cache = <&l2_400>; l2_400: l2-cache { compatible = "cache"; @@ -177,6 +183,7 @@ cpu5: cpu@500 { <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&cpu_pd5>; power-domain-names = "psci"; + #cooling-cells = <2>; next-level-cache = <&l2_500>; l2_500: l2-cache { compatible = "cache"; @@ -199,6 +206,7 @@ cpu6: cpu@600 { <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&cpu_pd6>; power-domain-names = "psci"; + #cooling-cells = <2>; next-level-cache = <&l2_600>; l2_600: l2-cache { compatible = "cache"; @@ -221,6 +229,7 @@ cpu7: cpu@700 { <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&cpu_pd7>; power-domain-names = "psci"; + #cooling-cells = <2>; next-level-cache = <&l2_700>; l2_700: l2-cache { compatible = "cache"; @@ -1408,6 +1417,8 @@ gpu: gpu@5000000 { nvmem-cells = <&gpu_speed_bin>; nvmem-cell-names = "speed_bin"; + #cooling-cells = <2>; + status = "disabled"; gpu_zap_shader: zap-shader { @@ -2100,6 +2111,28 @@ dispcc: clock-controller@af00000 { #power-domain-cells = <1>; }; + tsens0: thermal-sensor@c263000 { + compatible = "qcom,sdm670-tsens", "qcom,tsens-v2"; + reg = <0 0x0c263000 0 0x1ff>, + <0 0x0c222000 0 0x4>; + interrupts-extended = <&pdc 26 IRQ_TYPE_EDGE_RISING>, + <&pdc 28 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + #qcom,sensors = <13>; + }; + + tsens1: thermal-sensor@c265000 { + compatible = "qcom,sdm670-tsens", "qcom,tsens-v2"; + reg = <0 0x0c265000 0 0x1ff>, + <0 0x0c223000 0 0x4>; + interrupts-extended = <&pdc 27 IRQ_TYPE_EDGE_RISING>, + <&pdc 29 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + #qcom,sensors = <8>; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sdm670-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x80000>; @@ -2289,5 +2322,446 @@ cpufreq_hw: cpufreq@17d43000 { #freq-domain-cells = <1>; }; + + lmh_cluster1: lmh@17d70800 { + compatible = "qcom,sdm670-lmh", "qcom,sdm845-lmh"; + reg = <0 0x17d70800 0 0x400>; + interrupts = ; + cpus = <&cpu6>; + qcom,lmh-temp-arm-millicelsius = <65000>; + qcom,lmh-temp-low-millicelsius = <94500>; + qcom,lmh-temp-high-millicelsius = <95000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + lmh_cluster0: lmh@17d78800 { + compatible = "qcom,sdm670-lmh", "qcom,sdm845-lmh"; + reg = <0 0x17d78800 0 0x400>; + interrupts = ; + cpus = <&cpu0>; + qcom,lmh-temp-arm-millicelsius = <65000>; + qcom,lmh-temp-low-millicelsius = <94500>; + qcom,lmh-temp-high-millicelsius = <95000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + thermal-zones { + aoss0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 0>; + + trips { + aoss0_crit: trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 1>; + + trips { + cpu0_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu0_crit: trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 2>; + + trips { + cpu1_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu1_crit: trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 3>; + + trips { + cpu2_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu2_crit: trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 4>; + + trips { + cpu3_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu3_crit: trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cluster0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 5>; + + trips { + cluster0_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; + }; + + cluster0_crit: trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cluster1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 6>; + + trips { + cluster1_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; + }; + + cluster1_crit: trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu4-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 7>; + + trips { + cpu4_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu4_crit: trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu5-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 8>; + + trips { + cpu5_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu5_crit: trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu6-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 9>; + + trips { + cpu6_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu6_crit: trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 10>; + + trips { + cpu7_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; + }; + + cpu7_crit: trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 11>; + + cooling-maps { + map0 { + trip = <&gpu0_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + gpu0_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; + }; + + gpu0_crit: trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 12>; + + cooling-maps { + map0 { + trip = <&gpu1_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + gpu1_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; + }; + + gpu1_crit: trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 0>; + + trips { + aoss1_crit: trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + q6-modem-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 1>; + + trips { + q6_modem_crit: trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + mem-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 2>; + + cooling-maps { + map0 { + trip = <&mem_alert0>; + cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + mem_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; + }; + + mem_crit: trip-point1 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + wlan-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 3>; + + trips { + wlan_crit: trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + q6-hvx-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 4>; + + trips { + q6_hvx_crit: trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + camera-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 5>; + + trips { + camera_crit: trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + video-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 6>; + + trips { + video_crit: trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + modem-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens1 7>; + + trips { + modem_crit: trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; }; }; -- 2.53.0