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Tue, 17 Mar 2026 08:10:55 -0700 From: Sumit Gupta To: , , , , , , , , , , , , CC: , , , , , , , , , Subject: [PATCH] cpufreq: CPPC: add autonomous mode boot parameter support Date: Tue, 17 Mar 2026 20:40:52 +0530 Message-ID: <20260317151053.2361475-1-sumitg@nvidia.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000055DB:EE_|CH3PR12MB8307:EE_ X-MS-Office365-Filtering-Correlation-Id: fc60729a-8e31-4f0f-d6aa-08de843774be X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700016|7416014|376014|921020|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: FC1Q+OA+vKKNnOyf8s7LlQPFxvN/xeqPtLK/2cOJWrGQNVWpBnMU1S9nYb6T/0LOzfG87K8mKSqVCeAEmif9uz4fKH+U9OrYk0C4A4ujnVsp/D75HUdnfT/dbf0Uxo4W00Fu7I9icDm6BuppVsrXViAg1kbx75aWJj63dvuYghAbI4T1O41ZBLfkH3ed5w+HGbyxpuiko0/VFbykPJcJViZXgm+aBFH15ZhDo9DJkjq6eJEmf11NmgDtwAboX+hChPhLWGDJ2fAhFhzA0HmZKAsXi9ltRvQRe5olqGJWEywPim6z1Fj53lEWrvTFZ3T9KQAqdWOkXoSJChQV0xxruCI+pt1sdDV3RVgQyCep5gs80ClflRtvLcnxnoaX3mzIZhVLpc+H7NOPCEC7nqedDiK9YIWm8f9YEdoT4NNvzDXAIOI+d5ydPdHxTpmkdP43Qpl5x8ACkzlRILcwkgCKI0AWN9byDslDHKDf4tzRXLoPi5zATW1Tl4o38ZhfnHIaIaWV2aYeAiWuwMSyDPenbJ+Vx5Ts+YlupPdGIkLnENb05RNomRRtLQY6qRtp+g2v3tsKvtDTAHJWS/KQi6DFiBj86oxQtBlZ30OEXylr/m1I7mGgS3IdqHF6XJxPpDlgP+1QMwC/L3miptucYug8eRBhpPafOTYZ9Pi3BHexG9QyWECyTcLnUPQBzj6cHuifNE1nLCVeokIPO8GmXBVWjbKMbcPT/Cg/259VbmuyiRHFCn2KGkizi6lsdfDrOwJVGe5ypzGUbob2Xizc3mYF3Y9y1NOuHZ7pNMU1dsq7+8iS3UuAsOskwbttSXZFd5rP X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700016)(7416014)(376014)(921020)(56012099003)(18002099003);DIR:OUT;SFP:1101; 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When autonomous mode is enabled, the hardware automatically adjusts CPU performance based on workload demands using Energy Performance Preference (EPP) hints. When auto_sel_mode=1: - Configure all CPUs for autonomous operation on first init - Set EPP to performance preference (0x0) - Use HW min/max when set; otherwise program from policy limits (caps) - Clamp desired_perf to bounds before enabling autonomous mode - Hardware controls frequency instead of the OS governor The boot parameter is applied only during first policy initialization. On hotplug, skip applying it so that the user's runtime sysfs configuration is preserved. Reviewed-by: Randy Dunlap (Documentation) Signed-off-by: Sumit Gupta --- Part 1 [1] of this series was applied for 7.1 and present in next. Sending this patch as reworked version of 'patch 11' from [2] based on next. [1] https://lore.kernel.org/lkml/20260206142658.72583-1-sumitg@nvidia.com/ [2] https://lore.kernel.org/lkml/20251223121307.711773-1-sumitg@nvidia.com/ --- .../admin-guide/kernel-parameters.txt | 13 +++ drivers/cpufreq/cppc_cpufreq.c | 84 +++++++++++++++++-- 2 files changed, 92 insertions(+), 5 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index fa6171b5fdd5..de4b4c89edfe 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1060,6 +1060,19 @@ Kernel parameters policy to use. This governor must be registered in the kernel before the cpufreq driver probes. + cppc_cpufreq.auto_sel_mode= + [CPU_FREQ] Enable ACPI CPPC autonomous performance + selection. When enabled, hardware automatically adjusts + CPU frequency on all CPUs based on workload demands. + In Autonomous mode, Energy Performance Preference (EPP) + hints guide hardware toward performance (0x0) or energy + efficiency (0xff). + Requires ACPI CPPC autonomous selection register support. + Format: + Default: 0 (disabled) + 0: use cpufreq governors + 1: enable if supported by hardware + cpu_init_udelay=N [X86,EARLY] Delay for N microsec between assert and de-assert of APIC INIT to start processors. This delay occurs diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index 5dfb109cf1f4..49c148b2a0a4 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -28,6 +28,9 @@ static struct cpufreq_driver cppc_cpufreq_driver; +/* Autonomous Selection boot parameter */ +static bool auto_sel_mode; + #ifdef CONFIG_ACPI_CPPC_CPUFREQ_FIE static enum { FIE_UNSET = -1, @@ -708,11 +711,74 @@ static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy) policy->cur = cppc_perf_to_khz(caps, caps->highest_perf); cpu_data->perf_ctrls.desired_perf = caps->highest_perf; - ret = cppc_set_perf(cpu, &cpu_data->perf_ctrls); - if (ret) { - pr_debug("Err setting perf value:%d on CPU:%d. ret:%d\n", - caps->highest_perf, cpu, ret); - goto out; + /* + * Enable autonomous mode on first init if boot param is set. + * Check last_governor to detect first init and skip if auto_sel + * is already enabled. + */ + if (auto_sel_mode && policy->last_governor[0] == '\0' && + !cpu_data->perf_ctrls.auto_sel) { + /* Enable CPPC - optional register, some platforms need it */ + ret = cppc_set_enable(cpu, true); + if (ret && ret != -EOPNOTSUPP) + pr_warn("Failed to enable CPPC for CPU%d (%d)\n", cpu, ret); + + /* + * Prefer HW min/max_perf when set; otherwise program from + * policy limits derived earlier from caps. + * Clamp desired_perf to bounds and sync policy->cur. + */ + if (!cpu_data->perf_ctrls.min_perf || !cpu_data->perf_ctrls.max_perf) + cppc_cpufreq_update_perf_limits(cpu_data, policy); + + cpu_data->perf_ctrls.desired_perf = + clamp_t(u32, cpu_data->perf_ctrls.desired_perf, + cpu_data->perf_ctrls.min_perf, + cpu_data->perf_ctrls.max_perf); + + policy->cur = cppc_perf_to_khz(caps, + cpu_data->perf_ctrls.desired_perf); + + /* EPP is optional - some platforms may not support it */ + ret = cppc_set_epp(cpu, CPPC_EPP_PERFORMANCE_PREF); + if (ret && ret != -EOPNOTSUPP) + pr_warn("Failed to set EPP for CPU%d (%d)\n", cpu, ret); + else if (!ret) + cpu_data->perf_ctrls.energy_perf = CPPC_EPP_PERFORMANCE_PREF; + + ret = cppc_set_perf(cpu, &cpu_data->perf_ctrls); + if (ret) { + pr_debug("Err setting perf for autonomous mode CPU:%d ret:%d\n", + cpu, ret); + goto out; + } + + ret = cppc_set_auto_sel(cpu, true); + if (ret && ret != -EOPNOTSUPP) { + pr_warn("Failed autonomous config for CPU%d (%d)\n", + cpu, ret); + goto out; + } + if (!ret) + cpu_data->perf_ctrls.auto_sel = true; + } + + if (cpu_data->perf_ctrls.auto_sel) { + /* Sync policy limits from HW when autonomous mode is active */ + policy->min = cppc_perf_to_khz(caps, + cpu_data->perf_ctrls.min_perf ?: + caps->lowest_nonlinear_perf); + policy->max = cppc_perf_to_khz(caps, + cpu_data->perf_ctrls.max_perf ?: + caps->nominal_perf); + } else { + /* Normal mode: governors control frequency */ + ret = cppc_set_perf(cpu, &cpu_data->perf_ctrls); + if (ret) { + pr_debug("Err setting perf value:%d on CPU:%d. ret:%d\n", + caps->highest_perf, cpu, ret); + goto out; + } } cppc_cpufreq_cpu_fie_init(policy); @@ -1038,10 +1104,18 @@ static int __init cppc_cpufreq_init(void) static void __exit cppc_cpufreq_exit(void) { + unsigned int cpu; + + for_each_present_cpu(cpu) + cppc_set_auto_sel(cpu, false); + cpufreq_unregister_driver(&cppc_cpufreq_driver); cppc_freq_invariance_exit(); } +module_param(auto_sel_mode, bool, 0444); +MODULE_PARM_DESC(auto_sel_mode, "Enable CPPC autonomous performance selection at boot"); + module_exit(cppc_cpufreq_exit); MODULE_AUTHOR("Ashwin Chaugule"); MODULE_DESCRIPTION("CPUFreq driver based on the ACPI CPPC v5.0+ spec"); -- 2.34.1