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Sun, 29 Mar 2026 00:06:56 -0700 (PDT) From: aravindanilraj0702@gmail.com To: rafael@kernel.org Cc: daniel.lezcano@kernel.org, rui.zhang@intel.com, lukasz.luba@arm.com, srinivas.pandruvada@linux.intel.com, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Aravind Anilraj Subject: [PATCH v2 1/2] thermal: intel: int340x: Fix potential shift overflow in ptc_mmio_write Date: Sun, 29 Mar 2026 03:06:41 -0400 Message-ID: <20260329070642.10721-2-aravindanilraj0702@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260329070642.10721-1-aravindanilraj0702@gmail.com> References: <20260329070642.10721-1-aravindanilraj0702@gmail.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Aravind Anilraj The value parameter is u32 but is shifted into a u64 register value without casting first. If the shift amount pushes bits beyond 32, they are lost. Cast value to u64 before shifting to ensure all bits are preserved. Signed-off-by: Aravind Anilraj --- .../intel/int340x_thermal/platform_temperature_control.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/thermal/intel/int340x_thermal/platform_temperature_control.c b/drivers/thermal/intel/int340x_thermal/platform_temperature_control.c index 0ccc72c93499..18ac5014d8dc 100644 --- a/drivers/thermal/intel/int340x_thermal/platform_temperature_control.c +++ b/drivers/thermal/intel/int340x_thermal/platform_temperature_control.c @@ -138,7 +138,7 @@ static void ptc_mmio_write(struct pci_dev *pdev, u32 offset, int index, u32 valu reg_val = readq((void __iomem *) (proc_priv->mmio_base + offset)); reg_val &= ~mask; - reg_val |= (value << ptc_mmio_regs[index].shift); + reg_val |= ((u64)value << ptc_mmio_regs[index].shift); writeq(reg_val, (void __iomem *) (proc_priv->mmio_base + offset)); } -- 2.47.3