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(unknown []) by gzsmtp3 (Coremail) with SMTP id PigvCgA3t7MPhPNpY8phBw--.45309S3; Fri, 01 May 2026 00:32:19 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: ray.huang@amd.com, mario.limonciello@amd.com, rafael@kernel.org, viresh.kumar@linaro.org, sven@kernel.org, j@jannau.net Cc: perry.yuan@amd.com, kprateek.nayak@amd.com, neal@gompa.dev, linux-pm@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [PATCH 1/2] cpufreq/amd-pstate: Use FIELD_MODIFY() Date: Fri, 1 May 2026 00:32:12 +0800 Message-Id: <20260430163213.44695-2-18255117159@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260430163213.44695-1-18255117159@163.com> References: <20260430163213.44695-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID:PigvCgA3t7MPhPNpY8phBw--.45309S3 X-Coremail-Antispam: 1Uf129KBjvJXoWxZr48KF4xKF45JFW5tw4rAFb_yoW5Aw4DpF W5CF4Iyr4Yqa1DtF43Ga1UWr1FqF1qkw4DJanIq397W3W5A3yUXa4vyw1UW34UZFyqgw15 uayUXFW3Ga1Sv3JanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pRa9akUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbC6xR9IWnzhBSRRgAA3+ Use FIELD_MODIFY() to remove open-coded bit manipulation. No functional change intended. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/cpufreq/amd-pstate.c | 26 ++++++++++---------------- 1 file changed, 10 insertions(+), 16 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 453084c67327..1037d1722263 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -246,12 +246,10 @@ static int msr_update_perf(struct cpufreq_policy *policy, u8 min_perf, value = prev = READ_ONCE(cpudata->cppc_req_cached); - value &= ~(AMD_CPPC_MAX_PERF_MASK | AMD_CPPC_MIN_PERF_MASK | - AMD_CPPC_DES_PERF_MASK | AMD_CPPC_EPP_PERF_MASK); - value |= FIELD_PREP(AMD_CPPC_MAX_PERF_MASK, max_perf); - value |= FIELD_PREP(AMD_CPPC_DES_PERF_MASK, des_perf); - value |= FIELD_PREP(AMD_CPPC_MIN_PERF_MASK, min_perf); - value |= FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, epp); + FIELD_MODIFY(AMD_CPPC_MAX_PERF_MASK, &value, max_perf); + FIELD_MODIFY(AMD_CPPC_DES_PERF_MASK, &value, des_perf); + FIELD_MODIFY(AMD_CPPC_MIN_PERF_MASK, &value, min_perf); + FIELD_MODIFY(AMD_CPPC_EPP_PERF_MASK, &value, epp); if (trace_amd_pstate_epp_perf_enabled()) { union perf_cached perf = READ_ONCE(cpudata->perf); @@ -300,8 +298,7 @@ static int msr_set_epp(struct cpufreq_policy *policy, u8 epp) int ret; value = prev = READ_ONCE(cpudata->cppc_req_cached); - value &= ~AMD_CPPC_EPP_PERF_MASK; - value |= FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, epp); + FIELD_MODIFY(AMD_CPPC_EPP_PERF_MASK, &value, epp); if (trace_amd_pstate_epp_perf_enabled()) { union perf_cached perf = cpudata->perf; @@ -441,8 +438,7 @@ static int shmem_set_epp(struct cpufreq_policy *policy, u8 epp) } value = READ_ONCE(cpudata->cppc_req_cached); - value &= ~AMD_CPPC_EPP_PERF_MASK; - value |= FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, epp); + FIELD_MODIFY(AMD_CPPC_EPP_PERF_MASK, &value, epp); WRITE_ONCE(cpudata->cppc_req_cached, value); return ret; @@ -575,12 +571,10 @@ static int shmem_update_perf(struct cpufreq_policy *policy, u8 min_perf, value = prev = READ_ONCE(cpudata->cppc_req_cached); - value &= ~(AMD_CPPC_MAX_PERF_MASK | AMD_CPPC_MIN_PERF_MASK | - AMD_CPPC_DES_PERF_MASK | AMD_CPPC_EPP_PERF_MASK); - value |= FIELD_PREP(AMD_CPPC_MAX_PERF_MASK, max_perf); - value |= FIELD_PREP(AMD_CPPC_DES_PERF_MASK, des_perf); - value |= FIELD_PREP(AMD_CPPC_MIN_PERF_MASK, min_perf); - value |= FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, epp); + FIELD_MODIFY(AMD_CPPC_MAX_PERF_MASK, &value, max_perf); + FIELD_MODIFY(AMD_CPPC_DES_PERF_MASK, &value, des_perf); + FIELD_MODIFY(AMD_CPPC_MIN_PERF_MASK, &value, min_perf); + FIELD_MODIFY(AMD_CPPC_EPP_PERF_MASK, &value, epp); if (trace_amd_pstate_epp_perf_enabled()) { union perf_cached perf = READ_ONCE(cpudata->perf); -- 2.34.1