From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5932A364052; Wed, 6 May 2026 21:53:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778104396; cv=none; b=SheBDaqtodw1fWa90EdEBK5muMOU7rLR9F/S+nAGwCs26q5VUiZa9ZKc1T0JHYS72qbTuEOdwxGftp5+yUz7oJ3Q5J/4e6VRvW82GmaGiffKO7DrcrJ+/ggkrSQ+OWsd3TTkpkf/S+57Xb8Er6+T+qt60GDwKU3PJH998ALidBA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778104396; c=relaxed/simple; bh=heY35TckZke+1W0qxIFdYfwKBHO6XvixKMHPpFriOG0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KC6nSMbVu6PSORVPiMK8zVkGtYmpeXcJYE7/mldNd5nuWCxXsEBKjWMpO52PUfG25hlrar4qh75D01yTq9ANNdfLAL6yms5N3GaoyMiLJAabIHubhNwseHrUV5BnJTz41rFPi1X+JC0HPHb5JFh+8GdJuw97iwqfXD/NzjLgr5Q= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=d8vQCafJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="d8vQCafJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id F17D1C2BCB2; Wed, 6 May 2026 21:53:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778104396; bh=heY35TckZke+1W0qxIFdYfwKBHO6XvixKMHPpFriOG0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=d8vQCafJGQjKD+nnxawV9t99PpADxI7dQk3LOhS3AVq2hIMg6lBjPSVRWpWpPOO+X uauLiJpqMkFD4kZgApZzNh0aONJd/DEo9Z8Lf02JKZ1dpj/dT5Ame3/P02H1C0jJzx HMXPbj/50HTS7HwOiG4HV44n84PcFvA0Bf9LEz6yPOs7sjyCjOZyH1ULxB2eTYs9kV i3JPZZAZNvhEIqiJLkJNGjgwJavpKvnmzr1/MnKi63WTEi/kJpzElHDfM41uUpySK5 PDYFpqZhzRX9syzM4dK0O5Lg3aIzbpwWYBpj2cPYlBNBwcMO/l7liXSev9/9A+nQ5e FOYtGGyxLBDqw== From: Danilo Krummrich To: gregkh@linuxfoundation.org, rafael@kernel.org, acourbot@nvidia.com, aliceryhl@google.com, david.m.ertman@intel.com, ira.weiny@intel.com, leon@kernel.org, viresh.kumar@linaro.org, m.wilczynski@samsung.com, ukleinek@kernel.org, bhelgaas@google.com, kwilczynski@kernel.org, abdiel.janulgue@gmail.com, robin.murphy@arm.com, markus.probst@posteo.de, ojeda@kernel.org, boqun@kernel.org, gary@garyguo.net, bjorn3_gh@protonmail.com, lossin@kernel.org, a.hindborg@kernel.org, tmgross@umich.edu, igor.korotin@linux.dev, daniel.almeida@collabora.com Cc: driver-core@lists.linux.dev, linux-kernel@vger.kernel.org, nova-gpu@lists.linux.dev, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org, linux-pwm@vger.kernel.org, linux-pci@vger.kernel.org, rust-for-linux@vger.kernel.org, Danilo Krummrich Subject: [PATCH v2 17/25] rust: pci: make Bar lifetime-parameterized Date: Wed, 6 May 2026 23:50:53 +0200 Message-ID: <20260506215113.851360-18-dakr@kernel.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260506215113.851360-1-dakr@kernel.org> References: <20260506215113.851360-1-dakr@kernel.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Convert pci::Bar to pci::Bar<'bound, SIZE>, storing &'bound Device to tie the BAR mapping lifetime to the device. iomap_region_sized() now returns Result> directly instead of impl PinInit>, Error>. Add Bar::into_devres() to consume the bar and register it as a device-managed resource, returning Devres>. The lifetime is erased to 'static because Devres guarantees the bar does not actually outlive the device -- access is revoked on unbind. Signed-off-by: Danilo Krummrich --- drivers/gpu/nova-core/driver.rs | 7 ++-- rust/kernel/devres.rs | 2 +- rust/kernel/pci/io.rs | 68 +++++++++++++++++---------------- samples/rust/rust_driver_pci.rs | 5 ++- 4 files changed, 44 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/nova-core/driver.rs b/drivers/gpu/nova-core/driver.rs index ed154cd93fa8..6ee2021ef56e 100644 --- a/drivers/gpu/nova-core/driver.rs +++ b/drivers/gpu/nova-core/driver.rs @@ -47,7 +47,7 @@ pub(crate) struct NovaCore { // DMA addresses. These systems should be quite rare. const GPU_DMA_BITS: u32 = 47; -pub(crate) type Bar0 = pci::Bar; +pub(crate) type Bar0 = pci::Bar<'static, BAR0_SIZE>; kernel::pci_device_table!( PCI_TABLE, @@ -93,8 +93,9 @@ fn probe( // other threads of execution. unsafe { pdev.dma_set_mask_and_coherent(DmaMask::new::())? }; - let bar = Arc::pin_init( - pdev.iomap_region_sized::(0, c"nova-core/bar0"), + let bar = Arc::new( + pdev.iomap_region_sized::(0, c"nova-core/bar0")? + .into_devres()?, GFP_KERNEL, )?; diff --git a/rust/kernel/devres.rs b/rust/kernel/devres.rs index 9e5f93aed20c..ec63317665f4 100644 --- a/rust/kernel/devres.rs +++ b/rust/kernel/devres.rs @@ -304,7 +304,7 @@ pub fn device(&self) -> &Device { /// pci, // /// }; /// - /// fn from_core(dev: &pci::Device, devres: Devres>) -> Result { + /// fn from_core(dev: &pci::Device, devres: Devres>) -> Result { /// let bar = devres.access(dev.as_ref())?; /// /// let _ = bar.read32(0x0); diff --git a/rust/kernel/pci/io.rs b/rust/kernel/pci/io.rs index ae78676c927f..5668394a155b 100644 --- a/rust/kernel/pci/io.rs +++ b/rust/kernel/pci/io.rs @@ -14,8 +14,7 @@ Mmio, MmioRaw, // }, - prelude::*, - sync::aref::ARef, // + prelude::*, // }; use core::{ marker::PhantomData, @@ -78,15 +77,15 @@ impl ConfigSpaceKind for Extended { /// The generic parameter `S` indicates the maximum size of the configuration space. /// Use [`Normal`] for 256-byte legacy configuration space or [`Extended`] for /// 4096-byte PCIe extended configuration space (default). -pub struct ConfigSpace<'a, S: ConfigSpaceKind = Extended> { - pub(crate) pdev: &'a Device, +pub struct ConfigSpace<'bound, S: ConfigSpaceKind = Extended> { + pub(crate) pdev: &'bound Device, _marker: PhantomData, } /// Implements [`IoCapable`] on [`ConfigSpace`] for `$ty` using `$read_fn` and `$write_fn`. macro_rules! impl_config_space_io_capable { ($ty:ty, $read_fn:ident, $write_fn:ident) => { - impl<'a, S: ConfigSpaceKind> IoCapable<$ty> for ConfigSpace<'a, S> { + impl<'bound, S: ConfigSpaceKind> IoCapable<$ty> for ConfigSpace<'bound, S> { unsafe fn io_read(&self, address: usize) -> $ty { let mut val: $ty = 0; @@ -119,7 +118,7 @@ unsafe fn io_write(&self, value: $ty, address: usize) { impl_config_space_io_capable!(u16, pci_read_config_word, pci_write_config_word); impl_config_space_io_capable!(u32, pci_read_config_dword, pci_write_config_dword); -impl<'a, S: ConfigSpaceKind> Io for ConfigSpace<'a, S> { +impl<'bound, S: ConfigSpaceKind> Io for ConfigSpace<'bound, S> { /// Returns the base address of the I/O region. It is always 0 for configuration space. #[inline] fn addr(&self) -> usize { @@ -133,7 +132,7 @@ fn maxsize(&self) -> usize { } } -impl<'a, S: ConfigSpaceKind> IoKnownSize for ConfigSpace<'a, S> { +impl<'bound, S: ConfigSpaceKind> IoKnownSize for ConfigSpace<'bound, S> { const MIN_SIZE: usize = S::SIZE; } @@ -146,14 +145,14 @@ impl<'a, S: ConfigSpaceKind> IoKnownSize for ConfigSpace<'a, S> { /// /// `Bar` always holds an `IoRaw` instance that holds a valid pointer to the start of the I/O /// memory mapped PCI BAR and its size. -pub struct Bar { - pdev: ARef, +pub struct Bar<'bound, const SIZE: usize = 0> { + pdev: &'bound Device, io: MmioRaw, num: i32, } -impl Bar { - pub(super) fn new(pdev: &Device, num: u32, name: &CStr) -> Result { +impl<'bound, const SIZE: usize> Bar<'bound, SIZE> { + pub(super) fn new(pdev: &'bound Device, num: u32, name: &CStr) -> Result { let len = pdev.resource_len(num)?; if len == 0 { return Err(ENOMEM); @@ -196,11 +195,7 @@ pub(super) fn new(pdev: &Device, num: u32, name: &CStr) -> Result { } }; - Ok(Bar { - pdev: pdev.into(), - io, - num, - }) + Ok(Bar { pdev, io, num }) } /// # Safety @@ -219,11 +214,24 @@ unsafe fn do_release(pdev: &Device, ioptr: usize, num: i32) { fn release(&self) { // SAFETY: The safety requirements are guaranteed by the type invariant of `self.pdev`. - unsafe { Self::do_release(&self.pdev, self.io.addr(), self.num) }; + unsafe { Self::do_release(self.pdev, self.io.addr(), self.num) }; + } + + /// Consume the `Bar` and register it as a device-managed resource. + /// + /// The returned `Devres>` can outlive the original lifetime `'bound`. Access + /// to the BAR is revoked when the device is unbound. + pub fn into_devres(self) -> Result>> { + // SAFETY: Casting to `'static` is sound because `Devres` guarantees the `Bar` does not + // actually outlive the device -- access is revoked and the resource is released when the + // device is unbound. + let bar: Bar<'static, SIZE> = unsafe { core::mem::transmute(self) }; + let pdev = bar.pdev; + Devres::new(pdev.as_ref(), bar) } } -impl Bar { +impl Bar<'_> { #[inline] pub(super) fn index_is_valid(index: u32) -> bool { // A `struct pci_dev` owns an array of resources with at most `PCI_NUM_RESOURCES` entries. @@ -231,13 +239,13 @@ pub(super) fn index_is_valid(index: u32) -> bool { } } -impl Drop for Bar { +impl Drop for Bar<'_, SIZE> { fn drop(&mut self) { self.release(); } } -impl Deref for Bar { +impl Deref for Bar<'_, SIZE> { type Target = Mmio; fn deref(&self) -> &Self::Target { @@ -249,20 +257,16 @@ fn deref(&self) -> &Self::Target { impl Device { /// Maps an entire PCI BAR after performing a region-request on it. I/O operation bound checks /// can be performed on compile time for offsets (plus the requested type size) < SIZE. - pub fn iomap_region_sized<'a, const SIZE: usize>( - &'a self, + pub fn iomap_region_sized<'bound, const SIZE: usize>( + &'bound self, bar: u32, - name: &'a CStr, - ) -> impl PinInit>, Error> + 'a { - Devres::new(self.as_ref(), Bar::::new(self, bar, name)) + name: &CStr, + ) -> Result> { + Bar::new(self, bar, name) } /// Maps an entire PCI BAR after performing a region-request on it. - pub fn iomap_region<'a>( - &'a self, - bar: u32, - name: &'a CStr, - ) -> impl PinInit, Error> + 'a { + pub fn iomap_region<'bound>(&'bound self, bar: u32, name: &CStr) -> Result> { self.iomap_region_sized::<0>(bar, name) } @@ -282,7 +286,7 @@ pub fn cfg_size(&self) -> ConfigSpaceSize { } /// Return an initialized normal (256-byte) config space object. - pub fn config_space<'a>(&'a self) -> ConfigSpace<'a, Normal> { + pub fn config_space<'bound>(&'bound self) -> ConfigSpace<'bound, Normal> { ConfigSpace { pdev: self, _marker: PhantomData, @@ -290,7 +294,7 @@ pub fn config_space<'a>(&'a self) -> ConfigSpace<'a, Normal> { } /// Return an initialized extended (4096-byte) config space object. - pub fn config_space_extended<'a>(&'a self) -> Result> { + pub fn config_space_extended<'bound>(&'bound self) -> Result> { if self.cfg_size() != ConfigSpaceSize::Extended { return Err(EINVAL); } diff --git a/samples/rust/rust_driver_pci.rs b/samples/rust/rust_driver_pci.rs index 794311691d1e..bbcb816456e0 100644 --- a/samples/rust/rust_driver_pci.rs +++ b/samples/rust/rust_driver_pci.rs @@ -45,7 +45,7 @@ mod regs { pub(super) const END: usize = 0x10; } -type Bar0 = pci::Bar<{ regs::END }>; +type Bar0 = pci::Bar<'static, { regs::END }>; #[derive(Copy, Clone, Debug)] struct TestIndex(u8); @@ -160,7 +160,8 @@ fn probe( pdev.set_master(); Ok(try_pin_init!(Self { - bar <- pdev.iomap_region_sized::<{ regs::END }>(0, c"rust_driver_pci"), + bar: pdev.iomap_region_sized::<{ regs::END }>(0, c"rust_driver_pci")? + .into_devres()?, index: *info, _: { let bar = bar.access(pdev.as_ref())?; -- 2.54.0