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Wysocki" , Viresh Kumar , linux-pm@vger.kernel.org Cc: Thierry Reding , Jonathan Hunter , linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Myeonghun Pak , Ijae Kim Subject: [PATCH] cpufreq: tegra124: Disable DFLL clock on removal Date: Fri, 26 Jun 2026 18:30:14 +0900 Message-Id: <20260626093014.66092-1-mhun512@gmail.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit tegra124_cpu_switch_to_dfll() enables the DFLL clock before switching the CPU clock parent to it. If cpufreq_dt_pdev_register() fails after that point, or when the driver is removed, the driver only drops clock references and never disables the enabled DFLL clock. Add a helper for switching the CPU back to PLLP and disabling DFLL, then use it in the post-DFLL probe unwind path and in remove. Fixes: 9f5ed5fe6060 ("cpufreq: tegra124: do not handle the CPU rail") Co-developed-by: Ijae Kim Signed-off-by: Ijae Kim Signed-off-by: Myeonghun Pak --- drivers/cpufreq/tegra124-cpufreq.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/tegra124-cpufreq.c b/drivers/cpufreq/tegra124-cpufreq.c index f8a76bbec..1fb3bf50b 100644 --- a/drivers/cpufreq/tegra124-cpufreq.c +++ b/drivers/cpufreq/tegra124-cpufreq.c @@ -54,12 +54,25 @@ return ret; } +static int tegra124_cpu_disable_dfll(struct tegra124_cpufreq_priv *priv) +{ + int ret; + + ret = clk_set_parent(priv->cpu_clk, priv->pllp_clk); + if (ret) + return ret; + + clk_disable_unprepare(priv->dfll_clk); + + return 0; +} + static int tegra124_cpufreq_probe(struct platform_device *pdev) { struct device_node *np __free(device_node) = of_cpu_device_node_get(0); struct tegra124_cpufreq_priv *priv; struct device *cpu_dev; - int ret; + int err, ret; if (!np) return -ENODEV; @@ -101,13 +114,17 @@ priv->cpufreq_dt_pdev = cpufreq_dt_pdev_register(&pdev->dev); if (IS_ERR(priv->cpufreq_dt_pdev)) { ret = PTR_ERR(priv->cpufreq_dt_pdev); - goto out_put_pllp_clk; + goto out_disable_dfll; } platform_set_drvdata(pdev, priv); return 0; +out_disable_dfll: + err = tegra124_cpu_disable_dfll(priv); + if (err) + dev_err(&pdev->dev, "failed to disable DFLL clock: %d\n", err); out_put_pllp_clk: clk_put(priv->pllp_clk); out_put_pllx_clk: @@ -175,12 +192,17 @@ static void tegra124_cpufreq_remove(struct platform_device *pdev) { struct tegra124_cpufreq_priv *priv = dev_get_drvdata(&pdev->dev); + int err; if (!IS_ERR(priv->cpufreq_dt_pdev)) { platform_device_unregister(priv->cpufreq_dt_pdev); priv->cpufreq_dt_pdev = ERR_PTR(-ENODEV); } + err = tegra124_cpu_disable_dfll(priv); + if (err) + dev_err(&pdev->dev, "failed to disable DFLL clock: %d\n", err); + clk_put(priv->pllp_clk); clk_put(priv->pllx_clk); clk_put(priv->dfll_clk); -- 2.39.5