From: Jonathan Cameron <jic23@kernel.org>
To: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Cc: "David Lechner" <dlechner@baylibre.com>,
"Nuno Sá" <nuno.sa@analog.com>,
"Andy Shevchenko" <andy@kernel.org>,
"Amit Kucheria" <amitk@kernel.org>,
"Thara Gopinath" <thara.gopinath@gmail.com>,
"Rafael J. Wysocki" <rafael@kernel.org>,
"Daniel Lezcano" <daniel.lezcano@kernel.org>,
"Zhang Rui" <rui.zhang@intel.com>,
"Lukasz Luba" <lukasz.luba@arm.com>,
linux-arm-msm@vger.kernel.org, linux-iio@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org,
"Kamal Wadhwa" <kamal.wadhwa@oss.qualcomm.com>,
"David Collins" <david.collins@oss.qualcomm.com>,
"Anjelique Melendez" <anjelique.melendez@oss.qualcomm.com>,
"Neil Armstrong" <neil.armstrong@linaro.org>,
"Stephan Gerhold" <stephan.gerhold@linaro.org>
Subject: Re: [PATCH v3 3/3] thermal: qcom: add support for PMIC5 Gen3 ADC thermal monitoring
Date: Mon, 6 Jul 2026 00:51:34 +0100 [thread overview]
Message-ID: <20260706005134.7add6bbe@jic23-huawei> (raw)
In-Reply-To: <20260705-gen3_adc_tm-v3-3-ac62f387dbce@oss.qualcomm.com>
On Sun, 05 Jul 2026 22:23:35 +0530
Jishnu Prakash <jishnu.prakash@oss.qualcomm.com> wrote:
> Add support for ADC_TM part of PMIC5 Gen3.
>
> This is an auxiliary driver under the Gen3 ADC driver, which implements the
> threshold setting and interrupt generating functionalities of QCOM ADC_TM
> drivers, used to support thermal trip points.
>
> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Hi Jishnu,
I took a quick look at this. A few really minor suggestions inline.
> diff --git a/drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c b/drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c
> new file mode 100644
> index 000000000000..5a82c4d8a37e
> --- /dev/null
> +++ b/drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c
> +static int adc_tm5_register_tzd(struct adc_tm5_gen3_chip *adc_tm5)
> +{
> + struct thermal_zone_device *tzd;
> + unsigned int channel;
> + int ret;
> +
> + for (int i = 0; i < adc_tm5->nchannels; i++) {
> + channel = ADC5_GEN3_V_CHAN(adc_tm5->chan_props[i].common_props);
> + tzd = devm_thermal_of_zone_register(adc_tm5->dev, channel,
> + &adc_tm5->chan_props[i],
> + &adc_tm_ops);
> + if (IS_ERR(tzd)) {
> + if (PTR_ERR(tzd) == -ENODEV) {
> + dev_info(adc_tm5->dev,
> + "thermal sensor on channel %d is not used\n",
That seems noisy. Maybe dev_dbg() appropriate if this is an expected
board dependent condition?
> + channel);
> + continue;
> + }
> + return dev_err_probe(adc_tm5->dev, PTR_ERR(tzd),
> + "Error registering TZ zone:%ld for channel:%d\n",
> + PTR_ERR(tzd), channel);
> + }
> + adc_tm5->chan_props[i].tzd = tzd;
> + ret = devm_thermal_add_hwmon_sysfs(adc_tm5->dev, tzd);
> + if (ret)
> + return ret;
> + }
> + return 0;
> +}
> +static int adc_tm5_probe(struct auxiliary_device *aux_dev,
> + const struct auxiliary_device_id *id)
> +{
> + struct adc_tm5_gen3_chip *adc_tm5;
> + struct tm5_aux_dev_wrapper *aux_dev_wrapper;
> + struct device *dev = &aux_dev->dev;
> + u32 irq_flags;
> + int ret;
> +
> + adc_tm5 = devm_kzalloc(dev, sizeof(*adc_tm5), GFP_KERNEL);
> + if (!adc_tm5)
> + return -ENOMEM;
> +
> + aux_dev_wrapper = container_of(aux_dev, struct tm5_aux_dev_wrapper, aux_dev);
> +
> + adc_tm5->dev = dev;
> + adc_tm5->dev_data = aux_dev_wrapper->dev_data;
> + adc_tm5->nchannels = aux_dev_wrapper->n_tm_channels;
> + adc_tm5->chan_props = devm_kcalloc(dev, aux_dev_wrapper->n_tm_channels,
> + sizeof(*adc_tm5->chan_props), GFP_KERNEL);
> + if (!adc_tm5->chan_props)
> + return -ENOMEM;
> +
> + for (int i = 0; i < adc_tm5->nchannels; i++) {
> + adc_tm5->chan_props[i].common_props = aux_dev_wrapper->tm_props[i];
> + adc_tm5->chan_props[i].timer = MEAS_INT_1S;
> + adc_tm5->chan_props[i].sdam_index = (i + 1) / 8;
> + adc_tm5->chan_props[i].tm_chan_index = (i + 1) % 8;
> + adc_tm5->chan_props[i].chip = adc_tm5;
> + }
> +
> + /* This is to disable all ADC_TM channels in case of probe failure. */
Perhaps indicate who turned them on? On from reset or something hidden
somewhere else?
> + ret = devm_add_action(dev, adc5_gen3_disable, adc_tm5);
> + if (ret)
> + return ret;
...
> + /*
> + * First SDAM's interrupt is shared between main ADC driver
> + * and auxiliary TM driver, so its flags must include
> + * IRQF_SHARED. This is not needed for other SDAMs as they
> + * will be used only for TM functionality.
If indent of this doesn't change, rewrap to 80 chars.
> + */
> + irq_flags = IRQF_ONESHOT | IRQF_SHARED;
> + for (int i = 0; i < adc_tm5->dev_data->num_sdams; i++) {
> + ret = devm_request_threaded_irq(dev,
> + adc_tm5->dev_data->base[i].irq,
> + adctm5_gen3_isr, adctm5_gen3_isr_thread,
> + irq_flags, adc_tm5->dev_data->base[i].irq_name,
> + adc_tm5);
> + if (ret < 0)
> + return ret;
> + irq_flags = IRQF_ONESHOT;
Whilst this code works, I'd be tempted to make it less ordering dependent. E.g.
for (int i = 0; i < adc_tm5->dev_data->num_sdams; i++) {
u32 irq_flags = IRQF_ONESHOT;
/*
* First SDAM's interrupt is shared between main ADC driver
* and auxiliary TM driver, so its flags must include
* IRQF_SHARED. This is not needed for other SDAMs as they
* will be used only for TM functionality.
*/
if (i == 0)
irq_flags |= IRQF_SHARED;
ret = devm_request_threaded_irq(dev,
> + adc_tm5->dev_data->base[i].irq,
> + adctm5_gen3_isr, adctm5_gen3_isr_thread,
> + irq_flags, adc_tm5->dev_data->base[i].irq_name,
> + adc_tm5);
> + }
> +
> + return 0;
> +}
next prev parent reply other threads:[~2026-07-05 23:51 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-05 16:53 [PATCH v3 0/3] thermal: qcom: add support for PMIC5 Gen3 ADC thermal monitoring Jishnu Prakash
2026-07-05 16:53 ` [PATCH v3 1/3] iio: adc: qcom-spmi-adc5-gen3: Share SDAM0 IRQ with ADC_TM auxiliary driver Jishnu Prakash
2026-07-05 16:53 ` [PATCH v3 2/3] iio: adc: qcom-spmi-adc5-gen3: Remove an unnecessary print Jishnu Prakash
2026-07-05 17:29 ` Joshua Crofts
2026-07-05 17:47 ` Maxwell Doose
2026-07-05 23:41 ` Jonathan Cameron
2026-07-06 5:44 ` Andy Shevchenko
2026-07-05 16:53 ` [PATCH v3 3/3] thermal: qcom: add support for PMIC5 Gen3 ADC thermal monitoring Jishnu Prakash
2026-07-05 23:51 ` Jonathan Cameron [this message]
2026-07-06 5:59 ` Andy Shevchenko
2026-07-05 23:53 ` [PATCH v3 0/3] " Jonathan Cameron
2026-07-06 5:45 ` Andy Shevchenko
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