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From: Jonathan Cameron <jic23@kernel.org>
To: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Cc: "David Lechner" <dlechner@baylibre.com>,
	"Nuno Sá" <nuno.sa@analog.com>,
	"Andy Shevchenko" <andy@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Amit Kucheria" <amitk@kernel.org>,
	"Thara Gopinath" <thara.gopinath@gmail.com>,
	"Rafael J. Wysocki" <rafael@kernel.org>,
	"Daniel Lezcano" <daniel.lezcano@kernel.org>,
	"Zhang Rui" <rui.zhang@intel.com>,
	"Lukasz Luba" <lukasz.luba@arm.com>,
	"Bjorn Andersson" <andersson@kernel.org>,
	"Konrad Dybcio" <konradybcio@kernel.org>,
	linux-iio@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	linux-pm@vger.kernel.org,
	"Kamal Wadhwa" <kamal.wadhwa@oss.qualcomm.com>,
	"Anjelique Melendez" <anjelique.melendez@oss.qualcomm.com>,
	"Manaf Meethalavalappu Pallikunhi"
	<manaf.pallikunhi@oss.qualcomm.com>,
	"Priyansh Jain" <priyansh.jain@oss.qualcomm.com>
Subject: Re: [PATCH 3/7] thermal: qcom: qcom-spmi-adc-tm5-gen3: Add support for QCOM PMIC5 Gen4 ADC
Date: Mon, 3 Aug 2026 01:17:09 +0100	[thread overview]
Message-ID: <20260803011709.31cf83f2@jic23-huawei> (raw)
In-Reply-To: <20260731-pmic5_gen4_adc-v1-3-9c49b2eea6f9@oss.qualcomm.com>

On Fri, 31 Jul 2026 23:36:16 +0530
Jishnu Prakash <jishnu.prakash@oss.qualcomm.com> wrote:

> PMIC5 Gen4 ADC is similar to PMIC5 Gen3 ADC, with several changes made
> for improved performance, mostly at the hardware level.
> 
> One significant software change is that ratiometric conversion resolution
> has been increased from 14 bits to 16 bits. Add a reverse scaling function
> for Gen4 ADC thermistor channels.
> 
> In the latest PMIC arbiter version (v8), there can be up to 4 buses
> under the PMIC arbiter and 32 PMICs under each bus. In order to
> support communication between ADC on the master PMIC and ADCs on any
> of the other PMICs, a field of width 2 bits is added for bus index
> and the bits for SID are extended from 4 to 5 bits, in the SID
> register. Add support for this.
> 
> Co-developed-by: Anjelique Melendez <anjelique.melendez@oss.qualcomm.com>
> Signed-off-by: Anjelique Melendez <anjelique.melendez@oss.qualcomm.com>
> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
Hi Jishnu, Anjelique

Code looks fine, but I just wanted to check.  What happens if
for some reason the patch before ends up in a tree and this one doesn't
Do we read the wrong temperatures given 'bus' isn't specified?

Jonathan


  reply	other threads:[~2026-08-03  0:17 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-31 18:06 [PATCH 0/7] Add support for QCOM SPMI PMIC5 Gen4 ADC Jishnu Prakash
2026-07-31 18:06 ` [PATCH 1/7] dt-bindings: iio: adc: Add support for QCOM " Jishnu Prakash
2026-08-02 23:49   ` Jonathan Cameron
2026-07-31 18:06 ` [PATCH 2/7] iio: adc: qcom-spmi-adc5-gen3: " Jishnu Prakash
2026-08-03  0:14   ` Jonathan Cameron
2026-07-31 18:06 ` [PATCH 3/7] thermal: qcom: qcom-spmi-adc-tm5-gen3: " Jishnu Prakash
2026-08-03  0:17   ` Jonathan Cameron [this message]
2026-07-31 18:06 ` [PATCH 4/7] arm64: dts: qcom: Add header file for ADC5 Gen4 channel macros Jishnu Prakash
2026-07-31 18:06 ` [PATCH 5/7] arm64: dts: qcom: pmk8850: Add ADC5 Gen4 peripheral Jishnu Prakash
2026-07-31 18:06 ` [PATCH 6/7] arm64: dts: qcom: glymur: Add ADC support for Glymur CRD Jishnu Prakash
2026-07-31 18:06 ` [PATCH 7/7] arm64: dts: qcom: kaanapali: Add ADC support for Kaanapali boards Jishnu Prakash

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