From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A48E1392802; Sun, 9 Aug 2026 06:26:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786256810; cv=none; b=tE0W8Sy41FQF3sI5TGsDWYacTcp1dzTmED3w+LhUErgqr/IIsoeqCnRJygsi83SYwl65AMXXAaRyQZsiyIyYGgcATo1eu3q0w1blfGHZo15KVxxkcJTIHMw/VtpC5Rp+i9iu1fudxANCWcakULYQ23Exl6VyBRWmoNvf10GsdbA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786256810; c=relaxed/simple; bh=xOxcLvLMk26sQfeqckO5tKfahU7ocatNC2XNnuTDrsQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RLyrx/ftl2VIJevT7wCVtVXgGJDZoYyyZUXv5GkvVNMQLNdlmqe/6ZaL7DM7901tlcflmtidTfvJYURnLOfq3WVlgnulsOHFCcZMIM0qD10QoTp3dHV7A3xuQ0vTMwWgDiC2mqlLMwAidxGhfm6XyZKdFipvlNpmnkmmWxbyzY0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=eDoe1MwW; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="eDoe1MwW" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BA1241596; Sat, 8 Aug 2026 23:26:43 -0700 (PDT) Received: from e127648.arm.com (unknown [10.57.4.198]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id DBD5D3F9A2; Sat, 8 Aug 2026 23:26:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1786256807; bh=xOxcLvLMk26sQfeqckO5tKfahU7ocatNC2XNnuTDrsQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eDoe1MwWtUDoJ3H5L/hF9NFZ5ygpHUdgXyykW3y5MvpZfryrYNzbuDT9+1F3tQnzC TjLe8CVjqUsJWOX/58S0dIpFwmbupmwH6nQWjCvVHfwF8WRyojn1n9P2fRQG4G8GFt bG94Ga3r4XS1loiwJYaLpUsLfmephAPtvBv7JFic= From: Christian Loehle To: "Rafael J . Wysocki" , Viresh Kumar Cc: linux-pm@vger.kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, Len Brown , Jie Zhan , Lifeng Zheng , Pierre Gondois , Sumit Gupta , Sudeep Holla , Ionela Voinescu , zhongqiu.han@oss.qualcomm.com, Christian Loehle Subject: [PATCH v3 14/15] ACPI: CPPC: Validate SystemIO overlaps across processors Date: Sun, 9 Aug 2026 07:25:48 +0100 Message-Id: <20260809062549.1415955-15-christian.loehle@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260809062549.1415955-1-christian.loehle@arm.com> References: <20260809062549.1415955-1-christian.loehle@arm.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit System I/O port space is global, but the overlap check only compares registers within one _CPC package. Whole-width accesses from different processors can therefore target partially overlapping port ranges and clobber each other. Extend the physical interval registry to SystemIO. Permit read-only overlap and exact full-width aliases of the same logical CPPC entry. Reject every other cross-processor overlap involving a writable entry. Fixes: a2c8f92bea5f ("ACPI: CPPC: Implement support for SystemIO registers") Signed-off-by: Christian Loehle --- drivers/acpi/cppc_acpi.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index a7141f4d9d0f..67d7f81a21b7 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -138,6 +138,7 @@ INTERVAL_TREE_DEFINE(struct cpc_non_mmio_node, rb, u64, subtree_last, cpc_non_mmio_itree) static struct rb_root_cached cpc_pcc_trees[MAX_PCC_SUBSPACES]; +static struct rb_root_cached cpc_sysio_tree = RB_ROOT_CACHED; static DEFINE_MUTEX(cpc_non_mmio_lock); static struct cpc_sysmem_node *cpc_sysmem_first(u64 start, u64 last) @@ -590,6 +591,8 @@ static struct rb_root_cached *cpc_non_mmio_tree(u8 space_id, u8 pcc_ss_id) { if (space_id == ACPI_ADR_SPACE_PLATFORM_COMM) return &cpc_pcc_trees[pcc_ss_id]; + if (space_id == ACPI_ADR_SPACE_SYSTEM_IO) + return &cpc_sysio_tree; return NULL; } @@ -607,7 +610,8 @@ static int cpc_validate_non_mmio_pair(const struct cpc_non_mmio_node *a, a->last == b->last) return 0; - name = "PCC"; + name = a->space_id == ACPI_ADR_SPACE_PLATFORM_COMM ? + "PCC" : "SystemIO"; pr_err("CPU%d: %s _CPC register %u conflicts with CPU%d register %u\n", a->desc->cpu_id, name, a->reg_idx, b->desc->cpu_id, b->reg_idx); @@ -662,10 +666,11 @@ static int cpc_register_non_mmio_desc(struct cpc_desc *cpc_desc, continue; space_id = reg->cpc_entry.reg.space_id; - if (space_id != ACPI_ADR_SPACE_PLATFORM_COMM) + if (space_id != ACPI_ADR_SPACE_PLATFORM_COMM && + space_id != ACPI_ADR_SPACE_SYSTEM_IO) continue; - if (pcc_ss_id < 0) { + if (space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id < 0) { ret = -EINVAL; goto out_unregister; } @@ -677,7 +682,8 @@ static int cpc_register_non_mmio_desc(struct cpc_desc *cpc_desc, node->desc = cpc_desc; node->reg_idx = i; node->space_id = space_id; - node->pcc_ss_id = pcc_ss_id; + node->pcc_ss_id = space_id == ACPI_ADR_SPACE_PLATFORM_COMM ? + pcc_ss_id : 0; tree = cpc_non_mmio_tree(space_id, node->pcc_ss_id); match = cpc_non_mmio_itree_iter_first(tree, node->start, -- 2.34.1