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client-ip=165.204.84.17; helo=satlexmb08.amd.com; pr=C Received: from satlexmb08.amd.com (165.204.84.17) by SN1PEPF000397B5.mail.protection.outlook.com (10.167.248.59) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.406.5 via Frontend Transport; Wed, 9 Sep 2026 03:36:47 +0000 Received: from Satlexmb09.amd.com (10.181.42.218) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Tue, 8 Sep 2026 22:36:44 -0500 Received: from aus0006770c4n-lx01.amd.com (10.180.168.240) by satlexmb09.amd.com (10.181.42.218) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46; Tue, 8 Sep 2026 22:36:44 -0500 From: Mario Limonciello To: K Prateek Nayak CC: Perry Yuan , "open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "open list:CPU FREQUENCY SCALING FRAMEWORK" , "Mario Limonciello (AMD)" Subject: [PATCH v3 2/3] cpufreq/amd-pstate: Add EPP tunings for Zen6 client platforms Date: Tue, 8 Sep 2026 22:36:22 -0500 Message-ID: <20260909033623.454449-3-mario.limonciello@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260909033623.454449-1-mario.limonciello@amd.com> References: <20260909033623.454449-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb09.amd.com (10.181.42.218) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B5:EE_|IA1PR12MB8286:EE_ X-MS-Office365-Filtering-Correlation-Id: 6041ca3c-0673-4aaa-0066-08df0e2393c9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|23010399003|36860700016|22082099003|18002099003|11063799006|56012099006|10067099003|3023799007; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: kQEv0Iv/Iq1/4cGktk1ht32eO4fWwy83h2zGgic0evoBS8aWnY5FAseLy6cOJ+NjiX0uIdQuYUULAq67B3Q6EAEh4RRSq+8Ty7enMFMF8s/7Q0dr1fqKsHQCochVodXtgoM3H+thoZTRUObjC8zF59n01vxJNh7mnQ2k9ikfhU0TiLKDegBdiSbrbqn0KjmQbnMTDGVDtwN4L3lMbQig1HL8EqgK8hHnfQmeD3oe2E5QOqKgI7agoEys3Gcq9gyyqcfrtDDFO5wfSCrnXf1nHHvcqz9GOd/gl/csWZ+2Pxq3tq70eBY7eiU52ybC9qEwvr4qElY9UMZ+OjSMs9Y2NkrFIUxMopS1bnJjfUxfTZ+nfCWgfHs74xGz8byGtgAI1wN9K0/l48k8BX3nIaPrP6VGyAn0bzkmxH2+A+oE8CP2dr3cl5vW1dQgoi1H3nzW X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Sep 2026 03:36:47.5355 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6041ca3c-0673-4aaa-0066-08df0e2393c9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8286 From: "Mario Limonciello (AMD)" Zen6 client platforms perform better with individual tunings for different core types. Add initial EPP tuning values for those platforms. Signed-off-by: Mario Limonciello (AMD) --- drivers/cpufreq/amd-pstate.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 60a8b8f220437..380294bb56cd7 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -206,7 +206,33 @@ struct amd_pstate_epp_soc { * Per-CPU-type EPP overrides for hybrid systems. Only hybrid SoCs should be * listed here; non-hybrid systems always use the legacy defaults. */ +static const struct amd_pstate_epp_soc epp_soc_zen6_client __initconst = { + .performance_core = { + .performance = 25, + .balance_performance = 51, + .balance_power = 64, + .power = 64, + }, + .efficiency_core = { + .performance = 25, + .balance_performance = 51, + .balance_power = 64, + .power = 115, + }, + .low_power_core = { + .performance = 25, + .balance_performance = 51, + .balance_power = 64, + .power = 115, + }, +}; + static const struct x86_cpu_id amd_pstate_epp_soc_ids[] __initconst = { + X86_MATCH_VENDOR_FAM_MODEL(AMD, 0x1A, 0x80, &epp_soc_zen6_client), + X86_MATCH_VENDOR_FAM_MODEL(AMD, 0x1A, 0x81, &epp_soc_zen6_client), + X86_MATCH_VENDOR_FAM_MODEL(AMD, 0x1A, 0x84, &epp_soc_zen6_client), + X86_MATCH_VENDOR_FAM_MODEL(AMD, 0x1A, 0x85, &epp_soc_zen6_client), + X86_MATCH_VENDOR_FAM_MODEL(AMD, 0x1A, 0xe0, &epp_soc_zen6_client), {} }; -- 2.43.0