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Tue, 03 Nov 2026 23:46:21 -0800 (PST) Received: from Sobhana.localdomain ([157.51.204.42]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-36ca38a67edsm4566016eec.8.2026.11.03.23.46.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Nov 2026 23:46:20 -0800 (PST) From: Sreeshankar K Subject: [PATCH v12 0/6] Add initial support for Qualcomm SM7250 SoC Date: Wed, 04 Nov 2026 07:46:03 +0000 Message-Id: <20261104-master-v12-0-57fbe9eef978@gmail.com> X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIALzi6moC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDI10FJSSM xLz0lN1M1OAAkpGBkZmhoYGJrq5icUlqUW6pskpRimWyUkGickWSkDFBUWpaZkVYJOiY2trAWA Gv35ZAAAA To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Konrad Dybcio , Robert Marko , Guru Das Srinagesh , "Rafael J. Wysocki" , Viresh Kumar , Manivannan Sadhasivam , Daniel Lezcano , Zhang Rui , Lukasz Luba , Thara Gopinath Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Sreeshankar K , Krzysztof Kozlowski X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1793778372; l=6866; i=sreeshankar0910@gmail.com; s=20261029; h=from:subject:message-id; bh=R1dhX5JbUMHvKu/MupaHu+YfQPZ+VXmXHq+cGAjavtA=; b=wTe5JCMSJDIBrfir08X+CflO5XCH+38PYn1/dbIo7kqXlXBKhfzYT0p6fZA4vBcS1d+x8ZviW ap932+ga3SoCl4nQUY2POWiiy16YDK+rlegZDJZCvMnr5sSYRVQnA23 X-Developer-Key: i=sreeshankar0910@gmail.com; a=ed25519; pk=CGSHduvtn2hwLCNRXRc9s/fh6X8PH/zNdp08zC8hOuQ= This patchset introduces foundational upstream support for the Qualcomm SM7250 SoC (internally codenamed Lito). SM7250 is an ARMv8.2-A platform manufactured on a 7nm process, featuring an octa-core Kryo 475 CPU configuration (1x Prime Cortex-A76, 1x Gold Cortex-A76, and 6x Silver Cortex-A55) and Adreno 620 GPU. This patchset is organized as follows: > Document relevant device tree bindings (SoC ID, Kryo 475 CPUs, SCM, PDC, RPMh clocks/power domains, GCC and cpufreq hardware). > Add driver support for SM7250 in socinfo, rpmh-clk, rpmhpd, and GCC. > Add the base SoC DTSI (sm7250.dtsi) defining the cpus, PSCI, interrupt controllers, clock providers, power domains, and reserved memory. >-----------------------------------------------------------------------------< Merged patches: dt-bindings: arm: qcom,ids: Add SoC ID for SM7250 soc: qcom: socinfo: Add SM7250 SoC ID dt-bindings: clock: qcom,rpmhcc: Document RPMHCC compatible clk: qcom: rpmh: Add SM7250 rpmh clocks dt-bindings: power: qcom,rpmhpd: Document RPMh power domain for SM7250 pmdomain: qcom: rpmhpd: Add RPMh power domains dt-bindings: arm: cpus: Document Kryo 475 CPUs dt-bindings: interrupt-controller: qcom,pdc: Document SM7250 PDC Pending patches: dt-bindings: clock: Add SM7250 global clock controller clk: qcom: Add Global Clock Controller (GCC) driver for SM7250 dt-bindings: firmware: qcom,scm: Document SM7250 SCM dt-bindings: cpufreq: qcom-hw: Document SM7250 cpufreq hardware dt-bindings: thermal: lmh: Document SM7250 LMh arm64: dts: qcom: Add SM7250 devicetree file >------------------------------------------------------------------------------< Changelog [v12]: [PATCH v12 1/6] dt-bindings: clock: Add SM7250 global clock controller > Move dt-binding definition to qcom,gcc-sm8250.yaml. The device tree schema of SM7250 matches with SM8250 for clock-controller node. [PATCH v12 5/6] dt-bindings: thermal: lmh: Document SM7250 LMh > Add LMh compatible. [PATCH v12 6/6] arm64: dts: qcom: Add SM7250 devicetree file > Remove cluster wise sorting of cpus. > Add LMh node. Link [RESEND v11]: https://lore.kernel.org/linux-arm-msm/20261029-master-v11-0-2c29e382162c@gmail.com/T/#t Link [v11]: https://lore.kernel.org/linux-arm-msm/20261016042432.824-1-sreeshankar0910@gmail.com/T/#t Changelog [v11]: [PATCH v11 2/5] clk: qcom: Add Global Clock Controller (GCC) driver > Drop hw_ctl clock branches > Populate default values for GDSCs Link [v10]: https://lore.kernel.org/linux-arm-msm/20261015051926.13752-1-sreeshankar0910@gmail.com/T/#t Changelog [v10]: [PATCH v10 2/6] clk: qcom: Add Global Clock Controller (GCC) driver > Update .halt_check and .ops are per the review. Link [v9]: https://lore.kernel.org/linux-arm-msm/20260901092447.3028-1-sreeshankar0910@gmail.com/T/#t Changelog [v9]: [PATCH v9 04/13]: clk: qcom: Add Global Clock Controller (GCC) driver for SM7250 > Make all clk_init_data instances const across the driver. Link [v8]: https://lore.kernel.org/linux-arm-msm/20260901070717.20513-1-sreeshankar0910@gmail.com/T/#t Changelog [v8]: Same as v7. Resending the full patchset as v8 due to a transmission interruption during v7. Link [v7]: https://lore.kernel.org/linux-arm-msm/20260901064357.20055-1-sreeshankar0910@gmail.com/T/#t Changelog [v7]: [PATCH v7 04/13]: clk: qcom: Add Global Clock Controller (GCC) driver for SM7250 > Fixed missing (struct device *dev) in gcc_sm7250_clk_regs_configure Link [v6]: https://lore.kernel.org/linux-arm-msm/20260824150156.1310-1-sreeshankar0910@gmail.com/T/#t Changelog [v6]: [PATCH v6 04/13]: clk: qcom: Add Global Clock Controller (GCC) driver for SM7250 > Make all clk_init_data instances const across the driver. Link [v5]: https://lore.kernel.org/linux-arm-msm/20260824130437.2771-1-sreeshankar0910@gmail.com/T/#t Changelog [v5]: [PATCH v5 13/13]: arm64: dts: qcom: Add SM7250 devicetree file > Reformat multi-entry phandle lists (domain-idle-states) to '<&a>, <&b>'. > Reformat multi-entry tuples and string lists (qcom,pdc-ranges, qcom,tcs-config, reg-names) to one item per line. > Enable QUPv3 wrapper globally by dropping 'status = "disabled"'. > Move compatible property to first. > Remove clock-frequency property for timer. Link [v4]: https://lore.kernel.org/linux-arm-msm/20260821154030.2514-1-sreeshankar0910@gmail.com/T/#t Changelog [v4]: [PATCH v4 04/13] clk: qcom: Add Global Clock Controller (GCC) driver for SM7250 > Update .fw_name with .index [PATCH v4 13/13] arm64: dts: qcom: Add SM7250 devicetree file > Added missing capacity-dmips-mhz and dynamic-power-coefficient for cpu@300 > Added power-domains for cpus and apps_rsc Link [v3]: https://lore.kernel.org/linux-arm-msm/20260821081125.4522-1-sreeshankar0910@gmail.com/T/#t Changelog [v3]: [PATCH v3 04/13] clk: qcom: Add Global Clock Controller (GCC) driver for SM7250 > Updated the way of registering critical clocks. > Made some more clock critical. GCC_VIDEO_XO_CLK GCC_CAMERA_XO_CLK GCC_DISP_XO_CLK GCC_NPU_CFG_AHB_CLK GCC_CPUSS_AHB_CLK GCC_NPU_BWMON_CFG_AHB_CLK These clocks are flagged as critical in gcc-lito.c Link [v2]: https://lore.kernel.org/linux-arm-msm/20260819152545.3934-1-sreeshankar0910@gmail.com/T/#t Changelog [v2]: [PATCH v2 12/13] dt-bindings: cpufreq: qcom-hw: Document SM7250 cpufreq hardware [PATCH v2 13/13] arm64: dts: qcom: Add SM7250 devicetree file > Added SM7250 cpufreq hardware Link [v1]: https://lore.kernel.org/linux-arm-msm/20260818080754.4362-1-sreeshankar0910@gmail.com/T/#t Signed-off-by: Sreeshankar K --- Sreeshankar K (6): dt-bindings: clock: Add SM7250 global clock controller clk: qcom: Add Global Clock Controller (GCC) driver for SM7250 dt-bindings: firmware: qcom,scm: Document SM7250 SCM dt-bindings: cpufreq: qcom-hw: Document SM7250 cpufreq hardware dt-bindings: thermal: lmh: Document SM7250 LMh arm64: dts: qcom: Add SM7250 devicetree file .../devicetree/bindings/clock/qcom,gcc-sm8250.yaml | 13 +- .../bindings/cpufreq/cpufreq-qcom-hw.yaml | 2 + .../devicetree/bindings/firmware/qcom,scm.yaml | 1 + .../devicetree/bindings/thermal/qcom-lmh.yaml | 4 +- arch/arm64/boot/dts/qcom/sm7250.dtsi | 795 +++++++ drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-sm7250.c | 2278 ++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sm7250.h | 163 ++ 9 files changed, 3262 insertions(+), 5 deletions(-) --- base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4 change-id: 20261104-master-5cd2d9cb0ac8 Best regards, -- Sreeshankar K