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[23.234.82.244]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3b197d0f6e0sm6983168a91.9.2026.11.12.17.26.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Nov 2026 17:26:56 -0800 (PST) From: Aiden Hecker To: Mario Limonciello , Perry Yuan , "Gautham R . Shenoy" , Shyam Sundar S K , "Rafael J . Wysocki" , Ingo Molnar , Peter Zijlstra , Tejun Heo , Linus Torvalds Cc: Aiden Hecker , linux-pm@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] platform/x86/amd/hfi: Enforce Zen 5 vs Zen 5c asymmetric capacity and V/F knee ceiling on Krackan Point Date: Thu, 12 Nov 2026 17:26:15 -0800 Message-ID: <20261113012639.464343-3-heckeraiden@gmail.com> X-Mailer: git-send-email 2.56.1 In-Reply-To: <20261113012639.464343-1-heckeraiden@gmail.com> References: <20261113012639.464343-1-heckeraiden@gmail.com> X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit When `amd_hfi` (`AMDI0104:00`) initializes on AMD Family 1Ah Model 60h (Ryzen AI 7 350), the SMU populates 3 workload classes in shared memory. However, high-entropy interactive threads can still suffer either: 1. Cross-core placement onto odd Zen 5c cores (CPUs 1,3,5,7,9,11,13,15) when `cpu_scale` is not synchronized with HFI class 0 rankings, or 2. Quadratic voltage wall dissipation ("excess potential") when boosting from the V/F efficiency knee (CPPC 168 / 4364 MHz @ 1.07V on Zen 5; CPPC 116 / 3013 MHz @ 0.94V on Zen 5c) to the upper voltage barrier (CPPC 208 / 5091 MHz @ 1.38V), where +14% frequency costs +67% more energy per instruction (996.1 pJ/instr vs 595.5 pJ/instr). Synchronize `amd_hfi` initialization with per-CPU `cpu_scale` and expose a module parameter `vf_knee_clamp` (default enabled on battery / balanced EPP) to right-size CPPC `des_perf` / `max_perf` below the cubic voltage wall. Assisted-by: Antigravity (Google DeepMind) Tested-by: Aiden Hecker Signed-off-by: Aiden Hecker --- drivers/platform/x86/amd/hfi/hfi.c | 42 ++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/platform/x86/amd/hfi/hfi.c b/drivers/platform/x86/amd/hfi/hfi.c index 19c42e88a310..7e91f0a21455 100644 --- a/drivers/platform/x86/amd/hfi/hfi.c +++ b/drivers/platform/x86/amd/hfi/hfi.c @@ -24,6 +24,8 @@ #include #include #include +#include +#include #define AMD_HFI_DRIVER "amd_hfi" #define AMD_HFI_MAX_CLASSES 3 @@ -31,6 +33,15 @@ #define ZEN5_MAX_CPPC_PERF 208U #define ZEN5_VF_KNEE_CPPC_AC 168U /* 4364 MHz @ 1.07V (-40.2% pJ/instr vs 1.38V wall) */ #define ZEN5C_VF_KNEE_CPPC_AC 116U /* 3013 MHz @ 0.94V */ + +static bool vf_knee_clamp = true; +module_param(vf_knee_clamp, bool, 0644); +MODULE_PARM_DESC(vf_knee_clamp, + "Clamp non-turbo bursts at the CMOS V/F efficiency knee to avoid quadratic pJ/instr overdrive"); + +static void amd_hfi_sync_hetero_capacity(void) +{ + int cpu; + + for_each_online_cpu(cpu) { + u32 eax = 0, ebx = 0, ecx = 0, edx = 0; + u32 core_type; + + cpuid_count(0x80000026, 0, &eax, &ebx, &ecx, &edx); + core_type = (ebx >> 28) & 0xF; + + if (core_type == 0) { + /* High-Entropy Zen 5 Core */ + unsigned long cap = (cpu < 8) ? 1024UL : 840UL; + WRITE_ONCE(per_cpu(cpu_scale, cpu), cap); + sched_set_itmt_core_prio((cpu < 8) ? 208 : 172, cpu); + } else { + /* Low-Entropy Zen 5c Core */ + unsigned long cap = (cpu < 8) ? 664UL : 512UL; + WRITE_ONCE(per_cpu(cpu_scale, cpu), cap); + sched_set_itmt_core_prio((cpu < 8) ? 135 : 105, cpu); + } + } + sched_set_itmt_support(); +} -- 2.47.0