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[82.149.12.148]) by smtp.gmail.com with ESMTPSA id m29-20020a05600c3b1d00b0040b3515cdf8sm25400470wms.7.2023.12.14.08.36.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Dec 2023 08:37:00 -0800 (PST) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: Viresh Kumar , Conor Dooley Cc: Brandon Cheo Fusi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Yangtao Li , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: Re: [PATCH 1/5] riscv: dts: allwinner: Update opp table to allow CPU frequency scaling Date: Thu, 14 Dec 2023 17:36:59 +0100 Message-ID: <2177637.Mh6RI2rZIc@archlinux> In-Reply-To: <20231214-junkyard-corset-d35b01bad69f@spud> References: <20231214103342.30775-1-fusibrandon13@gmail.com> <20231214111446.camz2krqanaieybh@vireshk-i7> <20231214-junkyard-corset-d35b01bad69f@spud> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" On Thursday, December 14, 2023 2:47:14 PM CET Conor Dooley wrote: > On Thu, Dec 14, 2023 at 04:44:46PM +0530, Viresh Kumar wrote: > > On 14-12-23, 11:33, Brandon Cheo Fusi wrote: > > > Two OPPs are currently defined for the D1/D1s; one at 408MHz and > > > another at 1.08GHz. Switching between these can be done with the > > > "sun50i-cpufreq-nvmem" driver. This patch populates the opp table > > > appropriately, with inspiration from > > > https://github.com/Tina-Linux/linux-5.4/blob/master/arch/riscv/boot/dts/sunxi/sun20iw1p1.dtsi > > > > > > The supply voltages are PWM-controlled, but support for that IP > > > is still in the works. So stick to a fixed 0.9V vdd-cpu supply, > > > which seems to be the default on most D1 boards. > > > > > > Signed-off-by: Brandon Cheo Fusi > > > --- > > > arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 18 +++++++++++++++--- > > > 1 file changed, 15 insertions(+), 3 deletions(-) > > > > > > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > > > index 64c3c2e6c..e211fe4c7 100644 > > > --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > > > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > > > @@ -39,16 +39,22 @@ cpu0_intc: interrupt-controller { > > > }; > > > > > > opp_table_cpu: opp-table-cpu { > > > - compatible = "operating-points-v2"; > > > + compatible = "allwinner,sun20i-d1-operating-points", > > > > I don't think you should add a new compatible for every SoC that needs > > to be supported by a DT bindings and cpufreq driver. Maybe you should > > just reuse "allwinner,sun50i-h6-operating-points" and it will work > > fine for you ? > > > > Rob ? > > The driver can definitely just reuse sun50i-h6, but the binding and > devicetree should have a soc-specific compatible for the sun20i-d1. Correct. This is to avoid later regrets if it turns out there are some slight differences or additional functionality. Best regards, Jernej > > That said, the compatible does need to be documented, there's a > dt-bindings patch missing from this series. > > Cheers, > Conor.