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Mon, 06 Jul 2026 04:57:27 -0700 (PDT) X-Received: by 2002:ac8:5710:0:b0:51c:db4:3cb8 with SMTP id d75a77b69052e-51c4bed6cd2mr89588051cf.8.1783339046794; Mon, 06 Jul 2026 04:57:26 -0700 (PDT) Received: from [192.168.120.193] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c12b62c2d37sm729266666b.42.2026.07.06.04.57.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 06 Jul 2026 04:57:25 -0700 (PDT) Message-ID: <21f13da7-94ee-4eb2-b2bd-6200d70f38f9@oss.qualcomm.com> Date: Mon, 6 Jul 2026 13:57:23 +0200 Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/4] powercap: qcom: Add SPEL powercap driver To: Manaf Meethalavalappu Pallikunhi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Bjorn Andersson , Konrad Dybcio , Daniel Lezcano Cc: Gaurav Kohli , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org References: <20260702-qcom_spel_driver_upstream-v3-0-434d50f0c5b0@oss.qualcomm.com> <20260702-qcom_spel_driver_upstream-v3-3-434d50f0c5b0@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260702-qcom_spel_driver_upstream-v3-3-434d50f0c5b0@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: nIYiJL51RQID4gLOCmXIZruZ90B85GVf X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzA2MDEyMSBTYWx0ZWRfX0EMsOoIloz7u cornKdstIGtLFF0zkqVBPd0rDiv7kzAvcDMdgoHIwjR4r7PGMN7Mjy62+jAfLjCtTQs5mZ+SjeX 7yCP+QbSv4o7XCO5B7Zm3sOFmg0KFKpxdJPTnU7+JAxgvvBpgjOcdXkYKZ7Q7E8Z2Meo+j2GnoJ VUJ8veS5Lh/ftyRk2gLQF32ICBZSIE/EV4IBdBmHN/Pf+usDDOplSOYGQ4DwK9OPnokhF+6/Cgo nbK/ClnZk+0xZlDM7tW4GcOXWo21s40W/9n9UZYQQwQbDmz9x8bHl8ZwHQux/QyLxsg+jTMgFK/ WVI6f8kZPaCowMzCN9JKUJWZa5YbZBDYOyZ0z0H2r9hSeJyVV0DWsOo/Hyr/6u5/9ENWe28Czx4 5GWyLWO9B/2cZ5qdJE9bQ1gobb0dZeEok4LsjTR1jNsCOSXlvyG8ke/m2SQ5/FNu0+s+YC/USJT b3XTBQ5MhrZ4oJdE9+Q== X-Proofpoint-ORIG-GUID: nIYiJL51RQID4gLOCmXIZruZ90B85GVf X-Proofpoint-Spam-Info: AW1haW4tMjYwNzA2MDEyMSBTYWx0ZWRfX6FarlF8IRDii ck+5yXEECnwMdD0dZYVSalky5Ov7rTzYpP3Yi5ql4xA3sWFuFtiuSzFVzm3qKz5H8N/sTtPudia u/RyyKurJSS67nfBh6tYiw5MLGQSYvY= X-Authority-Analysis: v=2.4 cv=c6Sbhx9l c=1 sm=1 tr=0 ts=6a4b9828 cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=yjWOilcczNxlq6oZqccA:9 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-06_01,2026-07-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 clxscore=1015 adultscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607060121 On 7/2/26 7:22 PM, Manaf Meethalavalappu Pallikunhi wrote: > The Qualcomm SoC Power and Electrical Limits (SPEL) provides hardware > based power monitoring and limiting capabilities for various power > domains including System, SoC, CPU clusters, GPU, and various other > subsystems. > > The driver integrates with the Linux powercap framework, exposing SPEL > capabilities through powercap sysfs interfaces. > > Signed-off-by: Manaf Meethalavalappu Pallikunhi > --- [...] > +#define TIME_WINDOW_MASK_L GENMASK(14, 0) > +#define TIME_WINDOW_MASK_H GENMASK(22, 16) > +#define TIME_WINDOW_MAX ((FIELD_MAX(TIME_WINDOW_MASK_H) << 15) | \ > + FIELD_MAX(TIME_WINDOW_MASK_L)) I am having difficulty correlating this mask to the register description I have available. Are you sure what you call TIME_WINDOW_MASK_L actually exists? [...] > +/* Constraint configuration */ > +static const struct spel_constraint_info constraints[] = { > + /* SYS domain constraints */ > + { 0x10, 0x70, BIT(0), SPEL_DOMAIN_SYS, POWER_LIMIT1 }, > + { 0x14, 0x74, BIT(1), SPEL_DOMAIN_SYS, POWER_LIMIT2 }, > + { 0x18, 0x78, BIT(2), SPEL_DOMAIN_SYS, POWER_LIMIT3 }, > + { 0x1c, 0x7c, BIT(3), SPEL_DOMAIN_SYS, POWER_LIMIT4 }, > + /* SoC domain constraints */ > + { 0x00, 0x60, BIT(4), SPEL_DOMAIN_SOC, POWER_LIMIT1 }, > + { 0x04, 0x64, BIT(5), SPEL_DOMAIN_SOC, POWER_LIMIT2 }, > + { 0x08, 0x68, BIT(6), SPEL_DOMAIN_SOC, POWER_LIMIT3 }, > + { 0x0c, 0x6c, BIT(7), SPEL_DOMAIN_SOC, POWER_LIMIT4 }, Similarly, these offsets are difficult for me to correlate with the register names in the constraints/0x0ef3_d000 space [...] > + /* > + * Enable/Disable PL based on the value: > + * - If value is 0, disable the PL (clear enable bit) > + * - If value is non-zero, enable the PL (set enable bit) > + */ > + FIELD_MODIFY(POWER_LIMIT_ENABLE, ®_val, new_val ? 1 : 0); !!new_val Konrad