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[89.182.137.217]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-46dd5f9da4fsm15043736f8f.23.2026.06.26.03.36.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 26 Jun 2026 03:36:50 -0700 (PDT) Message-ID: <2a69d701-741b-4d65-bdbe-226610bf53b5@gmail.com> Date: Fri, 26 Jun 2026 12:36:48 +0200 Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 2/2] riscv: dts: spacemit: Add cpu scaling for K1 SoC To: Shuwei Wu , "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yixun Lan Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, devicetree@vger.kernel.org References: <20260626-shadow-deps-v4-0-bba9831f2f1d@mailbox.org> <20260626-shadow-deps-v4-2-bba9831f2f1d@mailbox.org> From: Andre Heider Content-Language: de-DE In-Reply-To: <20260626-shadow-deps-v4-2-bba9831f2f1d@mailbox.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 26.06.26 10:10 AM, Shuwei Wu wrote: > Add CPU clock properties and OPP tables for the two CPU clusters in the > SpacemiT K1 SoC. The OPP entries use voltage ranges because the CPU > supply is shared by both clusters. > > Enable CPU DVFS on Banana Pi BPI-F3 by including the OPP tables and > wiring the CPU nodes to the CPU regulator supply. > > Signed-off-by: Shuwei Wu With the musepi-pro dts enablement patch [0] on top, this is Tested-by: Andre Heider # k1-musepi-pro Works as advertised, I get two policies, matching the clusters: $ cat /sys/devices/system/cpu/cpufreq/policy0/related_cpus 0 1 2 3 $ cat /sys/devices/system/cpu/cpufreq/policy4/related_cpus 4 5 6 7 Some time after boot: $ cat /sys/devices/system/cpu/cpufreq/policy0/stats/time_in_state 614400 31124 819000 185 1000000 158 1228800 341 1600000 1148 $ cat /sys/devices/system/cpu/cpufreq/policy4/stats/time_in_state 614400 29232 819000 198 1000000 212 1228800 443 1600000 3428 Creating one single-threaded load increases max freq time_in_state in one policy (4 here): $ yes > /dev/null & (...after some time) $ cat /sys/devices/system/cpu/cpufreq/policy0/stats/time_in_state 614400 45244 819000 187 1000000 169 1228800 345 1600000 1148 $ cat /sys/devices/system/cpu/cpufreq/policy4/stats/time_in_state 614400 38794 819000 201 1000000 226 1228800 450 1600000 7580 Creating load for all 8 cores in both: $ yes > /dev/null & $ yes > /dev/null & $ yes > /dev/null & $ yes > /dev/null & $ yes > /dev/null & $ yes > /dev/null & $ yes > /dev/null & $ yes > /dev/null & $ cat /sys/devices/system/cpu/cpufreq/policy0/stats/time_in_state 614400 51371 819000 190 1000000 171 1228800 352 1600000 4391 $ cat /sys/devices/system/cpu/cpufreq/policy4/stats/time_in_state 614400 44121 819000 203 1000000 244 1228800 452 1600000 11812 Thanks! Andre [0] https://lore.kernel.org/all/20260614122812.2287506-1-a.heider@gmail.com/ > --- > Changes in v4: > - Use separate OPP tables for the two CPU clock clusters > - Use voltage ranges for the shared CPU supply > > Changes in v3: > - Use one shared CPU OPP table for all CPUs > > Changes in v2: > - Add k1-opp.dtsi with OPP tables for both CPU clusters > - Assign CPU supplies and include OPP table for Banana Pi BPI-F3 > --- > --- > arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 35 +++++++- > arch/riscv/boot/dts/spacemit/k1-opp.dtsi | 105 ++++++++++++++++++++++++ > arch/riscv/boot/dts/spacemit/k1.dtsi | 8 ++ > 3 files changed, 147 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts > index 444c3b1e6f44..487179f7b9b9 100644 > --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts > +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts > @@ -4,6 +4,7 @@ > */ > > #include "k1.dtsi" > +#include "k1-opp.dtsi" > #include "k1-pinctrl.dtsi" > > / { > @@ -86,6 +87,38 @@ &combo_phy { > status = "okay"; > }; > > +&cpu_0 { > + cpu-supply = <&buck1_0v9>; > +}; > + > +&cpu_1 { > + cpu-supply = <&buck1_0v9>; > +}; > + > +&cpu_2 { > + cpu-supply = <&buck1_0v9>; > +}; > + > +&cpu_3 { > + cpu-supply = <&buck1_0v9>; > +}; > + > +&cpu_4 { > + cpu-supply = <&buck1_0v9>; > +}; > + > +&cpu_5 { > + cpu-supply = <&buck1_0v9>; > +}; > + > +&cpu_6 { > + cpu-supply = <&buck1_0v9>; > +}; > + > +&cpu_7 { > + cpu-supply = <&buck1_0v9>; > +}; > + > &emmc { > bus-width = <8>; > mmc-hs400-1_8v; > @@ -201,7 +234,7 @@ pmic@41 { > dldoin2-supply = <&buck5>; > > regulators { > - buck1 { > + buck1_0v9: buck1 { > regulator-min-microvolt = <500000>; > regulator-max-microvolt = <3450000>; > regulator-ramp-delay = <5000>; > diff --git a/arch/riscv/boot/dts/spacemit/k1-opp.dtsi b/arch/riscv/boot/dts/spacemit/k1-opp.dtsi > new file mode 100644 > index 000000000000..4cebfcd87485 > --- /dev/null > +++ b/arch/riscv/boot/dts/spacemit/k1-opp.dtsi > @@ -0,0 +1,105 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > + > +/ { > + cluster0_opp_table: opp-table-cluster0 { > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp-614400000 { > + opp-hz = /bits/ 64 <614400000>; > + opp-microvolt = <950000 950000 1050000>; > + clock-latency-ns = <200000>; > + }; > + > + opp-819000000 { > + opp-hz = /bits/ 64 <819000000>; > + opp-microvolt = <950000 950000 1050000>; > + clock-latency-ns = <200000>; > + }; > + > + opp-1000000000 { > + opp-hz = /bits/ 64 <1000000000>; > + opp-microvolt = <950000 950000 1050000>; > + clock-latency-ns = <200000>; > + }; > + > + opp-1228800000 { > + opp-hz = /bits/ 64 <1228800000>; > + opp-microvolt = <950000 950000 1050000>; > + clock-latency-ns = <200000>; > + }; > + > + opp-1600000000 { > + opp-hz = /bits/ 64 <1600000000>; > + opp-microvolt = <1050000 1050000 1050000>; > + clock-latency-ns = <200000>; > + }; > + }; > + > + cluster1_opp_table: opp-table-cluster1 { > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp-614400000 { > + opp-hz = /bits/ 64 <614400000>; > + opp-microvolt = <950000 950000 1050000>; > + clock-latency-ns = <200000>; > + }; > + > + opp-819000000 { > + opp-hz = /bits/ 64 <819000000>; > + opp-microvolt = <950000 950000 1050000>; > + clock-latency-ns = <200000>; > + }; > + > + opp-1000000000 { > + opp-hz = /bits/ 64 <1000000000>; > + opp-microvolt = <950000 950000 1050000>; > + clock-latency-ns = <200000>; > + }; > + > + opp-1228800000 { > + opp-hz = /bits/ 64 <1228800000>; > + opp-microvolt = <950000 950000 1050000>; > + clock-latency-ns = <200000>; > + }; > + > + opp-1600000000 { > + opp-hz = /bits/ 64 <1600000000>; > + opp-microvolt = <1050000 1050000 1050000>; > + clock-latency-ns = <200000>; > + }; > + }; > +}; > + > +&cpu_0 { > + operating-points-v2 = <&cluster0_opp_table>; > +}; > + > +&cpu_1 { > + operating-points-v2 = <&cluster0_opp_table>; > +}; > + > +&cpu_2 { > + operating-points-v2 = <&cluster0_opp_table>; > +}; > + > +&cpu_3 { > + operating-points-v2 = <&cluster0_opp_table>; > +}; > + > +&cpu_4 { > + operating-points-v2 = <&cluster1_opp_table>; > +}; > + > +&cpu_5 { > + operating-points-v2 = <&cluster1_opp_table>; > +}; > + > +&cpu_6 { > + operating-points-v2 = <&cluster1_opp_table>; > +}; > + > +&cpu_7 { > + operating-points-v2 = <&cluster1_opp_table>; > +}; > diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi > index 529ec68e9c23..bdd109b81730 100644 > --- a/arch/riscv/boot/dts/spacemit/k1.dtsi > +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi > @@ -54,6 +54,7 @@ cpu_0: cpu@0 { > compatible = "spacemit,x60", "riscv"; > device_type = "cpu"; > reg = <0>; > + clocks = <&syscon_apmu CLK_CPU_C0_CORE>; > riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", > @@ -84,6 +85,7 @@ cpu_1: cpu@1 { > compatible = "spacemit,x60", "riscv"; > device_type = "cpu"; > reg = <1>; > + clocks = <&syscon_apmu CLK_CPU_C0_CORE>; > riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", > @@ -114,6 +116,7 @@ cpu_2: cpu@2 { > compatible = "spacemit,x60", "riscv"; > device_type = "cpu"; > reg = <2>; > + clocks = <&syscon_apmu CLK_CPU_C0_CORE>; > riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", > @@ -144,6 +147,7 @@ cpu_3: cpu@3 { > compatible = "spacemit,x60", "riscv"; > device_type = "cpu"; > reg = <3>; > + clocks = <&syscon_apmu CLK_CPU_C0_CORE>; > riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", > @@ -174,6 +178,7 @@ cpu_4: cpu@4 { > compatible = "spacemit,x60", "riscv"; > device_type = "cpu"; > reg = <4>; > + clocks = <&syscon_apmu CLK_CPU_C1_CORE>; > riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", > @@ -204,6 +209,7 @@ cpu_5: cpu@5 { > compatible = "spacemit,x60", "riscv"; > device_type = "cpu"; > reg = <5>; > + clocks = <&syscon_apmu CLK_CPU_C1_CORE>; > riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", > @@ -234,6 +240,7 @@ cpu_6: cpu@6 { > compatible = "spacemit,x60", "riscv"; > device_type = "cpu"; > reg = <6>; > + clocks = <&syscon_apmu CLK_CPU_C1_CORE>; > riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", > @@ -264,6 +271,7 @@ cpu_7: cpu@7 { > compatible = "spacemit,x60", "riscv"; > device_type = "cpu"; > reg = <7>; > + clocks = <&syscon_apmu CLK_CPU_C1_CORE>; > riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", >