* [PATCH v3 1/8] ACPI: CPPC: Add AMD pstate energy performance preference cppc control
2022-11-07 17:56 [PATCH v3 0/8] Implement AMD Pstate EPP Driver Perry Yuan
@ 2022-11-07 17:56 ` Perry Yuan
2022-11-07 18:44 ` Limonciello, Mario
2022-11-07 17:56 ` [PATCH v3 2/8] Documentation: amd-pstate: add EPP profiles introduction Perry Yuan
` (6 subsequent siblings)
7 siblings, 1 reply; 35+ messages in thread
From: Perry Yuan @ 2022-11-07 17:56 UTC (permalink / raw)
To: rafael.j.wysocki, ray.huang, viresh.kumar
Cc: Deepak.Sharma, Mario.Limonciello, Nathan.Fontenot,
Alexander.Deucher, Shimmer.Huang, Xiaojian.Du, Li.Meng, linux-pm,
linux-kernel, Perry Yuan
Add the EPP(Energy Performance Preference) support for the
AMD SoCs without the dedicated CPPC MSR, those SoCs need to add this
cppc acpi functions to update EPP values and desired perf value.
In order to get EPP worked, cppc_get_epp_caps() will query EPP preference
value and cppc_set_epp_perf() will set EPP new value.
Before the EPP works, pstate driver will use cppc_set_auto_epp() to
enable EPP function from firmware firstly.
Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
---
drivers/acpi/cppc_acpi.c | 126 +++++++++++++++++++++++++++++++++++++++
include/acpi/cppc_acpi.h | 17 ++++++
2 files changed, 143 insertions(+)
diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
index 093675b1a1ff..d9c38dee1f48 100644
--- a/drivers/acpi/cppc_acpi.c
+++ b/drivers/acpi/cppc_acpi.c
@@ -1365,6 +1365,132 @@ int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
}
EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
+/**
+ * cppc_get_epp_caps - Get the energy preference register value.
+ * @cpunum: CPU from which to get epp preference level.
+ * @perf_caps: Return address.
+ *
+ * Return: 0 for success, -EIO otherwise.
+ */
+int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps)
+{
+ struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
+ struct cpc_register_resource *energy_perf_reg;
+ u64 energy_perf;
+
+ if (!cpc_desc) {
+ pr_warn("No CPC descriptor for CPU:%d\n", cpunum);
+ return -ENODEV;
+ }
+
+ energy_perf_reg = &cpc_desc->cpc_regs[ENERGY_PERF];
+
+ if (!CPC_SUPPORTED(energy_perf_reg))
+ pr_warn("energy perf reg update is unsupported!\n");
+
+ if (CPC_IN_PCC(energy_perf_reg)) {
+ int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
+ struct cppc_pcc_data *pcc_ss_data = NULL;
+ int ret = 0;
+
+ if (pcc_ss_id < 0)
+ return -ENODEV;
+
+ pcc_ss_data = pcc_data[pcc_ss_id];
+
+ down_write(&pcc_ss_data->pcc_lock);
+
+ if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) {
+ cpc_read(cpunum, energy_perf_reg, &energy_perf);
+ perf_caps->energy_perf = energy_perf;
+ } else {
+ ret = -EIO;
+ }
+
+ up_write(&pcc_ss_data->pcc_lock);
+
+ return ret;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(cppc_get_epp_caps);
+
+int cppc_set_auto_epp(int cpu, bool enable)
+{
+ int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
+ struct cpc_register_resource *auto_sel_reg;
+ struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
+ struct cppc_pcc_data *pcc_ss_data = NULL;
+ int ret = -EINVAL;
+
+ if (!cpc_desc) {
+ pr_warn("No CPC descriptor for CPU:%d\n", cpu);
+ return -EINVAL;
+ }
+
+ auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
+
+ if (CPC_IN_PCC(auto_sel_reg)) {
+ if (pcc_ss_id < 0)
+ return -ENODEV;
+
+ ret = cpc_write(cpu, auto_sel_reg, enable);
+ if (ret)
+ return ret;
+
+ pcc_ss_data = pcc_data[pcc_ss_id];
+
+ down_write(&pcc_ss_data->pcc_lock);
+ /* after writing CPC, transfer the ownership of PCC to platform */
+ ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
+ up_write(&pcc_ss_data->pcc_lock);
+ return ret;
+ }
+
+ return cpc_write(cpu, auto_sel_reg, enable);
+}
+EXPORT_SYMBOL_GPL(cppc_set_auto_epp);
+
+/*
+ * Set Energy Performance Preference Register value through
+ * Performance Controls Interface
+ */
+int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
+{
+ int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
+ struct cpc_register_resource *epp_set_reg;
+ struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
+ struct cppc_pcc_data *pcc_ss_data = NULL;
+ int ret = -EINVAL;
+
+ if (!cpc_desc) {
+ pr_warn("No CPC descriptor for CPU:%d\n", cpu);
+ return -EINVAL;
+ }
+
+ epp_set_reg = &cpc_desc->cpc_regs[ENERGY_PERF];
+
+ if (CPC_IN_PCC(epp_set_reg)) {
+ if (pcc_ss_id < 0)
+ return -ENODEV;
+
+ ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf);
+ if (ret)
+ return ret;
+
+ pcc_ss_data = pcc_data[pcc_ss_id];
+
+ down_write(&pcc_ss_data->pcc_lock);
+ /* after writing CPC, transfer the ownership of PCC to platform */
+ ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
+ up_write(&pcc_ss_data->pcc_lock);
+ }
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(cppc_set_epp_perf);
+
/**
* cppc_set_enable - Set to enable CPPC on the processor by writing the
* Continuous Performance Control package EnableRegister field.
diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h
index c5614444031f..10d91aeedaca 100644
--- a/include/acpi/cppc_acpi.h
+++ b/include/acpi/cppc_acpi.h
@@ -108,12 +108,14 @@ struct cppc_perf_caps {
u32 lowest_nonlinear_perf;
u32 lowest_freq;
u32 nominal_freq;
+ u32 energy_perf;
};
struct cppc_perf_ctrls {
u32 max_perf;
u32 min_perf;
u32 desired_perf;
+ u32 energy_perf;
};
struct cppc_perf_fb_ctrs {
@@ -149,6 +151,9 @@ extern bool cpc_ffh_supported(void);
extern bool cpc_supported_by_cpu(void);
extern int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val);
extern int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val);
+extern int cppc_set_auto_epp(int cpu, bool enable);
+extern int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps);
+extern int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls);
#else /* !CONFIG_ACPI_CPPC_LIB */
static inline int cppc_get_desired_perf(int cpunum, u64 *desired_perf)
{
@@ -202,6 +207,18 @@ static inline int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)
{
return -ENOTSUPP;
}
+static inline int cppc_set_auto_epp(int cpu, bool enable)
+{
+ return -ENOTSUPP;
+}
+static inline int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
+{
+ return -ENOTSUPP;
+}
+static inline int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps)
+{
+ return -ENOTSUPP;
+}
#endif /* !CONFIG_ACPI_CPPC_LIB */
#endif /* _CPPC_ACPI_H*/
--
2.34.1
^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [PATCH v3 1/8] ACPI: CPPC: Add AMD pstate energy performance preference cppc control
2022-11-07 17:56 ` [PATCH v3 1/8] ACPI: CPPC: Add AMD pstate energy performance preference cppc control Perry Yuan
@ 2022-11-07 18:44 ` Limonciello, Mario
2022-11-10 14:49 ` Rafael J. Wysocki
2022-11-13 16:28 ` Yuan, Perry
0 siblings, 2 replies; 35+ messages in thread
From: Limonciello, Mario @ 2022-11-07 18:44 UTC (permalink / raw)
To: Perry Yuan, rafael.j.wysocki, ray.huang, viresh.kumar
Cc: Deepak.Sharma, Nathan.Fontenot, Alexander.Deucher, Shimmer.Huang,
Xiaojian.Du, Li.Meng, linux-pm, linux-kernel
On 11/7/2022 11:56, Perry Yuan wrote:
> Add the EPP(Energy Performance Preference) support for the
> AMD SoCs without the dedicated CPPC MSR, those SoCs need to add this
> cppc acpi functions to update EPP values and desired perf value.
As far as I can tell this is generic code. Although the reason you're
submitting it is for enabling AMD SoCs, the commit message should be
worded as such.
>
> In order to get EPP worked, cppc_get_epp_caps() will query EPP preference
> value and cppc_set_epp_perf() will set EPP new value.
> Before the EPP works, pstate driver will use cppc_set_auto_epp() to
> enable EPP function from firmware firstly.
This could more succinctly say:
"Add support for setting and querying EPP preferences to the generic
CPPC driver. This enables downstream drivers such as amd-pstate to discover
and use these values."
>
> Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
> ---
> drivers/acpi/cppc_acpi.c | 126 +++++++++++++++++++++++++++++++++++++++
> include/acpi/cppc_acpi.h | 17 ++++++
> 2 files changed, 143 insertions(+)
>
> diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
> index 093675b1a1ff..d9c38dee1f48 100644
> --- a/drivers/acpi/cppc_acpi.c
> +++ b/drivers/acpi/cppc_acpi.c
> @@ -1365,6 +1365,132 @@ int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
> }
> EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
>
> +/**
> + * cppc_get_epp_caps - Get the energy preference register value.
> + * @cpunum: CPU from which to get epp preference level.
> + * @perf_caps: Return address.
> + *
> + * Return: 0 for success, -EIO otherwise.
> + */
> +int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps)
> +{
> + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
> + struct cpc_register_resource *energy_perf_reg;
> + u64 energy_perf;
> +
> + if (!cpc_desc) {
> + pr_warn("No CPC descriptor for CPU:%d\n", cpunum);
> + return -ENODEV;
> + }
> +
> + energy_perf_reg = &cpc_desc->cpc_regs[ENERGY_PERF];
> +
> + if (!CPC_SUPPORTED(energy_perf_reg))
> + pr_warn("energy perf reg update is unsupported!\n");
No need to add a explanation point at the end.
As this is a per-CPU message I wonder if this would be better as
pr_warn_once()? Othewrise some systems with large numbers of cores
might potentially show this message quite a few times.
> +
> + if (CPC_IN_PCC(energy_perf_reg)) {
> + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
> + struct cppc_pcc_data *pcc_ss_data = NULL;
> + int ret = 0;
> +
> + if (pcc_ss_id < 0)
> + return -ENODEV;
> +
> + pcc_ss_data = pcc_data[pcc_ss_id];
> +
> + down_write(&pcc_ss_data->pcc_lock);
> +
> + if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) {
> + cpc_read(cpunum, energy_perf_reg, &energy_perf);
> + perf_caps->energy_perf = energy_perf;
> + } else {
> + ret = -EIO;
> + }
> +
> + up_write(&pcc_ss_data->pcc_lock);
> +
> + return ret;
> + }
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(cppc_get_epp_caps);
> +
> +int cppc_set_auto_epp(int cpu, bool enable)
> +{
> + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
> + struct cpc_register_resource *auto_sel_reg;
> + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
> + struct cppc_pcc_data *pcc_ss_data = NULL;
> + int ret = -EINVAL;
> +
> + if (!cpc_desc) {
> + pr_warn("No CPC descriptor for CPU:%d\n", cpu);
Is this actually warn worthy? I would think it's fine a debug like we
have for the other _CPC missing messages.
> + return -EINVAL;
> + }
> +
> + auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
> +
> + if (CPC_IN_PCC(auto_sel_reg)) {
> + if (pcc_ss_id < 0)
> + return -ENODEV;
> +
> + ret = cpc_write(cpu, auto_sel_reg, enable);
> + if (ret)
> + return ret;
> +
> + pcc_ss_data = pcc_data[pcc_ss_id];
> +
> + down_write(&pcc_ss_data->pcc_lock);
> + /* after writing CPC, transfer the ownership of PCC to platform */
> + ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
> + up_write(&pcc_ss_data->pcc_lock);
> + return ret;
> + }
> +
> + return cpc_write(cpu, auto_sel_reg, enable);
> +}
> +EXPORT_SYMBOL_GPL(cppc_set_auto_epp);
> +
> +/*
> + * Set Energy Performance Preference Register value through
> + * Performance Controls Interface
> + */
> +int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
> +{
> + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
> + struct cpc_register_resource *epp_set_reg;
> + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
> + struct cppc_pcc_data *pcc_ss_data = NULL;
> + int ret = -EINVAL;
> +
> + if (!cpc_desc) {
> + pr_warn("No CPC descriptor for CPU:%d\n", cpu);
Is this actually warn worthy? I would think it's fine a debug like we
have for the other _CPC missing messages.
> + return -EINVAL;
> + }
> +
> + epp_set_reg = &cpc_desc->cpc_regs[ENERGY_PERF];
> +
> + if (CPC_IN_PCC(epp_set_reg)) {
> + if (pcc_ss_id < 0)
> + return -ENODEV;
> +
> + ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf);
> + if (ret)
> + return ret;
> +
> + pcc_ss_data = pcc_data[pcc_ss_id];
> +
> + down_write(&pcc_ss_data->pcc_lock);
> + /* after writing CPC, transfer the ownership of PCC to platform */
> + ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
> + up_write(&pcc_ss_data->pcc_lock);
cppc_set_auto_epp and cppc_set_epp_perf have nearly the same code in the
if block. I wonder if it's worth having a static helper function for
this purpose that takes "reg" and "value" as arguments?
> + }
> +
> + return ret;
> +}
> +EXPORT_SYMBOL_GPL(cppc_set_epp_perf);
> +
> /**
> * cppc_set_enable - Set to enable CPPC on the processor by writing the
> * Continuous Performance Control package EnableRegister field.
> diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h
> index c5614444031f..10d91aeedaca 100644
> --- a/include/acpi/cppc_acpi.h
> +++ b/include/acpi/cppc_acpi.h
> @@ -108,12 +108,14 @@ struct cppc_perf_caps {
> u32 lowest_nonlinear_perf;
> u32 lowest_freq;
> u32 nominal_freq;
> + u32 energy_perf;
> };
>
> struct cppc_perf_ctrls {
> u32 max_perf;
> u32 min_perf;
> u32 desired_perf;
> + u32 energy_perf;
> };
>
> struct cppc_perf_fb_ctrs {
> @@ -149,6 +151,9 @@ extern bool cpc_ffh_supported(void);
> extern bool cpc_supported_by_cpu(void);
> extern int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val);
> extern int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val);
> +extern int cppc_set_auto_epp(int cpu, bool enable);
> +extern int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps);
> +extern int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls);
> #else /* !CONFIG_ACPI_CPPC_LIB */
> static inline int cppc_get_desired_perf(int cpunum, u64 *desired_perf)
> {
> @@ -202,6 +207,18 @@ static inline int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)
> {
> return -ENOTSUPP;
> }
> +static inline int cppc_set_auto_epp(int cpu, bool enable)
> +{
> + return -ENOTSUPP;
> +}
> +static inline int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
> +{
> + return -ENOTSUPP;
> +}
> +static inline int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps)
> +{
> + return -ENOTSUPP;
> +}
> #endif /* !CONFIG_ACPI_CPPC_LIB */
>
> #endif /* _CPPC_ACPI_H*/
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH v3 1/8] ACPI: CPPC: Add AMD pstate energy performance preference cppc control
2022-11-07 18:44 ` Limonciello, Mario
@ 2022-11-10 14:49 ` Rafael J. Wysocki
2022-11-10 15:51 ` Yuan, Perry
2022-11-13 16:28 ` Yuan, Perry
1 sibling, 1 reply; 35+ messages in thread
From: Rafael J. Wysocki @ 2022-11-10 14:49 UTC (permalink / raw)
To: Limonciello, Mario, Perry Yuan
Cc: rafael.j.wysocki, ray.huang, viresh.kumar, Deepak.Sharma,
Nathan.Fontenot, Alexander.Deucher, Shimmer.Huang, Xiaojian.Du,
Li.Meng, linux-pm, linux-kernel
On Mon, Nov 7, 2022 at 7:44 PM Limonciello, Mario
<mario.limonciello@amd.com> wrote:
>
> On 11/7/2022 11:56, Perry Yuan wrote:
> > Add the EPP(Energy Performance Preference) support for the
> > AMD SoCs without the dedicated CPPC MSR, those SoCs need to add this
> > cppc acpi functions to update EPP values and desired perf value.
>
> As far as I can tell this is generic code. Although the reason you're
> submitting it is for enabling AMD SoCs, the commit message should be
> worded as such.
>
> >
> > In order to get EPP worked, cppc_get_epp_caps() will query EPP preference
> > value and cppc_set_epp_perf() will set EPP new value.
> > Before the EPP works, pstate driver will use cppc_set_auto_epp() to
> > enable EPP function from firmware firstly.
>
> This could more succinctly say:
>
> "Add support for setting and querying EPP preferences to the generic
> CPPC driver. This enables downstream drivers such as amd-pstate to discover
> and use these values."
>
> >
> > Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
> > ---
> > drivers/acpi/cppc_acpi.c | 126 +++++++++++++++++++++++++++++++++++++++
> > include/acpi/cppc_acpi.h | 17 ++++++
> > 2 files changed, 143 insertions(+)
> >
> > diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
> > index 093675b1a1ff..d9c38dee1f48 100644
> > --- a/drivers/acpi/cppc_acpi.c
> > +++ b/drivers/acpi/cppc_acpi.c
> > @@ -1365,6 +1365,132 @@ int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
> > }
> > EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
> >
> > +/**
> > + * cppc_get_epp_caps - Get the energy preference register value.
> > + * @cpunum: CPU from which to get epp preference level.
> > + * @perf_caps: Return address.
> > + *
> > + * Return: 0 for success, -EIO otherwise.
> > + */
> > +int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps)
> > +{
> > + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
> > + struct cpc_register_resource *energy_perf_reg;
> > + u64 energy_perf;
> > +
> > + if (!cpc_desc) {
> > + pr_warn("No CPC descriptor for CPU:%d\n", cpunum);
> > + return -ENODEV;
> > + }
> > +
> > + energy_perf_reg = &cpc_desc->cpc_regs[ENERGY_PERF];
> > +
> > + if (!CPC_SUPPORTED(energy_perf_reg))
> > + pr_warn("energy perf reg update is unsupported!\n");
>
> No need to add a explanation point at the end.
>
> As this is a per-CPU message I wonder if this would be better as
> pr_warn_once()? Othewrise some systems with large numbers of cores
> might potentially show this message quite a few times.
pr_info_once() would suffice IMO.
> > +
> > + if (CPC_IN_PCC(energy_perf_reg)) {
> > + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
> > + struct cppc_pcc_data *pcc_ss_data = NULL;
> > + int ret = 0;
> > +
> > + if (pcc_ss_id < 0)
> > + return -ENODEV;
> > +
> > + pcc_ss_data = pcc_data[pcc_ss_id];
> > +
> > + down_write(&pcc_ss_data->pcc_lock);
> > +
> > + if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) {
> > + cpc_read(cpunum, energy_perf_reg, &energy_perf);
> > + perf_caps->energy_perf = energy_perf;
> > + } else {
> > + ret = -EIO;
> > + }
> > +
> > + up_write(&pcc_ss_data->pcc_lock);
> > +
> > + return ret;
> > + }
What if CPC is not in PCC?
Would returning 0 then work for all users?
> > +
> > + return 0;
> > +}
> > +EXPORT_SYMBOL_GPL(cppc_get_epp_caps);
> > +
> > +int cppc_set_auto_epp(int cpu, bool enable)
> > +{
> > + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
> > + struct cpc_register_resource *auto_sel_reg;
> > + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
> > + struct cppc_pcc_data *pcc_ss_data = NULL;
> > + int ret = -EINVAL;
> > +
> > + if (!cpc_desc) {
> > + pr_warn("No CPC descriptor for CPU:%d\n", cpu);
>
> Is this actually warn worthy? I would think it's fine a debug like we
> have for the other _CPC missing messages.
>
> > + return -EINVAL;
> > + }
> > +
> > + auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
> > +
> > + if (CPC_IN_PCC(auto_sel_reg)) {
> > + if (pcc_ss_id < 0)
> > + return -ENODEV;
> > +
> > + ret = cpc_write(cpu, auto_sel_reg, enable);
> > + if (ret)
> > + return ret;
> > +
> > + pcc_ss_data = pcc_data[pcc_ss_id];
> > +
> > + down_write(&pcc_ss_data->pcc_lock);
> > + /* after writing CPC, transfer the ownership of PCC to platform */
> > + ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
> > + up_write(&pcc_ss_data->pcc_lock);
> > + return ret;
> > + }
> > +
> > + return cpc_write(cpu, auto_sel_reg, enable);
> > +}
> > +EXPORT_SYMBOL_GPL(cppc_set_auto_epp);
> > +
> > +/*
> > + * Set Energy Performance Preference Register value through
> > + * Performance Controls Interface
> > + */
> > +int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
> > +{
> > + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
> > + struct cpc_register_resource *epp_set_reg;
> > + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
> > + struct cppc_pcc_data *pcc_ss_data = NULL;
> > + int ret = -EINVAL;
> > +
> > + if (!cpc_desc) {
> > + pr_warn("No CPC descriptor for CPU:%d\n", cpu);
>
> Is this actually warn worthy? I would think it's fine a debug like we
> have for the other _CPC missing messages.
>
> > + return -EINVAL;
> > + }
> > +
> > + epp_set_reg = &cpc_desc->cpc_regs[ENERGY_PERF];
> > +
> > + if (CPC_IN_PCC(epp_set_reg)) {
> > + if (pcc_ss_id < 0)
> > + return -ENODEV;
> > +
> > + ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf);
> > + if (ret)
> > + return ret;
> > +
> > + pcc_ss_data = pcc_data[pcc_ss_id];
> > +
> > + down_write(&pcc_ss_data->pcc_lock);
> > + /* after writing CPC, transfer the ownership of PCC to platform */
> > + ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
> > + up_write(&pcc_ss_data->pcc_lock);
>
> cppc_set_auto_epp and cppc_set_epp_perf have nearly the same code in the
> if block. I wonder if it's worth having a static helper function for
> this purpose that takes "reg" and "value" as arguments?
>
> > + }
And what about the non-PCC case here?
> > +
> > + return ret;
> > +}
> > +EXPORT_SYMBOL_GPL(cppc_set_epp_perf);
> > +
> > /**
> > * cppc_set_enable - Set to enable CPPC on the processor by writing the
> > * Continuous Performance Control package EnableRegister field.
> > diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h
> > index c5614444031f..10d91aeedaca 100644
> > --- a/include/acpi/cppc_acpi.h
> > +++ b/include/acpi/cppc_acpi.h
> > @@ -108,12 +108,14 @@ struct cppc_perf_caps {
> > u32 lowest_nonlinear_perf;
> > u32 lowest_freq;
> > u32 nominal_freq;
> > + u32 energy_perf;
> > };
> >
> > struct cppc_perf_ctrls {
> > u32 max_perf;
> > u32 min_perf;
> > u32 desired_perf;
> > + u32 energy_perf;
> > };
> >
> > struct cppc_perf_fb_ctrs {
> > @@ -149,6 +151,9 @@ extern bool cpc_ffh_supported(void);
> > extern bool cpc_supported_by_cpu(void);
> > extern int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val);
> > extern int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val);
> > +extern int cppc_set_auto_epp(int cpu, bool enable);
> > +extern int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps);
> > +extern int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls);
> > #else /* !CONFIG_ACPI_CPPC_LIB */
> > static inline int cppc_get_desired_perf(int cpunum, u64 *desired_perf)
> > {
> > @@ -202,6 +207,18 @@ static inline int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)
> > {
> > return -ENOTSUPP;
> > }
> > +static inline int cppc_set_auto_epp(int cpu, bool enable)
> > +{
> > + return -ENOTSUPP;
> > +}
> > +static inline int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
> > +{
> > + return -ENOTSUPP;
> > +}
> > +static inline int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps)
> > +{
> > + return -ENOTSUPP;
> > +}
> > #endif /* !CONFIG_ACPI_CPPC_LIB */
> >
> > #endif /* _CPPC_ACPI_H*/
>
^ permalink raw reply [flat|nested] 35+ messages in thread* RE: [PATCH v3 1/8] ACPI: CPPC: Add AMD pstate energy performance preference cppc control
2022-11-10 14:49 ` Rafael J. Wysocki
@ 2022-11-10 15:51 ` Yuan, Perry
2022-11-10 15:55 ` Rafael J. Wysocki
0 siblings, 1 reply; 35+ messages in thread
From: Yuan, Perry @ 2022-11-10 15:51 UTC (permalink / raw)
To: Rafael J. Wysocki, Limonciello, Mario
Cc: rafael.j.wysocki@intel.com, Huang, Ray, viresh.kumar@linaro.org,
Sharma, Deepak, Fontenot, Nathan, Deucher, Alexander,
Huang, Shimmer, Du, Xiaojian, Meng, Li (Jassmine),
linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org
[AMD Official Use Only - General]
> -----Original Message-----
> From: Rafael J. Wysocki <rafael@kernel.org>
> Sent: Thursday, November 10, 2022 10:50 PM
> To: Limonciello, Mario <Mario.Limonciello@amd.com>; Yuan, Perry
> <Perry.Yuan@amd.com>
> Cc: rafael.j.wysocki@intel.com; Huang, Ray <Ray.Huang@amd.com>;
> viresh.kumar@linaro.org; Sharma, Deepak <Deepak.Sharma@amd.com>;
> Fontenot, Nathan <Nathan.Fontenot@amd.com>; Deucher, Alexander
> <Alexander.Deucher@amd.com>; Huang, Shimmer
> <Shimmer.Huang@amd.com>; Du, Xiaojian <Xiaojian.Du@amd.com>; Meng,
> Li (Jassmine) <Li.Meng@amd.com>; linux-pm@vger.kernel.org; linux-
> kernel@vger.kernel.org
> Subject: Re: [PATCH v3 1/8] ACPI: CPPC: Add AMD pstate energy
> performance preference cppc control
>
> Caution: This message originated from an External Source. Use proper
> caution when opening attachments, clicking links, or responding.
>
>
> On Mon, Nov 7, 2022 at 7:44 PM Limonciello, Mario
> <mario.limonciello@amd.com> wrote:
> >
> > On 11/7/2022 11:56, Perry Yuan wrote:
> > > Add the EPP(Energy Performance Preference) support for the AMD SoCs
> > > without the dedicated CPPC MSR, those SoCs need to add this cppc
> > > acpi functions to update EPP values and desired perf value.
> >
> > As far as I can tell this is generic code. Although the reason you're
> > submitting it is for enabling AMD SoCs, the commit message should be
> > worded as such.
> >
> > >
> > > In order to get EPP worked, cppc_get_epp_caps() will query EPP
> > > preference value and cppc_set_epp_perf() will set EPP new value.
> > > Before the EPP works, pstate driver will use cppc_set_auto_epp() to
> > > enable EPP function from firmware firstly.
> >
> > This could more succinctly say:
> >
> > "Add support for setting and querying EPP preferences to the generic
> > CPPC driver. This enables downstream drivers such as amd-pstate to
> > discover and use these values."
> >
> > >
> > > Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
> > > ---
> > > drivers/acpi/cppc_acpi.c | 126
> +++++++++++++++++++++++++++++++++++++++
> > > include/acpi/cppc_acpi.h | 17 ++++++
> > > 2 files changed, 143 insertions(+)
> > >
> > > diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
> > > index 093675b1a1ff..d9c38dee1f48 100644
> > > --- a/drivers/acpi/cppc_acpi.c
> > > +++ b/drivers/acpi/cppc_acpi.c
> > > @@ -1365,6 +1365,132 @@ int cppc_get_perf_ctrs(int cpunum, struct
> cppc_perf_fb_ctrs *perf_fb_ctrs)
> > > }
> > > EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
> > >
> > > +/**
> > > + * cppc_get_epp_caps - Get the energy preference register value.
> > > + * @cpunum: CPU from which to get epp preference level.
> > > + * @perf_caps: Return address.
> > > + *
> > > + * Return: 0 for success, -EIO otherwise.
> > > + */
> > > +int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps)
> > > +{
> > > + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
> > > + struct cpc_register_resource *energy_perf_reg;
> > > + u64 energy_perf;
> > > +
> > > + if (!cpc_desc) {
> > > + pr_warn("No CPC descriptor for CPU:%d\n", cpunum);
> > > + return -ENODEV;
> > > + }
> > > +
> > > + energy_perf_reg = &cpc_desc->cpc_regs[ENERGY_PERF];
> > > +
> > > + if (!CPC_SUPPORTED(energy_perf_reg))
> > > + pr_warn("energy perf reg update is unsupported!\n");
> >
> > No need to add a explanation point at the end.
> >
> > As this is a per-CPU message I wonder if this would be better as
> > pr_warn_once()? Othewrise some systems with large numbers of cores
> > might potentially show this message quite a few times.
>
> pr_info_once() would suffice IMO.
Fixed in V4.
>
> > > +
> > > + if (CPC_IN_PCC(energy_perf_reg)) {
> > > + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
> > > + struct cppc_pcc_data *pcc_ss_data = NULL;
> > > + int ret = 0;
> > > +
> > > + if (pcc_ss_id < 0)
> > > + return -ENODEV;
> > > +
> > > + pcc_ss_data = pcc_data[pcc_ss_id];
> > > +
> > > + down_write(&pcc_ss_data->pcc_lock);
> > > +
> > > + if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) {
> > > + cpc_read(cpunum, energy_perf_reg, &energy_perf);
> > > + perf_caps->energy_perf = energy_perf;
> > > + } else {
> > > + ret = -EIO;
> > > + }
> > > +
> > > + up_write(&pcc_ss_data->pcc_lock);
> > > +
> > > + return ret;
> > > + }
>
> What if CPC is not in PCC?
>
> Would returning 0 then work for all users?
Fixed in V4
>
> > > +
> > > + return 0;
> > > +}
> > > +EXPORT_SYMBOL_GPL(cppc_get_epp_caps);
> > > +
> > > +int cppc_set_auto_epp(int cpu, bool enable) {
> > > + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
> > > + struct cpc_register_resource *auto_sel_reg;
> > > + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
> > > + struct cppc_pcc_data *pcc_ss_data = NULL;
> > > + int ret = -EINVAL;
> > > +
> > > + if (!cpc_desc) {
> > > + pr_warn("No CPC descriptor for CPU:%d\n", cpu);
> >
> > Is this actually warn worthy? I would think it's fine a debug like we
> > have for the other _CPC missing messages.
> >
> > > + return -EINVAL;
> > > + }
> > > +
> > > + auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
> > > +
> > > + if (CPC_IN_PCC(auto_sel_reg)) {
> > > + if (pcc_ss_id < 0)
> > > + return -ENODEV;
> > > +
> > > + ret = cpc_write(cpu, auto_sel_reg, enable);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + pcc_ss_data = pcc_data[pcc_ss_id];
> > > +
> > > + down_write(&pcc_ss_data->pcc_lock);
> > > + /* after writing CPC, transfer the ownership of PCC to platform */
> > > + ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
> > > + up_write(&pcc_ss_data->pcc_lock);
> > > + return ret;
> > > + }
> > > +
> > > + return cpc_write(cpu, auto_sel_reg, enable); }
> > > +EXPORT_SYMBOL_GPL(cppc_set_auto_epp);
> > > +
> > > +/*
> > > + * Set Energy Performance Preference Register value through
> > > + * Performance Controls Interface
> > > + */
> > > +int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
> > > +{
> > > + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
> > > + struct cpc_register_resource *epp_set_reg;
> > > + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
> > > + struct cppc_pcc_data *pcc_ss_data = NULL;
> > > + int ret = -EINVAL;
> > > +
> > > + if (!cpc_desc) {
> > > + pr_warn("No CPC descriptor for CPU:%d\n", cpu);
> >
> > Is this actually warn worthy? I would think it's fine a debug like we
> > have for the other _CPC missing messages.
> >
> > > + return -EINVAL;
> > > + }
> > > +
> > > + epp_set_reg = &cpc_desc->cpc_regs[ENERGY_PERF];
> > > +
> > > + if (CPC_IN_PCC(epp_set_reg)) {
> > > + if (pcc_ss_id < 0)
> > > + return -ENODEV;
> > > +
> > > + ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + pcc_ss_data = pcc_data[pcc_ss_id];
> > > +
> > > + down_write(&pcc_ss_data->pcc_lock);
> > > + /* after writing CPC, transfer the ownership of PCC to platform */
> > > + ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
> > > + up_write(&pcc_ss_data->pcc_lock);
> >
> > cppc_set_auto_epp and cppc_set_epp_perf have nearly the same code in
> > the if block. I wonder if it's worth having a static helper function
> > for this purpose that takes "reg" and "value" as arguments?
> >
> > > + }
>
> And what about the non-PCC case here?
I merge the cppc_set_auto_epp and cppc_set_epp_perf in V4.
For the non-PCC case, we canno set the EPP value to FW, then just returned
Error code. Is it Ok ?
>
> > > +
> > > + return ret;
> > > +}
> > > +EXPORT_SYMBOL_GPL(cppc_set_epp_perf);
> > > +
> > > /**
> > > * cppc_set_enable - Set to enable CPPC on the processor by writing the
> > > * Continuous Performance Control package EnableRegister field.
> > > diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h
> > > index c5614444031f..10d91aeedaca 100644
> > > --- a/include/acpi/cppc_acpi.h
> > > +++ b/include/acpi/cppc_acpi.h
> > > @@ -108,12 +108,14 @@ struct cppc_perf_caps {
> > > u32 lowest_nonlinear_perf;
> > > u32 lowest_freq;
> > > u32 nominal_freq;
> > > + u32 energy_perf;
> > > };
> > >
> > > struct cppc_perf_ctrls {
> > > u32 max_perf;
> > > u32 min_perf;
> > > u32 desired_perf;
> > > + u32 energy_perf;
> > > };
> > >
> > > struct cppc_perf_fb_ctrs {
> > > @@ -149,6 +151,9 @@ extern bool cpc_ffh_supported(void);
> > > extern bool cpc_supported_by_cpu(void);
> > > extern int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val);
> > > extern int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64
> > > val);
> > > +extern int cppc_set_auto_epp(int cpu, bool enable); extern int
> > > +cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps);
> > > +extern int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls
> > > +*perf_ctrls);
> > > #else /* !CONFIG_ACPI_CPPC_LIB */
> > > static inline int cppc_get_desired_perf(int cpunum, u64 *desired_perf)
> > > {
> > > @@ -202,6 +207,18 @@ static inline int cpc_write_ffh(int cpunum, struct
> cpc_reg *reg, u64 val)
> > > {
> > > return -ENOTSUPP;
> > > }
> > > +static inline int cppc_set_auto_epp(int cpu, bool enable) {
> > > + return -ENOTSUPP;
> > > +}
> > > +static inline int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls
> > > +*perf_ctrls) {
> > > + return -ENOTSUPP;
> > > +}
> > > +static inline int cppc_get_epp_caps(int cpunum, struct
> > > +cppc_perf_caps *perf_caps) {
> > > + return -ENOTSUPP;
> > > +}
> > > #endif /* !CONFIG_ACPI_CPPC_LIB */
> > >
> > > #endif /* _CPPC_ACPI_H*/
> >
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH v3 1/8] ACPI: CPPC: Add AMD pstate energy performance preference cppc control
2022-11-10 15:51 ` Yuan, Perry
@ 2022-11-10 15:55 ` Rafael J. Wysocki
2022-11-10 16:23 ` Yuan, Perry
0 siblings, 1 reply; 35+ messages in thread
From: Rafael J. Wysocki @ 2022-11-10 15:55 UTC (permalink / raw)
To: Yuan, Perry
Cc: Rafael J. Wysocki, Limonciello, Mario, rafael.j.wysocki@intel.com,
Huang, Ray, viresh.kumar@linaro.org, Sharma, Deepak,
Fontenot, Nathan, Deucher, Alexander, Huang, Shimmer,
Du, Xiaojian, Meng, Li (Jassmine), linux-pm@vger.kernel.org,
linux-kernel@vger.kernel.org
On Thu, Nov 10, 2022 at 4:52 PM Yuan, Perry <Perry.Yuan@amd.com> wrote:
>
> [AMD Official Use Only - General]
>
>
>
> > -----Original Message-----
> > From: Rafael J. Wysocki <rafael@kernel.org>
> > Sent: Thursday, November 10, 2022 10:50 PM
> > To: Limonciello, Mario <Mario.Limonciello@amd.com>; Yuan, Perry
> > <Perry.Yuan@amd.com>
> > Cc: rafael.j.wysocki@intel.com; Huang, Ray <Ray.Huang@amd.com>;
> > viresh.kumar@linaro.org; Sharma, Deepak <Deepak.Sharma@amd.com>;
> > Fontenot, Nathan <Nathan.Fontenot@amd.com>; Deucher, Alexander
> > <Alexander.Deucher@amd.com>; Huang, Shimmer
> > <Shimmer.Huang@amd.com>; Du, Xiaojian <Xiaojian.Du@amd.com>; Meng,
> > Li (Jassmine) <Li.Meng@amd.com>; linux-pm@vger.kernel.org; linux-
> > kernel@vger.kernel.org
> > Subject: Re: [PATCH v3 1/8] ACPI: CPPC: Add AMD pstate energy
> > performance preference cppc control
> >
> > Caution: This message originated from an External Source. Use proper
> > caution when opening attachments, clicking links, or responding.
> >
> >
> > On Mon, Nov 7, 2022 at 7:44 PM Limonciello, Mario
> > <mario.limonciello@amd.com> wrote:
> > >
> > > On 11/7/2022 11:56, Perry Yuan wrote:
> > > > Add the EPP(Energy Performance Preference) support for the AMD SoCs
> > > > without the dedicated CPPC MSR, those SoCs need to add this cppc
> > > > acpi functions to update EPP values and desired perf value.
> > >
> > > As far as I can tell this is generic code. Although the reason you're
> > > submitting it is for enabling AMD SoCs, the commit message should be
> > > worded as such.
> > >
> > > >
> > > > In order to get EPP worked, cppc_get_epp_caps() will query EPP
> > > > preference value and cppc_set_epp_perf() will set EPP new value.
> > > > Before the EPP works, pstate driver will use cppc_set_auto_epp() to
> > > > enable EPP function from firmware firstly.
> > >
> > > This could more succinctly say:
> > >
> > > "Add support for setting and querying EPP preferences to the generic
> > > CPPC driver. This enables downstream drivers such as amd-pstate to
> > > discover and use these values."
> > >
> > > >
> > > > Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
> > > > ---
> > > > drivers/acpi/cppc_acpi.c | 126
> > +++++++++++++++++++++++++++++++++++++++
> > > > include/acpi/cppc_acpi.h | 17 ++++++
> > > > 2 files changed, 143 insertions(+)
> > > >
> > > > diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
> > > > index 093675b1a1ff..d9c38dee1f48 100644
> > > > --- a/drivers/acpi/cppc_acpi.c
> > > > +++ b/drivers/acpi/cppc_acpi.c
> > > > @@ -1365,6 +1365,132 @@ int cppc_get_perf_ctrs(int cpunum, struct
> > cppc_perf_fb_ctrs *perf_fb_ctrs)
> > > > }
> > > > EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
> > > >
> > > > +/**
> > > > + * cppc_get_epp_caps - Get the energy preference register value.
> > > > + * @cpunum: CPU from which to get epp preference level.
> > > > + * @perf_caps: Return address.
> > > > + *
> > > > + * Return: 0 for success, -EIO otherwise.
> > > > + */
> > > > +int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps)
> > > > +{
> > > > + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
> > > > + struct cpc_register_resource *energy_perf_reg;
> > > > + u64 energy_perf;
> > > > +
> > > > + if (!cpc_desc) {
> > > > + pr_warn("No CPC descriptor for CPU:%d\n", cpunum);
> > > > + return -ENODEV;
> > > > + }
> > > > +
> > > > + energy_perf_reg = &cpc_desc->cpc_regs[ENERGY_PERF];
> > > > +
> > > > + if (!CPC_SUPPORTED(energy_perf_reg))
> > > > + pr_warn("energy perf reg update is unsupported!\n");
> > >
> > > No need to add a explanation point at the end.
> > >
> > > As this is a per-CPU message I wonder if this would be better as
> > > pr_warn_once()? Othewrise some systems with large numbers of cores
> > > might potentially show this message quite a few times.
> >
> > pr_info_once() would suffice IMO.
>
> Fixed in V4.
>
> >
> > > > +
> > > > + if (CPC_IN_PCC(energy_perf_reg)) {
> > > > + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
> > > > + struct cppc_pcc_data *pcc_ss_data = NULL;
> > > > + int ret = 0;
> > > > +
> > > > + if (pcc_ss_id < 0)
> > > > + return -ENODEV;
> > > > +
> > > > + pcc_ss_data = pcc_data[pcc_ss_id];
> > > > +
> > > > + down_write(&pcc_ss_data->pcc_lock);
> > > > +
> > > > + if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) {
> > > > + cpc_read(cpunum, energy_perf_reg, &energy_perf);
> > > > + perf_caps->energy_perf = energy_perf;
> > > > + } else {
> > > > + ret = -EIO;
> > > > + }
> > > > +
> > > > + up_write(&pcc_ss_data->pcc_lock);
> > > > +
> > > > + return ret;
> > > > + }
> >
> > What if CPC is not in PCC?
> >
> > Would returning 0 then work for all users?
>
> Fixed in V4
>
> >
> > > > +
> > > > + return 0;
> > > > +}
> > > > +EXPORT_SYMBOL_GPL(cppc_get_epp_caps);
> > > > +
> > > > +int cppc_set_auto_epp(int cpu, bool enable) {
> > > > + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
> > > > + struct cpc_register_resource *auto_sel_reg;
> > > > + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
> > > > + struct cppc_pcc_data *pcc_ss_data = NULL;
> > > > + int ret = -EINVAL;
> > > > +
> > > > + if (!cpc_desc) {
> > > > + pr_warn("No CPC descriptor for CPU:%d\n", cpu);
> > >
> > > Is this actually warn worthy? I would think it's fine a debug like we
> > > have for the other _CPC missing messages.
> > >
> > > > + return -EINVAL;
> > > > + }
> > > > +
> > > > + auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
> > > > +
> > > > + if (CPC_IN_PCC(auto_sel_reg)) {
> > > > + if (pcc_ss_id < 0)
> > > > + return -ENODEV;
> > > > +
> > > > + ret = cpc_write(cpu, auto_sel_reg, enable);
> > > > + if (ret)
> > > > + return ret;
> > > > +
> > > > + pcc_ss_data = pcc_data[pcc_ss_id];
> > > > +
> > > > + down_write(&pcc_ss_data->pcc_lock);
> > > > + /* after writing CPC, transfer the ownership of PCC to platform */
> > > > + ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
> > > > + up_write(&pcc_ss_data->pcc_lock);
> > > > + return ret;
> > > > + }
> > > > +
> > > > + return cpc_write(cpu, auto_sel_reg, enable); }
> > > > +EXPORT_SYMBOL_GPL(cppc_set_auto_epp);
> > > > +
> > > > +/*
> > > > + * Set Energy Performance Preference Register value through
> > > > + * Performance Controls Interface
> > > > + */
> > > > +int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
> > > > +{
> > > > + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
> > > > + struct cpc_register_resource *epp_set_reg;
> > > > + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
> > > > + struct cppc_pcc_data *pcc_ss_data = NULL;
> > > > + int ret = -EINVAL;
> > > > +
> > > > + if (!cpc_desc) {
> > > > + pr_warn("No CPC descriptor for CPU:%d\n", cpu);
> > >
> > > Is this actually warn worthy? I would think it's fine a debug like we
> > > have for the other _CPC missing messages.
> > >
> > > > + return -EINVAL;
> > > > + }
> > > > +
> > > > + epp_set_reg = &cpc_desc->cpc_regs[ENERGY_PERF];
> > > > +
> > > > + if (CPC_IN_PCC(epp_set_reg)) {
> > > > + if (pcc_ss_id < 0)
> > > > + return -ENODEV;
> > > > +
> > > > + ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf);
> > > > + if (ret)
> > > > + return ret;
> > > > +
> > > > + pcc_ss_data = pcc_data[pcc_ss_id];
> > > > +
> > > > + down_write(&pcc_ss_data->pcc_lock);
> > > > + /* after writing CPC, transfer the ownership of PCC to platform */
> > > > + ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
> > > > + up_write(&pcc_ss_data->pcc_lock);
> > >
> > > cppc_set_auto_epp and cppc_set_epp_perf have nearly the same code in
> > > the if block. I wonder if it's worth having a static helper function
> > > for this purpose that takes "reg" and "value" as arguments?
> > >
> > > > + }
> >
> > And what about the non-PCC case here?
>
> I merge the cppc_set_auto_epp and cppc_set_epp_perf in V4.
> For the non-PCC case, we canno set the EPP value to FW, then just returned
> Error code. Is it Ok ?
Yes, if it cannot be updated, it should be treated the same way as
unsupported IMV.
^ permalink raw reply [flat|nested] 35+ messages in thread* RE: [PATCH v3 1/8] ACPI: CPPC: Add AMD pstate energy performance preference cppc control
2022-11-10 15:55 ` Rafael J. Wysocki
@ 2022-11-10 16:23 ` Yuan, Perry
0 siblings, 0 replies; 35+ messages in thread
From: Yuan, Perry @ 2022-11-10 16:23 UTC (permalink / raw)
To: Rafael J. Wysocki
Cc: Limonciello, Mario, rafael.j.wysocki@intel.com, Huang, Ray,
viresh.kumar@linaro.org, Sharma, Deepak, Fontenot, Nathan,
Deucher, Alexander, Huang, Shimmer, Du, Xiaojian,
Meng, Li (Jassmine), linux-pm@vger.kernel.org,
linux-kernel@vger.kernel.org
[AMD Official Use Only - General]
Hi Rafael.
> -----Original Message-----
> From: Rafael J. Wysocki <rafael@kernel.org>
> Sent: Thursday, November 10, 2022 11:56 PM
> To: Yuan, Perry <Perry.Yuan@amd.com>
> Cc: Rafael J. Wysocki <rafael@kernel.org>; Limonciello, Mario
> <Mario.Limonciello@amd.com>; rafael.j.wysocki@intel.com; Huang, Ray
> <Ray.Huang@amd.com>; viresh.kumar@linaro.org; Sharma, Deepak
> <Deepak.Sharma@amd.com>; Fontenot, Nathan
> <Nathan.Fontenot@amd.com>; Deucher, Alexander
> <Alexander.Deucher@amd.com>; Huang, Shimmer
> <Shimmer.Huang@amd.com>; Du, Xiaojian <Xiaojian.Du@amd.com>; Meng,
> Li (Jassmine) <Li.Meng@amd.com>; linux-pm@vger.kernel.org; linux-
> kernel@vger.kernel.org
> Subject: Re: [PATCH v3 1/8] ACPI: CPPC: Add AMD pstate energy
> performance preference cppc control
>
> Caution: This message originated from an External Source. Use proper
> caution when opening attachments, clicking links, or responding.
>
>
> On Thu, Nov 10, 2022 at 4:52 PM Yuan, Perry <Perry.Yuan@amd.com> wrote:
> >
> > [AMD Official Use Only - General]
> >
> >
> >
> > > -----Original Message-----
> > > From: Rafael J. Wysocki <rafael@kernel.org>
> > > Sent: Thursday, November 10, 2022 10:50 PM
> > > To: Limonciello, Mario <Mario.Limonciello@amd.com>; Yuan, Perry
> > > <Perry.Yuan@amd.com>
> > > Cc: rafael.j.wysocki@intel.com; Huang, Ray <Ray.Huang@amd.com>;
> > > viresh.kumar@linaro.org; Sharma, Deepak <Deepak.Sharma@amd.com>;
> > > Fontenot, Nathan <Nathan.Fontenot@amd.com>; Deucher, Alexander
> > > <Alexander.Deucher@amd.com>; Huang, Shimmer
> <Shimmer.Huang@amd.com>;
> > > Du, Xiaojian <Xiaojian.Du@amd.com>; Meng, Li (Jassmine)
> > > <Li.Meng@amd.com>; linux-pm@vger.kernel.org; linux-
> > > kernel@vger.kernel.org
> > > Subject: Re: [PATCH v3 1/8] ACPI: CPPC: Add AMD pstate energy
> > > performance preference cppc control
> > >
> > > Caution: This message originated from an External Source. Use proper
> > > caution when opening attachments, clicking links, or responding.
> > >
> > >
> > > On Mon, Nov 7, 2022 at 7:44 PM Limonciello, Mario
> > > <mario.limonciello@amd.com> wrote:
> > > >
> > > > On 11/7/2022 11:56, Perry Yuan wrote:
> > > > > Add the EPP(Energy Performance Preference) support for the AMD
> > > > > SoCs without the dedicated CPPC MSR, those SoCs need to add this
> > > > > cppc acpi functions to update EPP values and desired perf value.
> > > >
> > > > As far as I can tell this is generic code. Although the reason
> > > > you're submitting it is for enabling AMD SoCs, the commit message
> > > > should be worded as such.
> > > >
> > > > >
> > > > > In order to get EPP worked, cppc_get_epp_caps() will query EPP
> > > > > preference value and cppc_set_epp_perf() will set EPP new value.
> > > > > Before the EPP works, pstate driver will use cppc_set_auto_epp()
> > > > > to enable EPP function from firmware firstly.
> > > >
> > > > This could more succinctly say:
> > > >
> > > > "Add support for setting and querying EPP preferences to the
> > > > generic CPPC driver. This enables downstream drivers such as
> > > > amd-pstate to discover and use these values."
> > > >
> > > > >
> > > > > Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
> > > > > ---
> > > > > drivers/acpi/cppc_acpi.c | 126
> > > +++++++++++++++++++++++++++++++++++++++
> > > > > include/acpi/cppc_acpi.h | 17 ++++++
> > > > > 2 files changed, 143 insertions(+)
> > > > >
> > > > > diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
> > > > > index 093675b1a1ff..d9c38dee1f48 100644
> > > > > --- a/drivers/acpi/cppc_acpi.c
> > > > > +++ b/drivers/acpi/cppc_acpi.c
> > > > > @@ -1365,6 +1365,132 @@ int cppc_get_perf_ctrs(int cpunum,
> > > > > struct
> > > cppc_perf_fb_ctrs *perf_fb_ctrs)
> > > > > }
> > > > > EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
> > > > >
> > > > > +/**
> > > > > + * cppc_get_epp_caps - Get the energy preference register value.
> > > > > + * @cpunum: CPU from which to get epp preference level.
> > > > > + * @perf_caps: Return address.
> > > > > + *
> > > > > + * Return: 0 for success, -EIO otherwise.
> > > > > + */
> > > > > +int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps
> > > > > +*perf_caps) {
> > > > > + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
> > > > > + struct cpc_register_resource *energy_perf_reg;
> > > > > + u64 energy_perf;
> > > > > +
> > > > > + if (!cpc_desc) {
> > > > > + pr_warn("No CPC descriptor for CPU:%d\n", cpunum);
> > > > > + return -ENODEV;
> > > > > + }
> > > > > +
> > > > > + energy_perf_reg = &cpc_desc->cpc_regs[ENERGY_PERF];
> > > > > +
> > > > > + if (!CPC_SUPPORTED(energy_perf_reg))
> > > > > + pr_warn("energy perf reg update is
> > > > > + unsupported!\n");
> > > >
> > > > No need to add a explanation point at the end.
> > > >
> > > > As this is a per-CPU message I wonder if this would be better as
> > > > pr_warn_once()? Othewrise some systems with large numbers of
> > > > cores might potentially show this message quite a few times.
> > >
> > > pr_info_once() would suffice IMO.
> >
> > Fixed in V4.
> >
> > >
> > > > > +
> > > > > + if (CPC_IN_PCC(energy_perf_reg)) {
> > > > > + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
> > > > > + struct cppc_pcc_data *pcc_ss_data = NULL;
> > > > > + int ret = 0;
> > > > > +
> > > > > + if (pcc_ss_id < 0)
> > > > > + return -ENODEV;
> > > > > +
> > > > > + pcc_ss_data = pcc_data[pcc_ss_id];
> > > > > +
> > > > > + down_write(&pcc_ss_data->pcc_lock);
> > > > > +
> > > > > + if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) {
> > > > > + cpc_read(cpunum, energy_perf_reg, &energy_perf);
> > > > > + perf_caps->energy_perf = energy_perf;
> > > > > + } else {
> > > > > + ret = -EIO;
> > > > > + }
> > > > > +
> > > > > + up_write(&pcc_ss_data->pcc_lock);
> > > > > +
> > > > > + return ret;
> > > > > + }
> > >
> > > What if CPC is not in PCC?
> > >
> > > Would returning 0 then work for all users?
> >
> > Fixed in V4
> >
> > >
> > > > > +
> > > > > + return 0;
> > > > > +}
> > > > > +EXPORT_SYMBOL_GPL(cppc_get_epp_caps);
> > > > > +
> > > > > +int cppc_set_auto_epp(int cpu, bool enable) {
> > > > > + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
> > > > > + struct cpc_register_resource *auto_sel_reg;
> > > > > + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
> > > > > + struct cppc_pcc_data *pcc_ss_data = NULL;
> > > > > + int ret = -EINVAL;
> > > > > +
> > > > > + if (!cpc_desc) {
> > > > > + pr_warn("No CPC descriptor for CPU:%d\n", cpu);
> > > >
> > > > Is this actually warn worthy? I would think it's fine a debug
> > > > like we have for the other _CPC missing messages.
> > > >
> > > > > + return -EINVAL;
> > > > > + }
> > > > > +
> > > > > + auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
> > > > > +
> > > > > + if (CPC_IN_PCC(auto_sel_reg)) {
> > > > > + if (pcc_ss_id < 0)
> > > > > + return -ENODEV;
> > > > > +
> > > > > + ret = cpc_write(cpu, auto_sel_reg, enable);
> > > > > + if (ret)
> > > > > + return ret;
> > > > > +
> > > > > + pcc_ss_data = pcc_data[pcc_ss_id];
> > > > > +
> > > > > + down_write(&pcc_ss_data->pcc_lock);
> > > > > + /* after writing CPC, transfer the ownership of PCC to
> platform */
> > > > > + ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
> > > > > + up_write(&pcc_ss_data->pcc_lock);
> > > > > + return ret;
> > > > > + }
> > > > > +
> > > > > + return cpc_write(cpu, auto_sel_reg, enable); }
> > > > > +EXPORT_SYMBOL_GPL(cppc_set_auto_epp);
> > > > > +
> > > > > +/*
> > > > > + * Set Energy Performance Preference Register value through
> > > > > + * Performance Controls Interface */ int cppc_set_epp_perf(int
> > > > > +cpu, struct cppc_perf_ctrls *perf_ctrls) {
> > > > > + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
> > > > > + struct cpc_register_resource *epp_set_reg;
> > > > > + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
> > > > > + struct cppc_pcc_data *pcc_ss_data = NULL;
> > > > > + int ret = -EINVAL;
> > > > > +
> > > > > + if (!cpc_desc) {
> > > > > + pr_warn("No CPC descriptor for CPU:%d\n", cpu);
> > > >
> > > > Is this actually warn worthy? I would think it's fine a debug
> > > > like we have for the other _CPC missing messages.
> > > >
> > > > > + return -EINVAL;
> > > > > + }
> > > > > +
> > > > > + epp_set_reg = &cpc_desc->cpc_regs[ENERGY_PERF];
> > > > > +
> > > > > + if (CPC_IN_PCC(epp_set_reg)) {
> > > > > + if (pcc_ss_id < 0)
> > > > > + return -ENODEV;
> > > > > +
> > > > > + ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf);
> > > > > + if (ret)
> > > > > + return ret;
> > > > > +
> > > > > + pcc_ss_data = pcc_data[pcc_ss_id];
> > > > > +
> > > > > + down_write(&pcc_ss_data->pcc_lock);
> > > > > + /* after writing CPC, transfer the ownership of PCC to
> platform */
> > > > > + ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
> > > > > + up_write(&pcc_ss_data->pcc_lock);
> > > >
> > > > cppc_set_auto_epp and cppc_set_epp_perf have nearly the same
> code
> > > > in the if block. I wonder if it's worth having a static helper
> > > > function for this purpose that takes "reg" and "value" as arguments?
> > > >
> > > > > + }
> > >
> > > And what about the non-PCC case here?
> >
> > I merge the cppc_set_auto_epp and cppc_set_epp_perf in V4.
> > For the non-PCC case, we canno set the EPP value to FW, then just
> > returned Error code. Is it Ok ?
>
> Yes, if it cannot be updated, it should be treated the same way as
> unsupported IMV.
Make sense, I will make change for this in V4 and you can help to take a look at V4.
Thanks.
Perry .
^ permalink raw reply [flat|nested] 35+ messages in thread
* RE: [PATCH v3 1/8] ACPI: CPPC: Add AMD pstate energy performance preference cppc control
2022-11-07 18:44 ` Limonciello, Mario
2022-11-10 14:49 ` Rafael J. Wysocki
@ 2022-11-13 16:28 ` Yuan, Perry
1 sibling, 0 replies; 35+ messages in thread
From: Yuan, Perry @ 2022-11-13 16:28 UTC (permalink / raw)
To: Limonciello, Mario, rafael.j.wysocki@intel.com, Huang, Ray,
viresh.kumar@linaro.org
Cc: Sharma, Deepak, Fontenot, Nathan, Deucher, Alexander,
Huang, Shimmer, Du, Xiaojian, Meng, Li (Jassmine),
linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org
[AMD Official Use Only - General]
Hi Mario,
> -----Original Message-----
> From: Limonciello, Mario <Mario.Limonciello@amd.com>
> Sent: Tuesday, November 8, 2022 2:45 AM
> To: Yuan, Perry <Perry.Yuan@amd.com>; rafael.j.wysocki@intel.com; Huang,
> Ray <Ray.Huang@amd.com>; viresh.kumar@linaro.org
> Cc: Sharma, Deepak <Deepak.Sharma@amd.com>; Fontenot, Nathan
> <Nathan.Fontenot@amd.com>; Deucher, Alexander
> <Alexander.Deucher@amd.com>; Huang, Shimmer
> <Shimmer.Huang@amd.com>; Du, Xiaojian <Xiaojian.Du@amd.com>; Meng,
> Li (Jassmine) <Li.Meng@amd.com>; linux-pm@vger.kernel.org; linux-
> kernel@vger.kernel.org
> Subject: Re: [PATCH v3 1/8] ACPI: CPPC: Add AMD pstate energy performance
> preference cppc control
>
> On 11/7/2022 11:56, Perry Yuan wrote:
> > Add the EPP(Energy Performance Preference) support for the AMD SoCs
> > without the dedicated CPPC MSR, those SoCs need to add this cppc acpi
> > functions to update EPP values and desired perf value.
>
> As far as I can tell this is generic code. Although the reason you're submitting
> it is for enabling AMD SoCs, the commit message should be worded as such.
>
Thanks for your suggestions, fixed in V4.
> >
> > In order to get EPP worked, cppc_get_epp_caps() will query EPP
> > preference value and cppc_set_epp_perf() will set EPP new value.
> > Before the EPP works, pstate driver will use cppc_set_auto_epp() to
> > enable EPP function from firmware firstly.
>
> This could more succinctly say:
>
> "Add support for setting and querying EPP preferences to the generic CPPC
> driver. This enables downstream drivers such as amd-pstate to discover and
> use these values."
>
Changed in v4 as you suggested.
> >
> > Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
> > ---
> > drivers/acpi/cppc_acpi.c | 126
> +++++++++++++++++++++++++++++++++++++++
> > include/acpi/cppc_acpi.h | 17 ++++++
> > 2 files changed, 143 insertions(+)
> >
> > diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index
> > 093675b1a1ff..d9c38dee1f48 100644
> > --- a/drivers/acpi/cppc_acpi.c
> > +++ b/drivers/acpi/cppc_acpi.c
> > @@ -1365,6 +1365,132 @@ int cppc_get_perf_ctrs(int cpunum, struct
> cppc_perf_fb_ctrs *perf_fb_ctrs)
> > }
> > EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
> >
> > +/**
> > + * cppc_get_epp_caps - Get the energy preference register value.
> > + * @cpunum: CPU from which to get epp preference level.
> > + * @perf_caps: Return address.
> > + *
> > + * Return: 0 for success, -EIO otherwise.
> > + */
> > +int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps) {
> > + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
> > + struct cpc_register_resource *energy_perf_reg;
> > + u64 energy_perf;
> > +
> > + if (!cpc_desc) {
> > + pr_warn("No CPC descriptor for CPU:%d\n", cpunum);
> > + return -ENODEV;
> > + }
> > +
> > + energy_perf_reg = &cpc_desc->cpc_regs[ENERGY_PERF];
> > +
> > + if (!CPC_SUPPORTED(energy_perf_reg))
> > + pr_warn("energy perf reg update is unsupported!\n");
>
> No need to add a explanation point at the end.
>
> As this is a per-CPU message I wonder if this would be better as
> pr_warn_once()? Othewrise some systems with large numbers of cores
> might potentially show this message quite a few times.
I made some new changes and combined the two Epp call functions.
Remove some unnecessary log printing.
Please help to take a look at the V4 if you have any concerns.
Perry .
>
> > +
> > + if (CPC_IN_PCC(energy_perf_reg)) {
> > + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
> > + struct cppc_pcc_data *pcc_ss_data = NULL;
> > + int ret = 0;
> > +
> > + if (pcc_ss_id < 0)
> > + return -ENODEV;
> > +
> > + pcc_ss_data = pcc_data[pcc_ss_id];
> > +
> > + down_write(&pcc_ss_data->pcc_lock);
> > +
> > + if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) {
> > + cpc_read(cpunum, energy_perf_reg, &energy_perf);
> > + perf_caps->energy_perf = energy_perf;
> > + } else {
> > + ret = -EIO;
> > + }
> > +
> > + up_write(&pcc_ss_data->pcc_lock);
> > +
> > + return ret;
> > + }
> > +
> > + return 0;
> > +}
> > +EXPORT_SYMBOL_GPL(cppc_get_epp_caps);
> > +
> > +int cppc_set_auto_epp(int cpu, bool enable) {
> > + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
> > + struct cpc_register_resource *auto_sel_reg;
> > + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
> > + struct cppc_pcc_data *pcc_ss_data = NULL;
> > + int ret = -EINVAL;
> > +
> > + if (!cpc_desc) {
> > + pr_warn("No CPC descriptor for CPU:%d\n", cpu);
>
> Is this actually warn worthy? I would think it's fine a debug like we have for
> the other _CPC missing messages.
>
Fixed in V4.
> > + return -EINVAL;
> > + }
> > +
> > + auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
> > +
> > + if (CPC_IN_PCC(auto_sel_reg)) {
> > + if (pcc_ss_id < 0)
> > + return -ENODEV;
> > +
> > + ret = cpc_write(cpu, auto_sel_reg, enable);
> > + if (ret)
> > + return ret;
> > +
> > + pcc_ss_data = pcc_data[pcc_ss_id];
> > +
> > + down_write(&pcc_ss_data->pcc_lock);
> > + /* after writing CPC, transfer the ownership of PCC to
> platform */
> > + ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
> > + up_write(&pcc_ss_data->pcc_lock);
> > + return ret;
> > + }
> > +
> > + return cpc_write(cpu, auto_sel_reg, enable); }
> > +EXPORT_SYMBOL_GPL(cppc_set_auto_epp);
> > +
> > +/*
> > + * Set Energy Performance Preference Register value through
> > + * Performance Controls Interface
> > + */
> > +int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) {
> > + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
> > + struct cpc_register_resource *epp_set_reg;
> > + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
> > + struct cppc_pcc_data *pcc_ss_data = NULL;
> > + int ret = -EINVAL;
> > +
> > + if (!cpc_desc) {
> > + pr_warn("No CPC descriptor for CPU:%d\n", cpu);
>
> Is this actually warn worthy? I would think it's fine a debug like we have for
> the other _CPC missing messages.
Fixed in V4.
>
> > + return -EINVAL;
> > + }
> > +
> > + epp_set_reg = &cpc_desc->cpc_regs[ENERGY_PERF];
> > +
> > + if (CPC_IN_PCC(epp_set_reg)) {
> > + if (pcc_ss_id < 0)
> > + return -ENODEV;
> > +
> > + ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf);
> > + if (ret)
> > + return ret;
> > +
> > + pcc_ss_data = pcc_data[pcc_ss_id];
> > +
> > + down_write(&pcc_ss_data->pcc_lock);
> > + /* after writing CPC, transfer the ownership of PCC to
> platform */
> > + ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
> > + up_write(&pcc_ss_data->pcc_lock);
>
> cppc_set_auto_epp and cppc_set_epp_perf have nearly the same code in the
> if block. I wonder if it's worth having a static helper function for this purpose
> that takes "reg" and "value" as arguments?
Good idea, Ray also suggested to merge them.
I combined the two calls into single in V4.
Please take a look.
Perry.
>
> > + }
> > +
> > + return ret;
> > +}
> > +EXPORT_SYMBOL_GPL(cppc_set_epp_perf);
> > +
> > /**
> > * cppc_set_enable - Set to enable CPPC on the processor by writing the
> > * Continuous Performance Control package EnableRegister field.
> > diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index
> > c5614444031f..10d91aeedaca 100644
> > --- a/include/acpi/cppc_acpi.h
> > +++ b/include/acpi/cppc_acpi.h
> > @@ -108,12 +108,14 @@ struct cppc_perf_caps {
> > u32 lowest_nonlinear_perf;
> > u32 lowest_freq;
> > u32 nominal_freq;
> > + u32 energy_perf;
> > };
> >
> > struct cppc_perf_ctrls {
> > u32 max_perf;
> > u32 min_perf;
> > u32 desired_perf;
> > + u32 energy_perf;
> > };
> >
> > struct cppc_perf_fb_ctrs {
> > @@ -149,6 +151,9 @@ extern bool cpc_ffh_supported(void);
> > extern bool cpc_supported_by_cpu(void);
> > extern int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val);
> > extern int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val);
> > +extern int cppc_set_auto_epp(int cpu, bool enable); extern int
> > +cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps);
> > +extern int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls
> > +*perf_ctrls);
> > #else /* !CONFIG_ACPI_CPPC_LIB */
> > static inline int cppc_get_desired_perf(int cpunum, u64 *desired_perf)
> > {
> > @@ -202,6 +207,18 @@ static inline int cpc_write_ffh(int cpunum, struct
> cpc_reg *reg, u64 val)
> > {
> > return -ENOTSUPP;
> > }
> > +static inline int cppc_set_auto_epp(int cpu, bool enable) {
> > + return -ENOTSUPP;
> > +}
> > +static inline int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls
> > +*perf_ctrls) {
> > + return -ENOTSUPP;
> > +}
> > +static inline int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps
> > +*perf_caps) {
> > + return -ENOTSUPP;
> > +}
> > #endif /* !CONFIG_ACPI_CPPC_LIB */
> >
> > #endif /* _CPPC_ACPI_H*/
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v3 2/8] Documentation: amd-pstate: add EPP profiles introduction
2022-11-07 17:56 [PATCH v3 0/8] Implement AMD Pstate EPP Driver Perry Yuan
2022-11-07 17:56 ` [PATCH v3 1/8] ACPI: CPPC: Add AMD pstate energy performance preference cppc control Perry Yuan
@ 2022-11-07 17:56 ` Perry Yuan
2022-11-07 18:33 ` Limonciello, Mario
2022-11-10 14:57 ` Rafael J. Wysocki
2022-11-07 17:57 ` [PATCH v3 3/8] cpufreq: amd-pstate: change driver to be built-in type Perry Yuan
` (5 subsequent siblings)
7 siblings, 2 replies; 35+ messages in thread
From: Perry Yuan @ 2022-11-07 17:56 UTC (permalink / raw)
To: rafael.j.wysocki, ray.huang, viresh.kumar
Cc: Deepak.Sharma, Mario.Limonciello, Nathan.Fontenot,
Alexander.Deucher, Shimmer.Huang, Xiaojian.Du, Li.Meng, linux-pm,
linux-kernel, Perry Yuan
The patch add AMD pstate EPP feature introduction and what EPP
preference supported for AMD processors.
User can get supported list from
energy_performance_available_preferences attribute file, or update
current profile to energy_performance_preference file
1) See all EPP profiles
$ sudo cat /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_available_preferences
default performance balance_performance balance_power power
2) Check current EPP profile
$ sudo cat /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_preference
performance
3) Set new EPP profile
$ sudo bash -c "echo power > /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_preference"
Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
---
Documentation/admin-guide/pm/amd-pstate.rst | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst
index 8f3d30c5a0d8..78c6525d5a49 100644
--- a/Documentation/admin-guide/pm/amd-pstate.rst
+++ b/Documentation/admin-guide/pm/amd-pstate.rst
@@ -262,6 +262,25 @@ lowest non-linear performance in `AMD CPPC Performance Capability
<perf_cap_>`_.)
This attribute is read-only.
+``energy_performance_available_preferences``
+
+All the supported EPP preference could be selected, List of the strings that
+can be set to the ``energy_performance_preference`` attribute
+those different profiles represent different energy vs efficiency hints provided
+to low-level firmware
+however, the ``default`` represents the epp value is set by platform firmware
+This attribute is read-only.
+
+``energy_performance_preference``
+
+The current energy performance preference can be read from this attribute.
+and user can change current preference according to energy or performance needs
+Please get all support profiles list from
+``energy_performance_available_preferences`` attribute, all the profiles are
+integer values defined between 0 to 255 when EPP feature is enabled by platform
+firmware, if EPP feature is disabled, driver will ignore the written value
+This attribute is read-write.
+
Other performance and frequency values can be read back from
``/sys/devices/system/cpu/cpuX/acpi_cppc/``, see :ref:`cppc_sysfs`.
--
2.34.1
^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [PATCH v3 2/8] Documentation: amd-pstate: add EPP profiles introduction
2022-11-07 17:56 ` [PATCH v3 2/8] Documentation: amd-pstate: add EPP profiles introduction Perry Yuan
@ 2022-11-07 18:33 ` Limonciello, Mario
2022-11-13 16:23 ` Yuan, Perry
2022-11-10 14:57 ` Rafael J. Wysocki
1 sibling, 1 reply; 35+ messages in thread
From: Limonciello, Mario @ 2022-11-07 18:33 UTC (permalink / raw)
To: Perry Yuan, rafael.j.wysocki, ray.huang, viresh.kumar
Cc: Deepak.Sharma, Nathan.Fontenot, Alexander.Deucher, Shimmer.Huang,
Xiaojian.Du, Li.Meng, linux-pm, linux-kernel
On 11/7/2022 11:56, Perry Yuan wrote:
> The patch add AMD pstate EPP feature introduction and what EPP
> preference supported for AMD processors.
>
> User can get supported list from
> energy_performance_available_preferences attribute file, or update
> current profile to energy_performance_preference file
>
> 1) See all EPP profiles
> $ sudo cat /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_available_preferences
> default performance balance_performance balance_power power
>
> 2) Check current EPP profile
> $ sudo cat /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_preference
> performance
>
> 3) Set new EPP profile
> $ sudo bash -c "echo power > /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_preference"
>
> Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
> ---
> Documentation/admin-guide/pm/amd-pstate.rst | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst
> index 8f3d30c5a0d8..78c6525d5a49 100644
> --- a/Documentation/admin-guide/pm/amd-pstate.rst
> +++ b/Documentation/admin-guide/pm/amd-pstate.rst
> @@ -262,6 +262,25 @@ lowest non-linear performance in `AMD CPPC Performance Capability
> <perf_cap_>`_.)
> This attribute is read-only.
> > +``energy_performance_available_preferences``
> +
> +All the supported EPP preference could be selected, List of the strings that
> +can be set to the ``energy_performance_preference`` attribute
> +those different profiles represent different energy vs efficiency hints provided
> +to low-level firmware
> +however, the ``default`` represents the epp value is set by platform firmware
> +This attribute is read-only.
My proposal at rewording it.
A list of all the supported EPP preferences that could be used for
``energy_performance_preference` on this system.
These profiles represent different hints that are provided
to the low-level firmware about the user's desired energy vs efficiency
tradeoff. ``default`` represents the epp value is set by platform
firmware. This attribute is read-only.
> +
> +``energy_performance_preference``
> +
> +The current energy performance preference can be read from this attribute.
> +and user can change current preference according to energy or performance needs
> +Please get all support profiles list from
> +``energy_performance_available_preferences`` attribute, all the profiles are
> +integer values defined between 0 to 255 when EPP feature is enabled by platform
> +firmware, if EPP feature is disabled, driver will ignore the written value
> +This attribute is read-write.
> +
> Other performance and frequency values can be read back from
> ``/sys/devices/system/cpu/cpuX/acpi_cppc/``, see :ref:`cppc_sysfs`.
>
^ permalink raw reply [flat|nested] 35+ messages in thread
* RE: [PATCH v3 2/8] Documentation: amd-pstate: add EPP profiles introduction
2022-11-07 18:33 ` Limonciello, Mario
@ 2022-11-13 16:23 ` Yuan, Perry
0 siblings, 0 replies; 35+ messages in thread
From: Yuan, Perry @ 2022-11-13 16:23 UTC (permalink / raw)
To: Limonciello, Mario, rafael.j.wysocki@intel.com, Huang, Ray,
viresh.kumar@linaro.org
Cc: Sharma, Deepak, Fontenot, Nathan, Deucher, Alexander,
Huang, Shimmer, Du, Xiaojian, Meng, Li (Jassmine),
linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org
[AMD Official Use Only - General]
Hi Mario
> -----Original Message-----
> From: Limonciello, Mario <Mario.Limonciello@amd.com>
> Sent: Tuesday, November 8, 2022 2:34 AM
> To: Yuan, Perry <Perry.Yuan@amd.com>; rafael.j.wysocki@intel.com; Huang,
> Ray <Ray.Huang@amd.com>; viresh.kumar@linaro.org
> Cc: Sharma, Deepak <Deepak.Sharma@amd.com>; Fontenot, Nathan
> <Nathan.Fontenot@amd.com>; Deucher, Alexander
> <Alexander.Deucher@amd.com>; Huang, Shimmer
> <Shimmer.Huang@amd.com>; Du, Xiaojian <Xiaojian.Du@amd.com>; Meng,
> Li (Jassmine) <Li.Meng@amd.com>; linux-pm@vger.kernel.org; linux-
> kernel@vger.kernel.org
> Subject: Re: [PATCH v3 2/8] Documentation: amd-pstate: add EPP profiles
> introduction
>
> On 11/7/2022 11:56, Perry Yuan wrote:
> > The patch add AMD pstate EPP feature introduction and what EPP
> > preference supported for AMD processors.
> >
> > User can get supported list from
> > energy_performance_available_preferences attribute file, or update
> > current profile to energy_performance_preference file
> >
> > 1) See all EPP profiles
> > $ sudo cat
> >
> /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_available_pref
> > erences default performance balance_performance balance_power power
> >
> > 2) Check current EPP profile
> > $ sudo cat
> > /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_preference
> > performance
> >
> > 3) Set new EPP profile
> > $ sudo bash -c "echo power >
> /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_preference"
> >
> > Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
> > ---
> > Documentation/admin-guide/pm/amd-pstate.rst | 19
> +++++++++++++++++++
> > 1 file changed, 19 insertions(+)
> >
> > diff --git a/Documentation/admin-guide/pm/amd-pstate.rst
> > b/Documentation/admin-guide/pm/amd-pstate.rst
> > index 8f3d30c5a0d8..78c6525d5a49 100644
> > --- a/Documentation/admin-guide/pm/amd-pstate.rst
> > +++ b/Documentation/admin-guide/pm/amd-pstate.rst
> > @@ -262,6 +262,25 @@ lowest non-linear performance in `AMD CPPC
> Performance Capability
> > <perf_cap_>`_.)
> > This attribute is read-only.
> > > +``energy_performance_available_preferences``
> > +
> > +All the supported EPP preference could be selected, List of the
> > +strings that can be set to the ``energy_performance_preference``
> > +attribute those different profiles represent different energy vs
> > +efficiency hints provided to low-level firmware however, the
> > +``default`` represents the epp value is set by platform firmware This
> > +attribute is read-only.
>
> My proposal at rewording it.
>
> A list of all the supported EPP preferences that could be used for
> ``energy_performance_preference` on this system.
> These profiles represent different hints that are provided to the low-level
> firmware about the user's desired energy vs efficiency tradeoff. ``default``
> represents the epp value is set by platform firmware. This attribute is read-
> only.
Make sense.
Fixed in V4 as you suggested.
>
>
> > +
> > +``energy_performance_preference``
> > +
> > +The current energy performance preference can be read from this
> attribute.
> > +and user can change current preference according to energy or
> > +performance needs Please get all support profiles list from
> > +``energy_performance_available_preferences`` attribute, all the
> > +profiles are integer values defined between 0 to 255 when EPP feature
> > +is enabled by platform firmware, if EPP feature is disabled, driver
> > +will ignore the written value This attribute is read-write.
> > +
> > Other performance and frequency values can be read back from
> > ``/sys/devices/system/cpu/cpuX/acpi_cppc/``, see :ref:`cppc_sysfs`.
> >
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v3 2/8] Documentation: amd-pstate: add EPP profiles introduction
2022-11-07 17:56 ` [PATCH v3 2/8] Documentation: amd-pstate: add EPP profiles introduction Perry Yuan
2022-11-07 18:33 ` Limonciello, Mario
@ 2022-11-10 14:57 ` Rafael J. Wysocki
2022-11-10 15:07 ` Yuan, Perry
1 sibling, 1 reply; 35+ messages in thread
From: Rafael J. Wysocki @ 2022-11-10 14:57 UTC (permalink / raw)
To: Perry Yuan
Cc: rafael.j.wysocki, ray.huang, viresh.kumar, Deepak.Sharma,
Mario.Limonciello, Nathan.Fontenot, Alexander.Deucher,
Shimmer.Huang, Xiaojian.Du, Li.Meng, linux-pm, linux-kernel
On Mon, Nov 7, 2022 at 7:02 PM Perry Yuan <Perry.Yuan@amd.com> wrote:
>
> The patch add AMD pstate EPP feature introduction and what EPP
> preference supported for AMD processors.
>
> User can get supported list from
> energy_performance_available_preferences attribute file, or update
> current profile to energy_performance_preference file
>
> 1) See all EPP profiles
> $ sudo cat /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_available_preferences
> default performance balance_performance balance_power power
>
> 2) Check current EPP profile
> $ sudo cat /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_preference
> performance
>
> 3) Set new EPP profile
> $ sudo bash -c "echo power > /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_preference"
>
> Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
> ---
> Documentation/admin-guide/pm/amd-pstate.rst | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst
> index 8f3d30c5a0d8..78c6525d5a49 100644
> --- a/Documentation/admin-guide/pm/amd-pstate.rst
> +++ b/Documentation/admin-guide/pm/amd-pstate.rst
> @@ -262,6 +262,25 @@ lowest non-linear performance in `AMD CPPC Performance Capability
> <perf_cap_>`_.)
> This attribute is read-only.
>
> +``energy_performance_available_preferences``
> +
> +All the supported EPP preference could be selected, List of the strings that
> +can be set to the ``energy_performance_preference`` attribute
> +those different profiles represent different energy vs efficiency hints provided
> +to low-level firmware
> +however, the ``default`` represents the epp value is set by platform firmware
> +This attribute is read-only.
> +
> +``energy_performance_preference``
> +
> +The current energy performance preference can be read from this attribute.
> +and user can change current preference according to energy or performance needs
> +Please get all support profiles list from
> +``energy_performance_available_preferences`` attribute, all the profiles are
> +integer values defined between 0 to 255 when EPP feature is enabled by platform
> +firmware, if EPP feature is disabled, driver will ignore the written value
> +This attribute is read-write.
> +
> Other performance and frequency values can be read back from
> ``/sys/devices/system/cpu/cpuX/acpi_cppc/``, see :ref:`cppc_sysfs`.
>
> --
So the interface is the same as for intel_pstate AFAICS, which is
good, because it is all consistent.
However, there is some code duplication introduced in the subsequent
patches and that may be a problem from the perspective of maintaining
that consistency in the future.
Have you at least considered introducing a common EPP support header
file that could be used by both intel_pstate and amd_pstate?
^ permalink raw reply [flat|nested] 35+ messages in thread
* RE: [PATCH v3 2/8] Documentation: amd-pstate: add EPP profiles introduction
2022-11-10 14:57 ` Rafael J. Wysocki
@ 2022-11-10 15:07 ` Yuan, Perry
0 siblings, 0 replies; 35+ messages in thread
From: Yuan, Perry @ 2022-11-10 15:07 UTC (permalink / raw)
To: Rafael J. Wysocki
Cc: rafael.j.wysocki@intel.com, Huang, Ray, viresh.kumar@linaro.org,
Sharma, Deepak, Limonciello, Mario, Fontenot, Nathan,
Deucher, Alexander, Huang, Shimmer, Du, Xiaojian,
Meng, Li (Jassmine), linux-pm@vger.kernel.org,
linux-kernel@vger.kernel.org
[AMD Official Use Only - General]
Hi Rafael.
> -----Original Message-----
> From: Rafael J. Wysocki <rafael@kernel.org>
> Sent: Thursday, November 10, 2022 10:58 PM
> To: Yuan, Perry <Perry.Yuan@amd.com>
> Cc: rafael.j.wysocki@intel.com; Huang, Ray <Ray.Huang@amd.com>;
> viresh.kumar@linaro.org; Sharma, Deepak <Deepak.Sharma@amd.com>;
> Limonciello, Mario <Mario.Limonciello@amd.com>; Fontenot, Nathan
> <Nathan.Fontenot@amd.com>; Deucher, Alexander
> <Alexander.Deucher@amd.com>; Huang, Shimmer
> <Shimmer.Huang@amd.com>; Du, Xiaojian <Xiaojian.Du@amd.com>; Meng,
> Li (Jassmine) <Li.Meng@amd.com>; linux-pm@vger.kernel.org; linux-
> kernel@vger.kernel.org
> Subject: Re: [PATCH v3 2/8] Documentation: amd-pstate: add EPP profiles
> introduction
>
> Caution: This message originated from an External Source. Use proper
> caution when opening attachments, clicking links, or responding.
>
>
> On Mon, Nov 7, 2022 at 7:02 PM Perry Yuan <Perry.Yuan@amd.com> wrote:
> >
> > The patch add AMD pstate EPP feature introduction and what EPP
> > preference supported for AMD processors.
> >
> > User can get supported list from
> > energy_performance_available_preferences attribute file, or update
> > current profile to energy_performance_preference file
> >
> > 1) See all EPP profiles
> > $ sudo cat
> >
> /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_available_pr
> ef
> > erences default performance balance_performance balance_power power
> >
> > 2) Check current EPP profile
> > $ sudo cat
> > /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_preference
> > performance
> >
> > 3) Set new EPP profile
> > $ sudo bash -c "echo power >
> /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_preference"
> >
> > Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
> > ---
> > Documentation/admin-guide/pm/amd-pstate.rst | 19
> +++++++++++++++++++
> > 1 file changed, 19 insertions(+)
> >
> > diff --git a/Documentation/admin-guide/pm/amd-pstate.rst
> > b/Documentation/admin-guide/pm/amd-pstate.rst
> > index 8f3d30c5a0d8..78c6525d5a49 100644
> > --- a/Documentation/admin-guide/pm/amd-pstate.rst
> > +++ b/Documentation/admin-guide/pm/amd-pstate.rst
> > @@ -262,6 +262,25 @@ lowest non-linear performance in `AMD CPPC
> > Performance Capability
> > <perf_cap_>`_.)
> > This attribute is read-only.
> >
> > +``energy_performance_available_preferences``
> > +
> > +All the supported EPP preference could be selected, List of the
> > +strings that can be set to the ``energy_performance_preference``
> > +attribute those different profiles represent different energy vs
> > +efficiency hints provided to low-level firmware however, the
> > +``default`` represents the epp value is set by platform firmware This
> > +attribute is read-only.
> > +
> > +``energy_performance_preference``
> > +
> > +The current energy performance preference can be read from this
> attribute.
> > +and user can change current preference according to energy or
> > +performance needs Please get all support profiles list from
> > +``energy_performance_available_preferences`` attribute, all the
> > +profiles are integer values defined between 0 to 255 when EPP feature
> > +is enabled by platform firmware, if EPP feature is disabled, driver
> > +will ignore the written value This attribute is read-write.
> > +
> > Other performance and frequency values can be read back from
> > ``/sys/devices/system/cpu/cpuX/acpi_cppc/``, see :ref:`cppc_sysfs`.
> >
> > --
>
> So the interface is the same as for intel_pstate AFAICS, which is good,
> because it is all consistent.
>
> However, there is some code duplication introduced in the subsequent
> patches and that may be a problem from the perspective of maintaining that
> consistency in the future.
>
> Have you at least considered introducing a common EPP support header file
> that could be used by both intel_pstate and amd_pstate?
I will send the V4 today, that will change the epp value set and get interface
To be compatible with the Gnome power preference setting sysfs call, I use the same profile names.
But V4 patch will there is no raw_epp support as the suggested by Mario.
I will also think about what else can make as common code in the driver scale.
Thanks for your suggestions.
Perry.
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v3 3/8] cpufreq: amd-pstate: change driver to be built-in type
2022-11-07 17:56 [PATCH v3 0/8] Implement AMD Pstate EPP Driver Perry Yuan
2022-11-07 17:56 ` [PATCH v3 1/8] ACPI: CPPC: Add AMD pstate energy performance preference cppc control Perry Yuan
2022-11-07 17:56 ` [PATCH v3 2/8] Documentation: amd-pstate: add EPP profiles introduction Perry Yuan
@ 2022-11-07 17:57 ` Perry Yuan
2022-11-07 18:29 ` Limonciello, Mario
2022-11-07 17:57 ` [PATCH v3 4/8] cpufreq: amd_pstate: add AMD Pstate EPP support for the MSR based processors Perry Yuan
` (4 subsequent siblings)
7 siblings, 1 reply; 35+ messages in thread
From: Perry Yuan @ 2022-11-07 17:57 UTC (permalink / raw)
To: rafael.j.wysocki, ray.huang, viresh.kumar
Cc: Deepak.Sharma, Mario.Limonciello, Nathan.Fontenot,
Alexander.Deucher, Shimmer.Huang, Xiaojian.Du, Li.Meng, linux-pm,
linux-kernel, Perry Yuan
Change the `amd-pstate` driver as the built-in type which can help to
load the driver before the acpi_cpufreq driver as the default pstate
driver for the AMD processors.
for the processors do not have the dedicated MSR functions, add
`amd-pstate=legacy_cppc` to grub which enable shared memmory interface
to communicate with cppc_acpi module to control pstate hints.
Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
---
drivers/cpufreq/amd-pstate.c | 23 +++++++++++++----------
1 file changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
index ace7d50cf2ac..14906431dc15 100644
--- a/drivers/cpufreq/amd-pstate.c
+++ b/drivers/cpufreq/amd-pstate.c
@@ -59,10 +59,7 @@
* we disable it by default to go acpi-cpufreq on these processors and add a
* module parameter to be able to enable it manually for debugging.
*/
-static bool shared_mem = false;
-module_param(shared_mem, bool, 0444);
-MODULE_PARM_DESC(shared_mem,
- "enable amd-pstate on processors with shared memory solution (false = disabled (default), true = enabled)");
+static bool shared_mem __read_mostly;
static struct cpufreq_driver amd_pstate_driver;
@@ -653,16 +650,22 @@ static int __init amd_pstate_init(void)
return ret;
}
+device_initcall(amd_pstate_init);
-static void __exit amd_pstate_exit(void)
+static int __init amd_pstate_param(char *str)
{
- cpufreq_unregister_driver(&amd_pstate_driver);
+ if (!str)
+ return -EINVAL;
- amd_pstate_enable(false);
-}
+ /* enable shared memory type CPPC ,if you processor has no MSR, you have to add this
+ * to your grub to make cppc driver loaded successfully.
+ */
+ if (!strcmp(str, "legacy_cppc"))
+ shared_mem = true;
-module_init(amd_pstate_init);
-module_exit(amd_pstate_exit);
+ return 0;
+}
+early_param("amd-pstate", amd_pstate_param);
MODULE_AUTHOR("Huang Rui <ray.huang@amd.com>");
MODULE_DESCRIPTION("AMD Processor P-state Frequency Driver");
--
2.34.1
^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [PATCH v3 3/8] cpufreq: amd-pstate: change driver to be built-in type
2022-11-07 17:57 ` [PATCH v3 3/8] cpufreq: amd-pstate: change driver to be built-in type Perry Yuan
@ 2022-11-07 18:29 ` Limonciello, Mario
2022-11-13 16:21 ` Yuan, Perry
0 siblings, 1 reply; 35+ messages in thread
From: Limonciello, Mario @ 2022-11-07 18:29 UTC (permalink / raw)
To: Perry Yuan, rafael.j.wysocki, ray.huang, viresh.kumar, wyes.karny
Cc: Deepak.Sharma, Nathan.Fontenot, Alexander.Deucher, Shimmer.Huang,
Xiaojian.Du, Li.Meng, linux-pm, linux-kernel
+ wyes.karny@amd.com
You should sync with Wyes Karny on this patch, I think he had some
different ideas that you guys should fold together for v4 of this
series. I'll leave some direct comments on your implementation below.
Also, include him in on CC for your v4.
On 11/7/2022 11:57, Perry Yuan wrote:
> Change the `amd-pstate` driver as the built-in type which can help to
> load the driver before the acpi_cpufreq driver as the default pstate
> driver for the AMD processors.
>
> for the processors do not have the dedicated MSR functions, add
> `amd-pstate=legacy_cppc` to grub which enable shared memmory interface
> to communicate with cppc_acpi module to control pstate hints.
1) s/memmory/memory/
2) Although many users will use GRUB to configure their kernel command
line you should not assume it in the commit message.
>
> Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
> ---
> drivers/cpufreq/amd-pstate.c | 23 +++++++++++++----------
> 1 file changed, 13 insertions(+), 10 deletions(-)
You need to document the new early parameter support in
kernel-parameters.txt, and should also put it in amd-pstate.rst.
>
> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
> index ace7d50cf2ac..14906431dc15 100644
> --- a/drivers/cpufreq/amd-pstate.c
> +++ b/drivers/cpufreq/amd-pstate.c
> @@ -59,10 +59,7 @@
> * we disable it by default to go acpi-cpufreq on these processors and add a
> * module parameter to be able to enable it manually for debugging.
> */
> -static bool shared_mem = false;
> -module_param(shared_mem, bool, 0444);
> -MODULE_PARM_DESC(shared_mem,
> - "enable amd-pstate on processors with shared memory solution (false = disabled (default), true = enabled)");
> +static bool shared_mem __read_mostly;
>
> static struct cpufreq_driver amd_pstate_driver;
>
> @@ -653,16 +650,22 @@ static int __init amd_pstate_init(void)
>
> return ret;
> }
> +device_initcall(amd_pstate_init);
>
> -static void __exit amd_pstate_exit(void)
> +static int __init amd_pstate_param(char *str)
> {
> - cpufreq_unregister_driver(&amd_pstate_driver);
> + if (!str)
> + return -EINVAL;
>
> - amd_pstate_enable(false);
> -}
> + /* enable shared memory type CPPC ,if you processor has no MSR, you have to add this
> + * to your grub to make cppc driver loaded successfully.
Don't reference GRUB here, it should be referenced from the kernel
command line.
> + */
> + if (!strcmp(str, "legacy_cppc"))
> + shared_mem = true;
Sync with Wyes about this. He had some different strings and flow in
mind which I think would be more preferable.
>
> -module_init(amd_pstate_init);
> -module_exit(amd_pstate_exit);
> + return 0;
> +}
> +early_param("amd-pstate", amd_pstate_param);
>
> MODULE_AUTHOR("Huang Rui <ray.huang@amd.com>");
> MODULE_DESCRIPTION("AMD Processor P-state Frequency Driver");
^ permalink raw reply [flat|nested] 35+ messages in thread* RE: [PATCH v3 3/8] cpufreq: amd-pstate: change driver to be built-in type
2022-11-07 18:29 ` Limonciello, Mario
@ 2022-11-13 16:21 ` Yuan, Perry
0 siblings, 0 replies; 35+ messages in thread
From: Yuan, Perry @ 2022-11-13 16:21 UTC (permalink / raw)
To: Limonciello, Mario, rafael.j.wysocki@intel.com, Huang, Ray,
viresh.kumar@linaro.org, Karny, Wyes
Cc: Sharma, Deepak, Fontenot, Nathan, Deucher, Alexander,
Huang, Shimmer, Du, Xiaojian, Meng, Li (Jassmine),
linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org
[AMD Official Use Only - General]
> -----Original Message-----
> From: Limonciello, Mario <Mario.Limonciello@amd.com>
> Sent: Tuesday, November 8, 2022 2:30 AM
> To: Yuan, Perry <Perry.Yuan@amd.com>; rafael.j.wysocki@intel.com; Huang,
> Ray <Ray.Huang@amd.com>; viresh.kumar@linaro.org; Karny, Wyes
> <Wyes.Karny@amd.com>
> Cc: Sharma, Deepak <Deepak.Sharma@amd.com>; Fontenot, Nathan
> <Nathan.Fontenot@amd.com>; Deucher, Alexander
> <Alexander.Deucher@amd.com>; Huang, Shimmer
> <Shimmer.Huang@amd.com>; Du, Xiaojian <Xiaojian.Du@amd.com>; Meng,
> Li (Jassmine) <Li.Meng@amd.com>; linux-pm@vger.kernel.org; linux-
> kernel@vger.kernel.org
> Subject: Re: [PATCH v3 3/8] cpufreq: amd-pstate: change driver to be built-in
> type
>
> + wyes.karny@amd.com
>
> You should sync with Wyes Karny on this patch, I think he had some different
> ideas that you guys should fold together for v4 of this series. I'll leave some
> direct comments on your implementation below.
>
> Also, include him in on CC for your v4.
>
> On 11/7/2022 11:57, Perry Yuan wrote:
> > Change the `amd-pstate` driver as the built-in type which can help to
> > load the driver before the acpi_cpufreq driver as the default pstate
> > driver for the AMD processors.
> >
> > for the processors do not have the dedicated MSR functions, add
> > `amd-pstate=legacy_cppc` to grub which enable shared memmory interface
> > to communicate with cppc_acpi module to control pstate hints.
>
> 1) s/memmory/memory/
> 2) Although many users will use GRUB to configure their kernel command
> line you should not assume it in the commit message.
Fixed in V4.
>
> >
> > Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
> > ---
> > drivers/cpufreq/amd-pstate.c | 23 +++++++++++++----------
> > 1 file changed, 13 insertions(+), 10 deletions(-)
>
> You need to document the new early parameter support in kernel-
> parameters.txt, and should also put it in amd-pstate.rst.
>
> >
> > diff --git a/drivers/cpufreq/amd-pstate.c
> > b/drivers/cpufreq/amd-pstate.c index ace7d50cf2ac..14906431dc15
> 100644
> > --- a/drivers/cpufreq/amd-pstate.c
> > +++ b/drivers/cpufreq/amd-pstate.c
> > @@ -59,10 +59,7 @@
> > * we disable it by default to go acpi-cpufreq on these processors and add
> a
> > * module parameter to be able to enable it manually for debugging.
> > */
> > -static bool shared_mem = false;
> > -module_param(shared_mem, bool, 0444); -
> MODULE_PARM_DESC(shared_mem,
> > - "enable amd-pstate on processors with shared memory
> solution (false = disabled (default), true = enabled)");
> > +static bool shared_mem __read_mostly;
> >
> > static struct cpufreq_driver amd_pstate_driver;
> >
> > @@ -653,16 +650,22 @@ static int __init amd_pstate_init(void)
> >
> > return ret;
> > }
> > +device_initcall(amd_pstate_init);
> >
> > -static void __exit amd_pstate_exit(void)
> > +static int __init amd_pstate_param(char *str)
> > {
> > - cpufreq_unregister_driver(&amd_pstate_driver);
> > + if (!str)
> > + return -EINVAL;
> >
> > - amd_pstate_enable(false);
> > -}
> > + /* enable shared memory type CPPC ,if you processor has no MSR,
> you have to add this
> > + * to your grub to make cppc driver loaded successfully.
>
> Don't reference GRUB here, it should be referenced from the kernel
> command line.
>
> > + */
> > + if (!strcmp(str, "legacy_cppc"))
> > + shared_mem = true;
> Sync with Wyes about this. He had some different strings and flow in mind
> which I think would be more preferable.
Aligned with Wyes,
Some new changes brought into V4.
Please help to take a look at the new patch.
Thanks
Perry.
>
> >
> > -module_init(amd_pstate_init);
> > -module_exit(amd_pstate_exit);
> > + return 0;
> > +}
> > +early_param("amd-pstate", amd_pstate_param);
> >
> > MODULE_AUTHOR("Huang Rui <ray.huang@amd.com>");
> > MODULE_DESCRIPTION("AMD Processor P-state Frequency Driver");
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v3 4/8] cpufreq: amd_pstate: add AMD Pstate EPP support for the MSR based processors
2022-11-07 17:56 [PATCH v3 0/8] Implement AMD Pstate EPP Driver Perry Yuan
` (2 preceding siblings ...)
2022-11-07 17:57 ` [PATCH v3 3/8] cpufreq: amd-pstate: change driver to be built-in type Perry Yuan
@ 2022-11-07 17:57 ` Perry Yuan
2022-11-07 20:32 ` Limonciello, Mario
2022-11-07 17:57 ` [PATCH v3 5/8] cpufreq: amd_pstate: implement amd pstate cpu online and offline callback Perry Yuan
` (3 subsequent siblings)
7 siblings, 1 reply; 35+ messages in thread
From: Perry Yuan @ 2022-11-07 17:57 UTC (permalink / raw)
To: rafael.j.wysocki, ray.huang, viresh.kumar
Cc: Deepak.Sharma, Mario.Limonciello, Nathan.Fontenot,
Alexander.Deucher, Shimmer.Huang, Xiaojian.Du, Li.Meng, linux-pm,
linux-kernel, Perry Yuan
Add EPP driver support for those AMD CPUs which has full MSR feature
enabled, The EPP is used in the DPM controller to drive the frequency
that a core is going to operate during short periods of activity.
EPP values will be utilized for different OS profiles (balanced, performance,
power savings). cppc performance can be controlled by the user space interface
sys attributes for min and max frequency limits, when pstate driver is
working under power save policy.
EPP scale is 0 - 255, 0 is the max performance and 255 is min level.
balance_performance (0x80) can provide best balance performance and watt for
most of system, meanwhile user can choose performance policy on needs.
$ cat /sys/devices/system/cpu/cpufreq/policy0/energy_performance_available_preferences
default performance balance_performance balance_power power
$ cat /sys/devices/system/cpu/cpufreq/policy0/energy_performance_preference
balance_performance
Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
---
drivers/cpufreq/amd-pstate.c | 658 ++++++++++++++++++++++++++++++++++-
include/linux/amd-pstate.h | 81 +++++
2 files changed, 734 insertions(+), 5 deletions(-)
diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
index 14906431dc15..eb82bc6a7f66 100644
--- a/drivers/cpufreq/amd-pstate.c
+++ b/drivers/cpufreq/amd-pstate.c
@@ -60,8 +60,136 @@
* module parameter to be able to enable it manually for debugging.
*/
static bool shared_mem __read_mostly;
+static int cppc_active __read_mostly;
+static int disable_pstate_load __initdata;
+static int epp_off __initdata;
-static struct cpufreq_driver amd_pstate_driver;
+static struct cpufreq_driver *default_pstate_driver;
+static struct amd_cpudata **all_cpu_data;
+
+static struct amd_pstate_params global_params;
+
+static DEFINE_MUTEX(amd_pstate_limits_lock);
+static DEFINE_MUTEX(amd_pstate_driver_lock);
+
+static bool cppc_boost __read_mostly;
+struct kobject *amd_pstate_kobj;
+
+#ifdef CONFIG_ACPI_CPPC_LIB
+static s16 amd_pstate_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached)
+{
+ s16 epp;
+ struct cppc_perf_caps perf_caps;
+ int ret;
+
+ if (boot_cpu_has(X86_FEATURE_CPPC)) {
+ if (!cppc_req_cached) {
+ epp = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ,
+ &cppc_req_cached);
+ if (epp)
+ return epp;
+ }
+ epp = (cppc_req_cached >> 24) & 0xFF;
+ } else {
+ ret = cppc_get_epp_caps(cpudata->cpu, &perf_caps);
+ if (ret < 0) {
+ pr_debug("Could not retrieve energy perf value (%d)\n", ret);
+ return -EIO;
+ }
+ epp = (s16) perf_caps.energy_perf;
+ }
+
+ return epp;
+}
+#endif
+
+static int amd_pstate_get_energy_pref_index(struct amd_cpudata *cpudata, int *raw_epp)
+{
+ s16 epp;
+ int index = -EINVAL;
+
+ *raw_epp = 0;
+ epp = amd_pstate_get_epp(cpudata, 0);
+ if (epp < 0)
+ return epp;
+
+ switch (epp) {
+ case AMD_CPPC_EPP_PERFORMANCE:
+ index = EPP_INDEX_PERFORMANCE;
+ break;
+ case AMD_CPPC_EPP_BALANCE_PERFORMANCE:
+ index = EPP_INDEX_BALANCE_PERFORMANCE;
+ break;
+ case AMD_CPPC_EPP_BALANCE_POWERSAVE:
+ index = EPP_INDEX_BALANCE_POWERSAVE;
+ break;
+ case AMD_CPPC_EPP_POWERSAVE:
+ index = EPP_INDEX_POWERSAVE;
+ break;
+ default:
+ *raw_epp = epp;
+ index = 0;
+ }
+
+ return index;
+}
+
+#ifdef CONFIG_ACPI_CPPC_LIB
+static int amd_pstate_set_epp(struct amd_cpudata *cpudata, u32 epp)
+{
+ int ret;
+ struct cppc_perf_ctrls perf_ctrls;
+
+ if (boot_cpu_has(X86_FEATURE_CPPC)) {
+ u64 value = READ_ONCE(cpudata->cppc_req_cached);
+
+ value &= ~GENMASK_ULL(31, 24);
+ value |= (u64)epp << 24;
+ WRITE_ONCE(cpudata->cppc_req_cached, value);
+
+ ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
+ if (!ret)
+ cpudata->epp_cached = epp;
+ } else {
+ perf_ctrls.energy_perf = epp;
+ ret = cppc_set_epp_perf(cpudata->cpu, &perf_ctrls);
+ if (ret) {
+ pr_debug("failed to set energy perf value (%d)\n", ret);
+ return ret;
+ }
+ cpudata->epp_cached = epp;
+ }
+
+ return ret;
+}
+
+static int amd_pstate_set_energy_pref_index(struct amd_cpudata *cpudata,
+ int pref_index, bool use_raw,
+ u32 raw_epp)
+{
+ int epp = -EINVAL;
+ int ret;
+
+ if (!pref_index) {
+ pr_debug("EPP pref_index is invalid\n");
+ return -EINVAL;
+ }
+
+ if (use_raw)
+ epp = raw_epp;
+ else if (epp == -EINVAL)
+ epp = epp_values[pref_index];
+
+ if (epp > 0 && cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) {
+ pr_debug("EPP cannot be set under performance policy\n");
+ return -EBUSY;
+ }
+
+ ret = amd_pstate_set_epp(cpudata, epp);
+
+ return ret;
+}
+#endif
static inline int pstate_enable(bool enable)
{
@@ -71,11 +199,25 @@ static inline int pstate_enable(bool enable)
static int cppc_enable(bool enable)
{
int cpu, ret = 0;
+ struct cppc_perf_ctrls perf_ctrls;
for_each_present_cpu(cpu) {
ret = cppc_set_enable(cpu, enable);
if (ret)
return ret;
+
+ /* Enable autonomous mode for EPP */
+ if (!cppc_active) {
+ ret = cppc_set_auto_epp(cpu, enable);
+ if (ret)
+ return ret;
+
+ /* Set desired perf as zero to allow EPP firmware control */
+ perf_ctrls.desired_perf = 0;
+ ret = cppc_set_perf(cpu, &perf_ctrls);
+ if (ret)
+ return ret;
+ }
}
return ret;
@@ -418,7 +560,7 @@ static void amd_pstate_boost_init(struct amd_cpudata *cpudata)
return;
cpudata->boost_supported = true;
- amd_pstate_driver.boost_enabled = true;
+ default_pstate_driver->boost_enabled = true;
}
static int amd_pstate_cpu_init(struct cpufreq_policy *policy)
@@ -582,10 +724,74 @@ static ssize_t show_amd_pstate_highest_perf(struct cpufreq_policy *policy,
return sprintf(&buf[0], "%u\n", perf);
}
+static ssize_t show_energy_performance_available_preferences(
+ struct cpufreq_policy *policy, char *buf)
+{
+ int i = 0;
+ int ret = 0;
+
+ while (energy_perf_strings[i] != NULL)
+ ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
+
+ ret += sprintf(&buf[ret], "\n");
+
+ return ret;
+}
+
+static ssize_t store_energy_performance_preference(
+ struct cpufreq_policy *policy, const char *buf, size_t count)
+{
+ struct amd_cpudata *cpudata = policy->driver_data;
+ char str_preference[21];
+ bool raw = false;
+ ssize_t ret;
+ u32 epp = 0;
+
+ ret = sscanf(buf, "%20s", str_preference);
+ if (ret != 1)
+ return -EINVAL;
+
+ ret = match_string(energy_perf_strings, -1, str_preference);
+ if (ret < 0) {
+ ret = kstrtouint(buf, 10, &epp);
+ if (ret)
+ return ret;
+
+ if ((epp > 255) || (epp < 0))
+ return -EINVAL;
+
+ raw = true;
+ }
+
+ mutex_lock(&amd_pstate_limits_lock);
+ ret = amd_pstate_set_energy_pref_index(cpudata, ret, raw, epp);
+ mutex_unlock(&amd_pstate_limits_lock);
+
+ return ret ?: count;
+}
+
+static ssize_t show_energy_performance_preference(
+ struct cpufreq_policy *policy, char *buf)
+{
+ struct amd_cpudata *cpudata = policy->driver_data;
+ int preference, raw_epp;
+
+ preference = amd_pstate_get_energy_pref_index(cpudata, &raw_epp);
+ if (preference < 0)
+ return preference;
+
+ if (raw_epp)
+ return sprintf(buf, "%d\n", raw_epp);
+ else
+ return sprintf(buf, "%s\n", energy_perf_strings[preference]);
+}
+
cpufreq_freq_attr_ro(amd_pstate_max_freq);
cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq);
cpufreq_freq_attr_ro(amd_pstate_highest_perf);
+cpufreq_freq_attr_rw(energy_performance_preference);
+cpufreq_freq_attr_ro(energy_performance_available_preferences);
static struct freq_attr *amd_pstate_attr[] = {
&amd_pstate_max_freq,
@@ -594,6 +800,415 @@ static struct freq_attr *amd_pstate_attr[] = {
NULL,
};
+static struct freq_attr *amd_pstate_epp_attr[] = {
+ &amd_pstate_max_freq,
+ &amd_pstate_lowest_nonlinear_freq,
+ &amd_pstate_highest_perf,
+ &energy_performance_preference,
+ &energy_performance_available_preferences,
+ NULL,
+};
+
+static inline void update_boost_state(void)
+{
+ u64 misc_en;
+ struct amd_cpudata *cpudata;
+
+ cpudata = all_cpu_data[0];
+ rdmsrl(MSR_K7_HWCR, misc_en);
+ global_params.cppc_boost_disabled = misc_en & BIT_ULL(25);
+}
+
+static int amd_pstate_init_cpu(unsigned int cpunum)
+{
+ struct amd_cpudata *cpudata;
+
+ cpudata = all_cpu_data[cpunum];
+ if (!cpudata) {
+ cpudata = kzalloc(sizeof(*cpudata), GFP_KERNEL);
+ if (!cpudata)
+ return -ENOMEM;
+ WRITE_ONCE(all_cpu_data[cpunum], cpudata);
+
+ cpudata->cpu = cpunum;
+ }
+ cpudata->epp_powersave = -EINVAL;
+ cpudata->epp_policy = 0;
+ pr_debug("controlling: cpu %d\n", cpunum);
+ return 0;
+}
+
+static int __amd_pstate_cpu_init(struct cpufreq_policy *policy)
+{
+ int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret;
+ struct amd_cpudata *cpudata;
+ struct device *dev;
+ int rc;
+ u64 value;
+
+ rc = amd_pstate_init_cpu(policy->cpu);
+ if (rc)
+ return rc;
+
+ cpudata = all_cpu_data[policy->cpu];
+
+ dev = get_cpu_device(policy->cpu);
+ if (!dev)
+ goto free_cpudata1;
+
+ rc = amd_pstate_init_perf(cpudata);
+ if (rc)
+ goto free_cpudata1;
+
+ min_freq = amd_get_min_freq(cpudata);
+ max_freq = amd_get_max_freq(cpudata);
+ nominal_freq = amd_get_nominal_freq(cpudata);
+ lowest_nonlinear_freq = amd_get_lowest_nonlinear_freq(cpudata);
+ if (min_freq < 0 || max_freq < 0 || min_freq > max_freq) {
+ dev_err(dev, "min_freq(%d) or max_freq(%d) value is incorrect\n",
+ min_freq, max_freq);
+ ret = -EINVAL;
+ goto free_cpudata1;
+ }
+
+ policy->min = min_freq;
+ policy->max = max_freq;
+
+ policy->cpuinfo.min_freq = min_freq;
+ policy->cpuinfo.max_freq = max_freq;
+ /* It will be updated by governor */
+ policy->cur = policy->cpuinfo.min_freq;
+
+ /* Initial processor data capability frequencies */
+ cpudata->max_freq = max_freq;
+ cpudata->min_freq = min_freq;
+ cpudata->nominal_freq = nominal_freq;
+ cpudata->lowest_nonlinear_freq = lowest_nonlinear_freq;
+
+ policy->driver_data = cpudata;
+
+ update_boost_state();
+ cpudata->epp_cached = amd_pstate_get_epp(cpudata, value);
+
+ policy->min = policy->cpuinfo.min_freq;
+ policy->max = policy->cpuinfo.max_freq;
+
+ if (boot_cpu_has(X86_FEATURE_CPPC))
+ policy->fast_switch_possible = true;
+
+ if (!shared_mem && boot_cpu_has(X86_FEATURE_CPPC)) {
+ ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value);
+ if (ret)
+ return ret;
+ WRITE_ONCE(cpudata->cppc_req_cached, value);
+
+ ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, &value);
+ if (ret)
+ return ret;
+ WRITE_ONCE(cpudata->cppc_cap1_cached, value);
+ }
+ amd_pstate_boost_init(cpudata);
+
+ return 0;
+
+free_cpudata1:
+ kfree(cpudata);
+ return ret;
+}
+
+static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy)
+{
+ int ret;
+
+ ret = __amd_pstate_cpu_init(policy);
+ if (ret)
+ return ret;
+ /*
+ * Set the policy to powersave to provide a valid fallback value in case
+ * the default cpufreq governor is neither powersave nor performance.
+ */
+ policy->policy = CPUFREQ_POLICY_POWERSAVE;
+
+ return 0;
+}
+
+static int amd_pstate_epp_cpu_exit(struct cpufreq_policy *policy)
+{
+ pr_debug("amd-pstate: CPU %d exiting\n", policy->cpu);
+ policy->fast_switch_possible = false;
+ return 0;
+}
+
+static void amd_pstate_update_max_freq(unsigned int cpu)
+{
+ struct cpufreq_policy *policy = policy = cpufreq_cpu_get(cpu);
+
+ if (!policy)
+ return;
+
+ refresh_frequency_limits(policy);
+ cpufreq_cpu_put(policy);
+}
+
+static void amd_pstate_epp_update_limits(unsigned int cpu)
+{
+ mutex_lock(&amd_pstate_driver_lock);
+ update_boost_state();
+ if (global_params.cppc_boost_disabled) {
+ for_each_possible_cpu(cpu)
+ amd_pstate_update_max_freq(cpu);
+ } else {
+ cpufreq_update_policy(cpu);
+ }
+ mutex_unlock(&amd_pstate_driver_lock);
+}
+
+static int cppc_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
+
+static inline void amd_pstate_boost_up(struct amd_cpudata *cpudata)
+{
+ u64 hwp_req = READ_ONCE(cpudata->cppc_req_cached);
+ u64 hwp_cap = READ_ONCE(cpudata->cppc_cap1_cached);
+ u32 max_limit = (hwp_req & 0xff);
+ u32 min_limit = (hwp_req & 0xff00) >> 8;
+ u32 boost_level1;
+
+ /* If max and min are equal or already at max, nothing to boost */
+ if (max_limit == min_limit)
+ return;
+
+ /* Set boost max and min to initial value */
+ if (!cpudata->cppc_boost_min)
+ cpudata->cppc_boost_min = min_limit;
+
+ boost_level1 = ((AMD_CPPC_NOMINAL_PERF(hwp_cap) + min_limit) >> 1);
+
+ if (cpudata->cppc_boost_min < boost_level1)
+ cpudata->cppc_boost_min = boost_level1;
+ else if (cpudata->cppc_boost_min < AMD_CPPC_NOMINAL_PERF(hwp_cap))
+ cpudata->cppc_boost_min = AMD_CPPC_NOMINAL_PERF(hwp_cap);
+ else if (cpudata->cppc_boost_min == AMD_CPPC_NOMINAL_PERF(hwp_cap))
+ cpudata->cppc_boost_min = max_limit;
+ else
+ return;
+
+ hwp_req &= ~AMD_CPPC_MIN_PERF(~0L);
+ hwp_req |= AMD_CPPC_MIN_PERF(cpudata->cppc_boost_min);
+ wrmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, hwp_req);
+ cpudata->last_update = cpudata->sample.time;
+}
+
+static inline void amd_pstate_boost_down(struct amd_cpudata *cpudata)
+{
+ bool expired;
+
+ if (cpudata->cppc_boost_min) {
+ expired = time_after64(cpudata->sample.time, cpudata->last_update +
+ cppc_boost_hold_time_ns);
+
+ if (expired) {
+ wrmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ,
+ cpudata->cppc_req_cached);
+ cpudata->cppc_boost_min = 0;
+ }
+ }
+
+ cpudata->last_update = cpudata->sample.time;
+}
+
+static inline void amd_pstate_boost_update_util(struct amd_cpudata *cpudata,
+ u64 time)
+{
+ cpudata->sample.time = time;
+ if (smp_processor_id() != cpudata->cpu)
+ return;
+
+ if (cpudata->sched_flags & SCHED_CPUFREQ_IOWAIT) {
+ bool do_io = false;
+
+ cpudata->sched_flags = 0;
+ /*
+ * Set iowait_boost flag and update time. Since IO WAIT flag
+ * is set all the time, we can't just conclude that there is
+ * some IO bound activity is scheduled on this CPU with just
+ * one occurrence. If we receive at least two in two
+ * consecutive ticks, then we treat as boost candidate.
+ * This is leveraged from Intel Pstate driver.
+ */
+ if (time_before64(time, cpudata->last_io_update + 2 * TICK_NSEC))
+ do_io = true;
+
+ cpudata->last_io_update = time;
+
+ if (do_io)
+ amd_pstate_boost_up(cpudata);
+
+ } else {
+ amd_pstate_boost_down(cpudata);
+ }
+}
+
+static inline void amd_pstate_cppc_update_hook(struct update_util_data *data,
+ u64 time, unsigned int flags)
+{
+ struct amd_cpudata *cpudata = container_of(data,
+ struct amd_cpudata, update_util);
+
+ cpudata->sched_flags |= flags;
+
+ if (smp_processor_id() == cpudata->cpu)
+ amd_pstate_boost_update_util(cpudata, time);
+}
+
+static void amd_pstate_clear_update_util_hook(unsigned int cpu)
+{
+ struct amd_cpudata *cpudata = all_cpu_data[cpu];
+
+ if (!cpudata->update_util_set)
+ return;
+
+ cpufreq_remove_update_util_hook(cpu);
+ cpudata->update_util_set = false;
+ synchronize_rcu();
+}
+
+static void amd_pstate_set_update_util_hook(unsigned int cpu_num)
+{
+ struct amd_cpudata *cpudata = all_cpu_data[cpu_num];
+
+ if (!cppc_boost) {
+ if (cpudata->update_util_set)
+ amd_pstate_clear_update_util_hook(cpudata->cpu);
+ return;
+ }
+
+ if (cpudata->update_util_set)
+ return;
+
+ cpudata->sample.time = 0;
+ cpufreq_add_update_util_hook(cpu_num, &cpudata->update_util,
+ amd_pstate_cppc_update_hook);
+ cpudata->update_util_set = true;
+}
+
+static void amd_pstate_epp_init(unsigned int cpu)
+{
+ struct amd_cpudata *cpudata = all_cpu_data[cpu];
+ u32 max_perf, min_perf;
+ u64 value;
+ s16 epp;
+ int ret;
+
+ max_perf = READ_ONCE(cpudata->highest_perf);
+ min_perf = READ_ONCE(cpudata->lowest_perf);
+
+ value = READ_ONCE(cpudata->cppc_req_cached);
+
+ if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE)
+ min_perf = max_perf;
+
+ /* Initial min/max values for CPPC Performance Controls Register */
+ value &= ~AMD_CPPC_MIN_PERF(~0L);
+ value |= AMD_CPPC_MIN_PERF(min_perf);
+
+ value &= ~AMD_CPPC_MAX_PERF(~0L);
+ value |= AMD_CPPC_MAX_PERF(max_perf);
+
+ /* CPPC EPP feature require to set zero to the desire perf bit */
+ value &= ~AMD_CPPC_DES_PERF(~0L);
+ value |= AMD_CPPC_DES_PERF(0);
+
+ if (cpudata->epp_policy == cpudata->policy)
+ goto skip_epp;
+
+ cpudata->epp_policy = cpudata->policy;
+
+ if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) {
+ epp = amd_pstate_get_epp(cpudata, value);
+ cpudata->epp_powersave = epp;
+ if (epp < 0)
+ goto skip_epp;
+ /* force the epp value to be zero for performance policy */
+ epp = 0;
+ } else {
+ if (cpudata->epp_powersave < 0)
+ goto skip_epp;
+ /* Get BIOS pre-defined epp value */
+ epp = amd_pstate_get_epp(cpudata, value);
+ if (epp)
+ goto skip_epp;
+ epp = cpudata->epp_powersave;
+ }
+ /* Set initial EPP value */
+ if (boot_cpu_has(X86_FEATURE_CPPC)) {
+ value &= ~GENMASK_ULL(31, 24);
+ value |= (u64)epp << 24;
+ }
+
+skip_epp:
+ WRITE_ONCE(cpudata->cppc_req_cached, value);
+ ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
+ if (!ret)
+ cpudata->epp_cached = epp;
+}
+
+static void amd_pstate_set_max_limits(struct amd_cpudata *cpudata)
+{
+ u64 hwp_cap = READ_ONCE(cpudata->cppc_cap1_cached);
+ u64 hwp_req = READ_ONCE(cpudata->cppc_req_cached);
+ u32 max_limit = (hwp_cap >> 24) & 0xff;
+
+ hwp_req &= ~AMD_CPPC_MIN_PERF(~0L);
+ hwp_req |= AMD_CPPC_MIN_PERF(max_limit);
+ wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, hwp_req);
+}
+
+static int amd_pstate_epp_set_policy(struct cpufreq_policy *policy)
+{
+ struct amd_cpudata *cpudata;
+
+ if (!policy->cpuinfo.max_freq)
+ return -ENODEV;
+
+ pr_debug("set_policy: cpuinfo.max %u policy->max %u\n",
+ policy->cpuinfo.max_freq, policy->max);
+
+ cpudata = all_cpu_data[policy->cpu];
+ cpudata->policy = policy->policy;
+
+ if (boot_cpu_has(X86_FEATURE_CPPC)) {
+ mutex_lock(&amd_pstate_limits_lock);
+
+ if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) {
+ amd_pstate_clear_update_util_hook(policy->cpu);
+ amd_pstate_set_max_limits(cpudata);
+ } else {
+ amd_pstate_set_update_util_hook(policy->cpu);
+ }
+
+ if (boot_cpu_has(X86_FEATURE_CPPC))
+ amd_pstate_epp_init(policy->cpu);
+
+ mutex_unlock(&amd_pstate_limits_lock);
+ }
+
+ return 0;
+}
+
+static void amd_pstate_verify_cpu_policy(struct amd_cpudata *cpudata,
+ struct cpufreq_policy_data *policy)
+{
+ update_boost_state();
+ cpufreq_verify_within_cpu_limits(policy);
+}
+
+static int amd_pstate_epp_verify_policy(struct cpufreq_policy_data *policy)
+{
+ amd_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy);
+ pr_debug("policy_max =%d, policy_min=%d\n", policy->max, policy->min);
+ return 0;
+}
+
static struct cpufreq_driver amd_pstate_driver = {
.flags = CPUFREQ_CONST_LOOPS | CPUFREQ_NEED_UPDATE_LIMITS,
.verify = amd_pstate_verify,
@@ -607,8 +1222,20 @@ static struct cpufreq_driver amd_pstate_driver = {
.attr = amd_pstate_attr,
};
+static struct cpufreq_driver amd_pstate_epp_driver = {
+ .flags = CPUFREQ_CONST_LOOPS,
+ .verify = amd_pstate_epp_verify_policy,
+ .setpolicy = amd_pstate_epp_set_policy,
+ .init = amd_pstate_epp_cpu_init,
+ .exit = amd_pstate_epp_cpu_exit,
+ .update_limits = amd_pstate_epp_update_limits,
+ .name = "amd_pstate_epp",
+ .attr = amd_pstate_epp_attr,
+};
+
static int __init amd_pstate_init(void)
{
+ static struct amd_cpudata **cpudata;
int ret;
if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
@@ -623,10 +1250,18 @@ static int __init amd_pstate_init(void)
if (cpufreq_get_current_driver())
return -EEXIST;
+ if (!epp_off) {
+ WRITE_ONCE(cppc_active, 1);
+ if (!default_pstate_driver)
+ default_pstate_driver = &amd_pstate_epp_driver;
+ }
+ pr_info("AMD CPPC loading with %s driver instance.\n", default_pstate_driver->name);
+
/* capability check */
if (boot_cpu_has(X86_FEATURE_CPPC)) {
+ if (!cppc_active)
+ default_pstate_driver->adjust_perf = amd_pstate_adjust_perf;
pr_debug("AMD CPPC MSR based functionality is supported\n");
- amd_pstate_driver.adjust_perf = amd_pstate_adjust_perf;
} else if (shared_mem) {
static_call_update(amd_pstate_enable, cppc_enable);
static_call_update(amd_pstate_init_perf, cppc_init_perf);
@@ -636,6 +1271,10 @@ static int __init amd_pstate_init(void)
return -ENODEV;
}
+ cpudata = vzalloc(array_size(sizeof(void *), num_possible_cpus()));
+ if (!cpudata)
+ return -ENOMEM;
+ WRITE_ONCE(all_cpu_data, cpudata);
/* enable amd pstate feature */
ret = amd_pstate_enable(true);
if (ret) {
@@ -643,9 +1282,9 @@ static int __init amd_pstate_init(void)
return ret;
}
- ret = cpufreq_register_driver(&amd_pstate_driver);
+ ret = cpufreq_register_driver(default_pstate_driver);
if (ret)
- pr_err("failed to register amd_pstate_driver with return %d\n",
+ pr_err("failed to register amd pstate driver with return %d\n",
ret);
return ret;
@@ -657,6 +1296,15 @@ static int __init amd_pstate_param(char *str)
if (!str)
return -EINVAL;
+ if (!strcmp(str, "disable"))
+ disable_pstate_load = 1;
+ else if (!strcmp(str, "active")) {
+ default_pstate_driver = &amd_pstate_epp_driver;
+ } else if (!strcmp(str, "passive")) {
+ epp_off = 1;
+ default_pstate_driver = &amd_pstate_driver;
+ }
+
/* enable shared memory type CPPC ,if you processor has no MSR, you have to add this
* to your grub to make cppc driver loaded successfully.
*/
diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h
index 1c4b8659f171..7e6e8cab97b3 100644
--- a/include/linux/amd-pstate.h
+++ b/include/linux/amd-pstate.h
@@ -25,6 +25,7 @@ struct amd_aperf_mperf {
u64 aperf;
u64 mperf;
u64 tsc;
+ u64 time;
};
/**
@@ -47,6 +48,18 @@ struct amd_aperf_mperf {
* @prev: Last Aperf/Mperf/tsc count value read from register
* @freq: current cpu frequency value
* @boost_supported: check whether the Processor or SBIOS supports boost mode
+ * @epp_powersave: Last saved CPPC energy performance preference
+ when policy switched to performance
+ * @epp_policy: Last saved policy used to set energy-performance preference
+ * @epp_cached: Cached CPPC energy-performance preference value
+ * @policy: Cpufreq policy value
+ * @sched_flags: Store scheduler flags for possible cross CPU update
+ * @update_util_set: CPUFreq utility callback is set
+ * @last_update: Time stamp of the last performance state update
+ * @cppc_boost_min: Last CPPC boosted min performance state
+ * @cppc_cap1_cached: Cached value of the last CPPC Capabilities MSR
+ * @update_util: Cpufreq utility callback information
+ * @sample: the stored performance sample
*
* The amd_cpudata is key private data for each CPU thread in AMD P-State, and
* represents all the attributes and goals that AMD P-State requests at runtime.
@@ -72,6 +85,74 @@ struct amd_cpudata {
u64 freq;
bool boost_supported;
+
+ /* EPP feature related attributes*/
+ s16 epp_powersave;
+ s16 epp_policy;
+ s16 epp_cached;
+ u32 policy;
+ u32 sched_flags;
+ bool update_util_set;
+ u64 last_update;
+ u64 last_io_update;
+ u32 cppc_boost_min;
+ u64 cppc_cap1_cached;
+ struct update_util_data update_util;
+ struct amd_aperf_mperf sample;
+};
+
+/**
+ * struct amd_pstate_params - global parameters for the performance control
+ * @ cppc_boost_disabled wheher the core performance boost disabled
+ */
+struct amd_pstate_params {
+ bool cppc_boost_disabled;
+};
+
+#define AMD_CPPC_EPP_PERFORMANCE 0x00
+#define AMD_CPPC_EPP_BALANCE_PERFORMANCE 0x80
+#define AMD_CPPC_EPP_BALANCE_POWERSAVE 0xBF
+#define AMD_CPPC_EPP_POWERSAVE 0xFF
+
+/*
+ * AMD Energy Preference Performance (EPP)
+ * The EPP is used in the CCLK DPM controller to drive
+ * the frequency that a core is going to operate during
+ * short periods of activity. EPP values will be utilized for
+ * different OS profiles (balanced, performance, power savings)
+ * display strings corresponding to EPP index in the
+ * energy_perf_strings[]
+ * index String
+ *-------------------------------------
+ * 0 default
+ * 1 performance
+ * 2 balance_performance
+ * 3 balance_power
+ * 4 power
+ */
+enum energy_perf_value_index {
+ EPP_INDEX_DEFAULT = 0,
+ EPP_INDEX_PERFORMANCE,
+ EPP_INDEX_BALANCE_PERFORMANCE,
+ EPP_INDEX_BALANCE_POWERSAVE,
+ EPP_INDEX_POWERSAVE,
+};
+
+static const char * const energy_perf_strings[] = {
+ [EPP_INDEX_DEFAULT] = "default",
+ [EPP_INDEX_PERFORMANCE] = "performance",
+ [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance",
+ [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power",
+ [EPP_INDEX_POWERSAVE] = "power",
+ NULL
+};
+
+static unsigned int epp_values[] = {
+ [EPP_INDEX_DEFAULT] = 0,
+ [EPP_INDEX_PERFORMANCE] = AMD_CPPC_EPP_PERFORMANCE,
+ [EPP_INDEX_BALANCE_PERFORMANCE] = AMD_CPPC_EPP_BALANCE_PERFORMANCE,
+ [EPP_INDEX_BALANCE_POWERSAVE] = AMD_CPPC_EPP_BALANCE_POWERSAVE,
+ [EPP_INDEX_POWERSAVE] = AMD_CPPC_EPP_POWERSAVE,
};
#endif /* _LINUX_AMD_PSTATE_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [PATCH v3 4/8] cpufreq: amd_pstate: add AMD Pstate EPP support for the MSR based processors
2022-11-07 17:57 ` [PATCH v3 4/8] cpufreq: amd_pstate: add AMD Pstate EPP support for the MSR based processors Perry Yuan
@ 2022-11-07 20:32 ` Limonciello, Mario
2022-11-10 15:59 ` Nathan Fontenot
0 siblings, 1 reply; 35+ messages in thread
From: Limonciello, Mario @ 2022-11-07 20:32 UTC (permalink / raw)
To: Perry Yuan, rafael.j.wysocki, ray.huang, viresh.kumar
Cc: Deepak.Sharma, Nathan.Fontenot, Alexander.Deucher, Shimmer.Huang,
Xiaojian.Du, Li.Meng, linux-pm, linux-kernel
On 11/7/2022 11:57, Perry Yuan wrote:
> Add EPP driver support for those AMD CPUs which has full MSR feature
> enabled, The EPP is used in the DPM controller to drive the frequency
> that a core is going to operate during short periods of activity.
To avoid the run on sentence, here is a different wording proposal.
Add EPP driver support for AMD SoCs which support a dedicated MSR for
CPPC. EPP is used by the DPM controller to configure the frequency that
a core operates at during short periods of activity.
>
> EPP values will be utilized for different OS profiles (balanced, performance,
> power savings). cppc performance can be controlled by the user space interface
> sys attributes for min and max frequency limits, when pstate driver is
> working under power save policy.
>
> EPP scale is 0 - 255, 0 is the max performance and 255 is min level.
> balance_performance (0x80) can provide best balance performance and watt for
> most of system, meanwhile user can choose performance policy on needs.
As a user reading this message it is confusing that there are values and
then there are strings, but you don't know the linkage between the two.
My proposal for rewording this:
The SoC EPP targets are configured on a scale from 0 to 255 where 0
represents maximum performance and 255 represents maximum efficiency.
The amd-pstate driver exports profile string names to userspace that are
tied to specific EPP values.
The balance_performance string (0x80) provides the best balance for
efficiency versus power on most systems, but users can choose other
strings to meet their needs as well.
>
> $ cat /sys/devices/system/cpu/cpufreq/policy0/energy_performance_available_preferences
> default performance balance_performance balance_power power
>
> $ cat /sys/devices/system/cpu/cpufreq/policy0/energy_performance_preference
> balance_performance
>
> Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
> ---
> drivers/cpufreq/amd-pstate.c | 658 ++++++++++++++++++++++++++++++++++-
> include/linux/amd-pstate.h | 81 +++++
> 2 files changed, 734 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
> index 14906431dc15..eb82bc6a7f66 100644
> --- a/drivers/cpufreq/amd-pstate.c
> +++ b/drivers/cpufreq/amd-pstate.c
> @@ -60,8 +60,136 @@
> * module parameter to be able to enable it manually for debugging.
> */
> static bool shared_mem __read_mostly;
> +static int cppc_active __read_mostly;
> +static int disable_pstate_load __initdata;
> +static int epp_off __initdata;
>
> -static struct cpufreq_driver amd_pstate_driver;
> +static struct cpufreq_driver *default_pstate_driver;
> +static struct amd_cpudata **all_cpu_data;
> +
> +static struct amd_pstate_params global_params;
> +
> +static DEFINE_MUTEX(amd_pstate_limits_lock);
> +static DEFINE_MUTEX(amd_pstate_driver_lock);
> +
> +static bool cppc_boost __read_mostly;
> +struct kobject *amd_pstate_kobj;
> +
> +#ifdef CONFIG_ACPI_CPPC_LIB
> +static s16 amd_pstate_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached)
> +{
> + s16 epp;
> + struct cppc_perf_caps perf_caps;
> + int ret;
> +
> + if (boot_cpu_has(X86_FEATURE_CPPC)) {
> + if (!cppc_req_cached) {
> + epp = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ,
> + &cppc_req_cached);
> + if (epp)
> + return epp;
> + }
> + epp = (cppc_req_cached >> 24) & 0xFF;
> + } else {
> + ret = cppc_get_epp_caps(cpudata->cpu, &perf_caps);
> + if (ret < 0) {
> + pr_debug("Could not retrieve energy perf value (%d)\n", ret);
> + return -EIO;
> + }
> + epp = (s16) perf_caps.energy_perf;
> + }
> +
> + return epp;
> +}
> +#endif
> +
> +static int amd_pstate_get_energy_pref_index(struct amd_cpudata *cpudata, int *raw_epp)
> +{
> + s16 epp;
> + int index = -EINVAL;
> +
> + *raw_epp = 0;
> + epp = amd_pstate_get_epp(cpudata, 0);
> + if (epp < 0)
> + return epp;
> +
> + switch (epp) {
> + case AMD_CPPC_EPP_PERFORMANCE:
> + index = EPP_INDEX_PERFORMANCE;
> + break;
> + case AMD_CPPC_EPP_BALANCE_PERFORMANCE:
> + index = EPP_INDEX_BALANCE_PERFORMANCE;
> + break;
> + case AMD_CPPC_EPP_BALANCE_POWERSAVE:
> + index = EPP_INDEX_BALANCE_POWERSAVE;
> + break;
> + case AMD_CPPC_EPP_POWERSAVE:
> + index = EPP_INDEX_POWERSAVE;
> + break;
> + default:
> + *raw_epp = epp;
> + index = 0;
> + }
> +
> + return index;
> +}
> +
> +#ifdef CONFIG_ACPI_CPPC_LIB
> +static int amd_pstate_set_epp(struct amd_cpudata *cpudata, u32 epp)
> +{
> + int ret;
> + struct cppc_perf_ctrls perf_ctrls;
> +
> + if (boot_cpu_has(X86_FEATURE_CPPC)) {
> + u64 value = READ_ONCE(cpudata->cppc_req_cached);
> +
> + value &= ~GENMASK_ULL(31, 24);
> + value |= (u64)epp << 24;
> + WRITE_ONCE(cpudata->cppc_req_cached, value);
> +
> + ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
> + if (!ret)
> + cpudata->epp_cached = epp;
> + } else {
> + perf_ctrls.energy_perf = epp;
> + ret = cppc_set_epp_perf(cpudata->cpu, &perf_ctrls);
> + if (ret) {
> + pr_debug("failed to set energy perf value (%d)\n", ret);
> + return ret;
> + }
> + cpudata->epp_cached = epp;
> + }
> +
> + return ret;
> +}
> +
> +static int amd_pstate_set_energy_pref_index(struct amd_cpudata *cpudata,
> + int pref_index, bool use_raw,
> + u32 raw_epp)
> +{
> + int epp = -EINVAL;
> + int ret;
> +
> + if (!pref_index) {
> + pr_debug("EPP pref_index is invalid\n");
> + return -EINVAL;
> + }
> +
> + if (use_raw)
> + epp = raw_epp;
> + else if (epp == -EINVAL)
> + epp = epp_values[pref_index];
> +
> + if (epp > 0 && cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) {
> + pr_debug("EPP cannot be set under performance policy\n");
> + return -EBUSY;
> + }
> +
> + ret = amd_pstate_set_epp(cpudata, epp);
> +
> + return ret;
> +}
> +#endif
>
> static inline int pstate_enable(bool enable)
> {
> @@ -71,11 +199,25 @@ static inline int pstate_enable(bool enable)
> static int cppc_enable(bool enable)
> {
> int cpu, ret = 0;
> + struct cppc_perf_ctrls perf_ctrls;
>
> for_each_present_cpu(cpu) {
> ret = cppc_set_enable(cpu, enable);
> if (ret)
> return ret;
> +
> + /* Enable autonomous mode for EPP */
> + if (!cppc_active) {
> + ret = cppc_set_auto_epp(cpu, enable);
> + if (ret)
> + return ret;
> +
> + /* Set desired perf as zero to allow EPP firmware control */
> + perf_ctrls.desired_perf = 0;
> + ret = cppc_set_perf(cpu, &perf_ctrls);
> + if (ret)
> + return ret;
> + }
> }
>
> return ret;
> @@ -418,7 +560,7 @@ static void amd_pstate_boost_init(struct amd_cpudata *cpudata)
> return;
>
> cpudata->boost_supported = true;
> - amd_pstate_driver.boost_enabled = true;
> + default_pstate_driver->boost_enabled = true;
> }
>
> static int amd_pstate_cpu_init(struct cpufreq_policy *policy)
> @@ -582,10 +724,74 @@ static ssize_t show_amd_pstate_highest_perf(struct cpufreq_policy *policy,
> return sprintf(&buf[0], "%u\n", perf);
> }
>
> +static ssize_t show_energy_performance_available_preferences(
> + struct cpufreq_policy *policy, char *buf)
> +{
> + int i = 0;
> + int ret = 0;
> +
> + while (energy_perf_strings[i] != NULL)
> + ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
> +
> + ret += sprintf(&buf[ret], "\n");
> +
> + return ret;
> +}
> +
> +static ssize_t store_energy_performance_preference(
> + struct cpufreq_policy *policy, const char *buf, size_t count)
> +{
> + struct amd_cpudata *cpudata = policy->driver_data;
> + char str_preference[21];
> + bool raw = false;
> + ssize_t ret;
> + u32 epp = 0;
> +
> + ret = sscanf(buf, "%20s", str_preference);
> + if (ret != 1)
> + return -EINVAL;
> +
> + ret = match_string(energy_perf_strings, -1, str_preference);
> + if (ret < 0) {
> + ret = kstrtouint(buf, 10, &epp);
> + if (ret)
> + return ret;
> +
> + if ((epp > 255) || (epp < 0))
> + return -EINVAL;
> +
> + raw = true;
> + }
What's the reason for supporting putting the raw number in here for
stuff "in between"? I think this is going to pretty confusing to
userspace that you can use string values or integer values. It also
means that if userspace writes an integer with a mapping to string and
tries to read it back they'll get the string rather than the integer!
I can understand using the raw values for internal characterization and
development to possibly introduce a new mapping string, but I don't
think that makes sense in the kernel.
> +
> + mutex_lock(&amd_pstate_limits_lock);
> + ret = amd_pstate_set_energy_pref_index(cpudata, ret, raw, epp);
> + mutex_unlock(&amd_pstate_limits_lock);
> +
> + return ret ?: count;
> +}
> +
> +static ssize_t show_energy_performance_preference(
> + struct cpufreq_policy *policy, char *buf)
> +{
> + struct amd_cpudata *cpudata = policy->driver_data;
> + int preference, raw_epp;
> +
> + preference = amd_pstate_get_energy_pref_index(cpudata, &raw_epp);
> + if (preference < 0)
> + return preference;
> +
> + if (raw_epp)
> + return sprintf(buf, "%d\n", raw_epp);
> + else
> + return sprintf(buf, "%s\n", energy_perf_strings[preference]);
> +}
> +
> cpufreq_freq_attr_ro(amd_pstate_max_freq);
> cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq);
>
> cpufreq_freq_attr_ro(amd_pstate_highest_perf);
> +cpufreq_freq_attr_rw(energy_performance_preference);
> +cpufreq_freq_attr_ro(energy_performance_available_preferences);
>
> static struct freq_attr *amd_pstate_attr[] = {
> &amd_pstate_max_freq,
> @@ -594,6 +800,415 @@ static struct freq_attr *amd_pstate_attr[] = {
> NULL,
> };
>
> +static struct freq_attr *amd_pstate_epp_attr[] = {
> + &amd_pstate_max_freq,
> + &amd_pstate_lowest_nonlinear_freq,
> + &amd_pstate_highest_perf,
> + &energy_performance_preference,
> + &energy_performance_available_preferences,
> + NULL,
> +};
> +
> +static inline void update_boost_state(void)
> +{
> + u64 misc_en;
> + struct amd_cpudata *cpudata;
> +
> + cpudata = all_cpu_data[0];
> + rdmsrl(MSR_K7_HWCR, misc_en);
> + global_params.cppc_boost_disabled = misc_en & BIT_ULL(25);
> +}
> +
> +static int amd_pstate_init_cpu(unsigned int cpunum)
> +{
> + struct amd_cpudata *cpudata;
> +
> + cpudata = all_cpu_data[cpunum];
> + if (!cpudata) {
> + cpudata = kzalloc(sizeof(*cpudata), GFP_KERNEL);
> + if (!cpudata)
> + return -ENOMEM;
> + WRITE_ONCE(all_cpu_data[cpunum], cpudata);
> +
> + cpudata->cpu = cpunum;
> + }
> + cpudata->epp_powersave = -EINVAL;
> + cpudata->epp_policy = 0;
> + pr_debug("controlling: cpu %d\n", cpunum);
> + return 0;
> +}
> +
> +static int __amd_pstate_cpu_init(struct cpufreq_policy *policy)
> +{
> + int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret;
> + struct amd_cpudata *cpudata;
> + struct device *dev;
> + int rc;
> + u64 value;
> +
> + rc = amd_pstate_init_cpu(policy->cpu);
> + if (rc)
> + return rc;
> +
> + cpudata = all_cpu_data[policy->cpu];
> +
> + dev = get_cpu_device(policy->cpu);
> + if (!dev)
> + goto free_cpudata1;
> +
> + rc = amd_pstate_init_perf(cpudata);
> + if (rc)
> + goto free_cpudata1;
> +
> + min_freq = amd_get_min_freq(cpudata);
> + max_freq = amd_get_max_freq(cpudata);
> + nominal_freq = amd_get_nominal_freq(cpudata);
> + lowest_nonlinear_freq = amd_get_lowest_nonlinear_freq(cpudata);
> + if (min_freq < 0 || max_freq < 0 || min_freq > max_freq) {
> + dev_err(dev, "min_freq(%d) or max_freq(%d) value is incorrect\n",
> + min_freq, max_freq);
> + ret = -EINVAL;
> + goto free_cpudata1;
> + }
> +
> + policy->min = min_freq;
> + policy->max = max_freq;
> +
> + policy->cpuinfo.min_freq = min_freq;
> + policy->cpuinfo.max_freq = max_freq;
> + /* It will be updated by governor */
> + policy->cur = policy->cpuinfo.min_freq;
> +
> + /* Initial processor data capability frequencies */
> + cpudata->max_freq = max_freq;
> + cpudata->min_freq = min_freq;
> + cpudata->nominal_freq = nominal_freq;
> + cpudata->lowest_nonlinear_freq = lowest_nonlinear_freq;
> +
> + policy->driver_data = cpudata;
> +
> + update_boost_state();
> + cpudata->epp_cached = amd_pstate_get_epp(cpudata, value);
> +
> + policy->min = policy->cpuinfo.min_freq;
> + policy->max = policy->cpuinfo.max_freq;
> +
> + if (boot_cpu_has(X86_FEATURE_CPPC))
> + policy->fast_switch_possible = true;
> +
> + if (!shared_mem && boot_cpu_has(X86_FEATURE_CPPC)) {
> + ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value);
> + if (ret)
> + return ret;
> + WRITE_ONCE(cpudata->cppc_req_cached, value);
> +
> + ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, &value);
> + if (ret)
> + return ret;
> + WRITE_ONCE(cpudata->cppc_cap1_cached, value);
> + }
> + amd_pstate_boost_init(cpudata);
> +
> + return 0;
> +
> +free_cpudata1:
> + kfree(cpudata);
> + return ret;
> +}
> +
> +static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy)
> +{
> + int ret;
> +
> + ret = __amd_pstate_cpu_init(policy);
> + if (ret)
> + return ret;
> + /*
> + * Set the policy to powersave to provide a valid fallback value in case
> + * the default cpufreq governor is neither powersave nor performance.
> + */
> + policy->policy = CPUFREQ_POLICY_POWERSAVE;
> +
> + return 0;
> +}
> +
> +static int amd_pstate_epp_cpu_exit(struct cpufreq_policy *policy)
> +{
> + pr_debug("amd-pstate: CPU %d exiting\n", policy->cpu);
Drop the "amd-pstate:", this file has pr_fmt.
> + policy->fast_switch_possible = false;
> + return 0;
> +}
> +
> +static void amd_pstate_update_max_freq(unsigned int cpu)
> +{
> + struct cpufreq_policy *policy = policy = cpufreq_cpu_get(cpu);
> +
> + if (!policy)
> + return;
> +
> + refresh_frequency_limits(policy);
> + cpufreq_cpu_put(policy);
> +}
> +
> +static void amd_pstate_epp_update_limits(unsigned int cpu)
> +{
> + mutex_lock(&amd_pstate_driver_lock);
> + update_boost_state();
> + if (global_params.cppc_boost_disabled) {
> + for_each_possible_cpu(cpu)
> + amd_pstate_update_max_freq(cpu);
> + } else {
> + cpufreq_update_policy(cpu);
> + }
> + mutex_unlock(&amd_pstate_driver_lock);
> +}
> +
> +static int cppc_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
> +
> +static inline void amd_pstate_boost_up(struct amd_cpudata *cpudata)
> +{
> + u64 hwp_req = READ_ONCE(cpudata->cppc_req_cached);
> + u64 hwp_cap = READ_ONCE(cpudata->cppc_cap1_cached);
> + u32 max_limit = (hwp_req & 0xff);
> + u32 min_limit = (hwp_req & 0xff00) >> 8;
> + u32 boost_level1;
> +
> + /* If max and min are equal or already at max, nothing to boost */
> + if (max_limit == min_limit)
> + return;
> +
> + /* Set boost max and min to initial value */
> + if (!cpudata->cppc_boost_min)
> + cpudata->cppc_boost_min = min_limit;
> +
> + boost_level1 = ((AMD_CPPC_NOMINAL_PERF(hwp_cap) + min_limit) >> 1);
> +
> + if (cpudata->cppc_boost_min < boost_level1)
> + cpudata->cppc_boost_min = boost_level1;
> + else if (cpudata->cppc_boost_min < AMD_CPPC_NOMINAL_PERF(hwp_cap))
> + cpudata->cppc_boost_min = AMD_CPPC_NOMINAL_PERF(hwp_cap);
> + else if (cpudata->cppc_boost_min == AMD_CPPC_NOMINAL_PERF(hwp_cap))
> + cpudata->cppc_boost_min = max_limit;
> + else
> + return;
> +
> + hwp_req &= ~AMD_CPPC_MIN_PERF(~0L);
> + hwp_req |= AMD_CPPC_MIN_PERF(cpudata->cppc_boost_min);
> + wrmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, hwp_req);
> + cpudata->last_update = cpudata->sample.time;
> +}
> +
> +static inline void amd_pstate_boost_down(struct amd_cpudata *cpudata)
> +{
> + bool expired;
> +
> + if (cpudata->cppc_boost_min) {
> + expired = time_after64(cpudata->sample.time, cpudata->last_update +
> + cppc_boost_hold_time_ns);
> +
> + if (expired) {
> + wrmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ,
> + cpudata->cppc_req_cached);
> + cpudata->cppc_boost_min = 0;
> + }
> + }
> +
> + cpudata->last_update = cpudata->sample.time;
> +}
> +
> +static inline void amd_pstate_boost_update_util(struct amd_cpudata *cpudata,
> + u64 time)
> +{
> + cpudata->sample.time = time;
> + if (smp_processor_id() != cpudata->cpu)
> + return;
> +
> + if (cpudata->sched_flags & SCHED_CPUFREQ_IOWAIT) {
> + bool do_io = false;
> +
> + cpudata->sched_flags = 0;
> + /*
> + * Set iowait_boost flag and update time. Since IO WAIT flag
> + * is set all the time, we can't just conclude that there is
> + * some IO bound activity is scheduled on this CPU with just
> + * one occurrence. If we receive at least two in two
> + * consecutive ticks, then we treat as boost candidate.
> + * This is leveraged from Intel Pstate driver.
> + */
> + if (time_before64(time, cpudata->last_io_update + 2 * TICK_NSEC))
> + do_io = true;
> +
> + cpudata->last_io_update = time;
> +
> + if (do_io)
> + amd_pstate_boost_up(cpudata);
> +
> + } else {
> + amd_pstate_boost_down(cpudata);
> + }
> +}
> +
> +static inline void amd_pstate_cppc_update_hook(struct update_util_data *data,
> + u64 time, unsigned int flags)
> +{
> + struct amd_cpudata *cpudata = container_of(data,
> + struct amd_cpudata, update_util);
> +
> + cpudata->sched_flags |= flags;
> +
> + if (smp_processor_id() == cpudata->cpu)
> + amd_pstate_boost_update_util(cpudata, time);
> +}
> +
> +static void amd_pstate_clear_update_util_hook(unsigned int cpu)
> +{
> + struct amd_cpudata *cpudata = all_cpu_data[cpu];
> +
> + if (!cpudata->update_util_set)
> + return;
> +
> + cpufreq_remove_update_util_hook(cpu);
> + cpudata->update_util_set = false;
> + synchronize_rcu();
> +}
> +
> +static void amd_pstate_set_update_util_hook(unsigned int cpu_num)
> +{
> + struct amd_cpudata *cpudata = all_cpu_data[cpu_num];
> +
> + if (!cppc_boost) {
> + if (cpudata->update_util_set)
> + amd_pstate_clear_update_util_hook(cpudata->cpu);
> + return;
> + }
> +
> + if (cpudata->update_util_set)
> + return;
> +
> + cpudata->sample.time = 0;
> + cpufreq_add_update_util_hook(cpu_num, &cpudata->update_util,
> + amd_pstate_cppc_update_hook);
> + cpudata->update_util_set = true;
> +}
> +
> +static void amd_pstate_epp_init(unsigned int cpu)
> +{
> + struct amd_cpudata *cpudata = all_cpu_data[cpu];
> + u32 max_perf, min_perf;
> + u64 value;
> + s16 epp;
> + int ret;
> +
> + max_perf = READ_ONCE(cpudata->highest_perf);
> + min_perf = READ_ONCE(cpudata->lowest_perf);
> +
> + value = READ_ONCE(cpudata->cppc_req_cached);
> +
> + if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE)
> + min_perf = max_perf;
> +
> + /* Initial min/max values for CPPC Performance Controls Register */
> + value &= ~AMD_CPPC_MIN_PERF(~0L);
> + value |= AMD_CPPC_MIN_PERF(min_perf);
> +
> + value &= ~AMD_CPPC_MAX_PERF(~0L);
> + value |= AMD_CPPC_MAX_PERF(max_perf);
> +
> + /* CPPC EPP feature require to set zero to the desire perf bit */
> + value &= ~AMD_CPPC_DES_PERF(~0L);
> + value |= AMD_CPPC_DES_PERF(0);
> +
> + if (cpudata->epp_policy == cpudata->policy)
> + goto skip_epp;
> +
> + cpudata->epp_policy = cpudata->policy;
> +
> + if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) {
> + epp = amd_pstate_get_epp(cpudata, value);
> + cpudata->epp_powersave = epp;
> + if (epp < 0)
> + goto skip_epp;
> + /* force the epp value to be zero for performance policy */
> + epp = 0;
> + } else {
> + if (cpudata->epp_powersave < 0)
> + goto skip_epp;
> + /* Get BIOS pre-defined epp value */
> + epp = amd_pstate_get_epp(cpudata, value);
> + if (epp)
> + goto skip_epp;
> + epp = cpudata->epp_powersave;
> + }
> + /* Set initial EPP value */
> + if (boot_cpu_has(X86_FEATURE_CPPC)) {
> + value &= ~GENMASK_ULL(31, 24);
> + value |= (u64)epp << 24;
> + }
> +
> +skip_epp:
> + WRITE_ONCE(cpudata->cppc_req_cached, value);
> + ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
> + if (!ret)
> + cpudata->epp_cached = epp;
> +}
> +
> +static void amd_pstate_set_max_limits(struct amd_cpudata *cpudata)
> +{
> + u64 hwp_cap = READ_ONCE(cpudata->cppc_cap1_cached);
> + u64 hwp_req = READ_ONCE(cpudata->cppc_req_cached);
> + u32 max_limit = (hwp_cap >> 24) & 0xff;
> +
> + hwp_req &= ~AMD_CPPC_MIN_PERF(~0L);
> + hwp_req |= AMD_CPPC_MIN_PERF(max_limit);
> + wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, hwp_req);
> +}
> +
> +static int amd_pstate_epp_set_policy(struct cpufreq_policy *policy)
> +{
> + struct amd_cpudata *cpudata;
> +
> + if (!policy->cpuinfo.max_freq)
> + return -ENODEV;
> +
> + pr_debug("set_policy: cpuinfo.max %u policy->max %u\n",
> + policy->cpuinfo.max_freq, policy->max);
> +
> + cpudata = all_cpu_data[policy->cpu];
> + cpudata->policy = policy->policy;
> +
> + if (boot_cpu_has(X86_FEATURE_CPPC)) {
> + mutex_lock(&amd_pstate_limits_lock);
> +
> + if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) {
> + amd_pstate_clear_update_util_hook(policy->cpu);
> + amd_pstate_set_max_limits(cpudata);
> + } else {
> + amd_pstate_set_update_util_hook(policy->cpu);
> + }
> +
> + if (boot_cpu_has(X86_FEATURE_CPPC))
> + amd_pstate_epp_init(policy->cpu);
> +
> + mutex_unlock(&amd_pstate_limits_lock);
> + }
> +
> + return 0;
> +}
> +
> +static void amd_pstate_verify_cpu_policy(struct amd_cpudata *cpudata,
> + struct cpufreq_policy_data *policy)
> +{
> + update_boost_state();
> + cpufreq_verify_within_cpu_limits(policy);
> +}
> +
> +static int amd_pstate_epp_verify_policy(struct cpufreq_policy_data *policy)
> +{
> + amd_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy);
> + pr_debug("policy_max =%d, policy_min=%d\n", policy->max, policy->min);
> + return 0;
> +}
> +
> static struct cpufreq_driver amd_pstate_driver = {
> .flags = CPUFREQ_CONST_LOOPS | CPUFREQ_NEED_UPDATE_LIMITS,
> .verify = amd_pstate_verify,
> @@ -607,8 +1222,20 @@ static struct cpufreq_driver amd_pstate_driver = {
> .attr = amd_pstate_attr,
> };
>
> +static struct cpufreq_driver amd_pstate_epp_driver = {
> + .flags = CPUFREQ_CONST_LOOPS,
> + .verify = amd_pstate_epp_verify_policy,
> + .setpolicy = amd_pstate_epp_set_policy,
> + .init = amd_pstate_epp_cpu_init,
> + .exit = amd_pstate_epp_cpu_exit,
> + .update_limits = amd_pstate_epp_update_limits,
> + .name = "amd_pstate_epp",
> + .attr = amd_pstate_epp_attr,
> +};
> +
> static int __init amd_pstate_init(void)
> {
> + static struct amd_cpudata **cpudata;
> int ret;
>
> if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
> @@ -623,10 +1250,18 @@ static int __init amd_pstate_init(void)
> if (cpufreq_get_current_driver())
> return -EEXIST;
>
> + if (!epp_off) {
> + WRITE_ONCE(cppc_active, 1);
> + if (!default_pstate_driver)
> + default_pstate_driver = &amd_pstate_epp_driver;
> + }
> + pr_info("AMD CPPC loading with %s driver instance.\n", default_pstate_driver->name);
This is pretty noisy, do we really need it on every boot if we can
easily check it from sysfs?
> +
> /* capability check */
> if (boot_cpu_has(X86_FEATURE_CPPC)) {
> + if (!cppc_active)
> + default_pstate_driver->adjust_perf = amd_pstate_adjust_perf;
> pr_debug("AMD CPPC MSR based functionality is supported\n");
> - amd_pstate_driver.adjust_perf = amd_pstate_adjust_perf;
> } else if (shared_mem) {
> static_call_update(amd_pstate_enable, cppc_enable);
> static_call_update(amd_pstate_init_perf, cppc_init_perf);
> @@ -636,6 +1271,10 @@ static int __init amd_pstate_init(void)
> return -ENODEV;
> }
>
> + cpudata = vzalloc(array_size(sizeof(void *), num_possible_cpus()));
> + if (!cpudata)
> + return -ENOMEM;
> + WRITE_ONCE(all_cpu_data, cpudata);
> /* enable amd pstate feature */
> ret = amd_pstate_enable(true);
> if (ret) {
> @@ -643,9 +1282,9 @@ static int __init amd_pstate_init(void)
> return ret;
> }
>
> - ret = cpufreq_register_driver(&amd_pstate_driver);
> + ret = cpufreq_register_driver(default_pstate_driver);
> if (ret)
> - pr_err("failed to register amd_pstate_driver with return %d\n",
> + pr_err("failed to register amd pstate driver with return %d\n",
> ret);
>
> return ret;
> @@ -657,6 +1296,15 @@ static int __init amd_pstate_param(char *str)
> if (!str)
> return -EINVAL;
>
> + if (!strcmp(str, "disable"))
> + disable_pstate_load = 1;
> + else if (!strcmp(str, "active")) {
> + default_pstate_driver = &amd_pstate_epp_driver;
> + } else if (!strcmp(str, "passive")) {
> + epp_off = 1;
> + default_pstate_driver = &amd_pstate_driver;
> + }
> +
> /* enable shared memory type CPPC ,if you processor has no MSR, you have to add this
> * to your grub to make cppc driver loaded successfully.
> */
> diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h
> index 1c4b8659f171..7e6e8cab97b3 100644
> --- a/include/linux/amd-pstate.h
> +++ b/include/linux/amd-pstate.h
> @@ -25,6 +25,7 @@ struct amd_aperf_mperf {
> u64 aperf;
> u64 mperf;
> u64 tsc;
> + u64 time;
> };
>
> /**
> @@ -47,6 +48,18 @@ struct amd_aperf_mperf {
> * @prev: Last Aperf/Mperf/tsc count value read from register
> * @freq: current cpu frequency value
> * @boost_supported: check whether the Processor or SBIOS supports boost mode
> + * @epp_powersave: Last saved CPPC energy performance preference
> + when policy switched to performance
> + * @epp_policy: Last saved policy used to set energy-performance preference
> + * @epp_cached: Cached CPPC energy-performance preference value
> + * @policy: Cpufreq policy value
> + * @sched_flags: Store scheduler flags for possible cross CPU update
> + * @update_util_set: CPUFreq utility callback is set
> + * @last_update: Time stamp of the last performance state update
> + * @cppc_boost_min: Last CPPC boosted min performance state
> + * @cppc_cap1_cached: Cached value of the last CPPC Capabilities MSR
> + * @update_util: Cpufreq utility callback information
> + * @sample: the stored performance sample
> *
> * The amd_cpudata is key private data for each CPU thread in AMD P-State, and
> * represents all the attributes and goals that AMD P-State requests at runtime.
> @@ -72,6 +85,74 @@ struct amd_cpudata {
>
> u64 freq;
> bool boost_supported;
> +
> + /* EPP feature related attributes*/
> + s16 epp_powersave;
> + s16 epp_policy;
> + s16 epp_cached;
> + u32 policy;
> + u32 sched_flags;
> + bool update_util_set;
> + u64 last_update;
> + u64 last_io_update;
> + u32 cppc_boost_min;
> + u64 cppc_cap1_cached;
> + struct update_util_data update_util;
> + struct amd_aperf_mperf sample;
> +};
> +
> +/**
> + * struct amd_pstate_params - global parameters for the performance control
> + * @ cppc_boost_disabled wheher the core performance boost disabled
> + */
> +struct amd_pstate_params {
> + bool cppc_boost_disabled;
> +};
> +
> +#define AMD_CPPC_EPP_PERFORMANCE 0x00
> +#define AMD_CPPC_EPP_BALANCE_PERFORMANCE 0x80
> +#define AMD_CPPC_EPP_BALANCE_POWERSAVE 0xBF
> +#define AMD_CPPC_EPP_POWERSAVE 0xFF
> +
> +/*
> + * AMD Energy Preference Performance (EPP)
> + * The EPP is used in the CCLK DPM controller to drive
> + * the frequency that a core is going to operate during
> + * short periods of activity. EPP values will be utilized for
> + * different OS profiles (balanced, performance, power savings)
> + * display strings corresponding to EPP index in the
> + * energy_perf_strings[]
> + * index String
> + *-------------------------------------
> + * 0 default
> + * 1 performance
> + * 2 balance_performance
> + * 3 balance_power
> + * 4 power
> + */
> +enum energy_perf_value_index {
> + EPP_INDEX_DEFAULT = 0,
> + EPP_INDEX_PERFORMANCE,
> + EPP_INDEX_BALANCE_PERFORMANCE,
> + EPP_INDEX_BALANCE_POWERSAVE,
> + EPP_INDEX_POWERSAVE,
> +};
> +
> +static const char * const energy_perf_strings[] = {
> + [EPP_INDEX_DEFAULT] = "default",
> + [EPP_INDEX_PERFORMANCE] = "performance",
> + [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance",
> + [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power",
> + [EPP_INDEX_POWERSAVE] = "power",
> + NULL
> +};
> +
> +static unsigned int epp_values[] = {
> + [EPP_INDEX_DEFAULT] = 0,
> + [EPP_INDEX_PERFORMANCE] = AMD_CPPC_EPP_PERFORMANCE,
> + [EPP_INDEX_BALANCE_PERFORMANCE] = AMD_CPPC_EPP_BALANCE_PERFORMANCE,
> + [EPP_INDEX_BALANCE_POWERSAVE] = AMD_CPPC_EPP_BALANCE_POWERSAVE,
> + [EPP_INDEX_POWERSAVE] = AMD_CPPC_EPP_POWERSAVE,
> };
>
> #endif /* _LINUX_AMD_PSTATE_H */
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH v3 4/8] cpufreq: amd_pstate: add AMD Pstate EPP support for the MSR based processors
2022-11-07 20:32 ` Limonciello, Mario
@ 2022-11-10 15:59 ` Nathan Fontenot
2022-11-10 16:22 ` Yuan, Perry
0 siblings, 1 reply; 35+ messages in thread
From: Nathan Fontenot @ 2022-11-10 15:59 UTC (permalink / raw)
To: Limonciello, Mario, Perry Yuan, rafael.j.wysocki, ray.huang,
viresh.kumar
Cc: Deepak.Sharma, Alexander.Deucher, Shimmer.Huang, Xiaojian.Du,
Li.Meng, linux-pm, linux-kernel
On 11/7/22 14:32, Limonciello, Mario wrote:
> On 11/7/2022 11:57, Perry Yuan wrote:
>> Add EPP driver support for those AMD CPUs which has full MSR feature
>> enabled, The EPP is used in the DPM controller to drive the frequency
>> that a core is going to operate during short periods of activity.
>
> To avoid the run on sentence, here is a different wording proposal.
>
> Add EPP driver support for AMD SoCs which support a dedicated MSR for CPPC. EPP is used by the DPM controller to configure the frequency that a core operates at during short periods of activity.
>
>>
>> EPP values will be utilized for different OS profiles (balanced, performance,
>> power savings). cppc performance can be controlled by the user space interface
>> sys attributes for min and max frequency limits, when pstate driver is
>> working under power save policy.
>>
>> EPP scale is 0 - 255, 0 is the max performance and 255 is min level.
>> balance_performance (0x80) can provide best balance performance and watt for
>> most of system, meanwhile user can choose performance policy on needs.
>
> As a user reading this message it is confusing that there are values and then there are strings, but you don't know the linkage between the two. My proposal for rewording this:
>
> The SoC EPP targets are configured on a scale from 0 to 255 where 0 represents maximum performance and 255 represents maximum efficiency.
>
> The amd-pstate driver exports profile string names to userspace that are tied to specific EPP values.
>
> The balance_performance string (0x80) provides the best balance for efficiency versus power on most systems, but users can choose other strings to meet their needs as well.
>
>>
>> $ cat /sys/devices/system/cpu/cpufreq/policy0/energy_performance_available_preferences
>> default performance balance_performance balance_power power
>>
>> $ cat /sys/devices/system/cpu/cpufreq/policy0/energy_performance_preference
>> balance_performance
>>
>> Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
>> ---
>> drivers/cpufreq/amd-pstate.c | 658 ++++++++++++++++++++++++++++++++++-
>> include/linux/amd-pstate.h | 81 +++++
>> 2 files changed, 734 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
>> index 14906431dc15..eb82bc6a7f66 100644
>> --- a/drivers/cpufreq/amd-pstate.c
>> +++ b/drivers/cpufreq/amd-pstate.c
>> @@ -60,8 +60,136 @@
>> * module parameter to be able to enable it manually for debugging.
>> */
>> static bool shared_mem __read_mostly;
>> +static int cppc_active __read_mostly;
>> +static int disable_pstate_load __initdata;
>> +static int epp_off __initdata;
>> -static struct cpufreq_driver amd_pstate_driver;
>> +static struct cpufreq_driver *default_pstate_driver;
>> +static struct amd_cpudata **all_cpu_data;
>> +
>> +static struct amd_pstate_params global_params;
>> +
>> +static DEFINE_MUTEX(amd_pstate_limits_lock);
>> +static DEFINE_MUTEX(amd_pstate_driver_lock);
>> +
>> +static bool cppc_boost __read_mostly;
>> +struct kobject *amd_pstate_kobj;
>> +
>> +#ifdef CONFIG_ACPI_CPPC_LIB
>> +static s16 amd_pstate_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached)
>> +{
>> + s16 epp;
>> + struct cppc_perf_caps perf_caps;
>> + int ret;
>> +
>> + if (boot_cpu_has(X86_FEATURE_CPPC)) {
>> + if (!cppc_req_cached) {
>> + epp = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ,
>> + &cppc_req_cached);
>> + if (epp)
>> + return epp;
>> + }
>> + epp = (cppc_req_cached >> 24) & 0xFF;
>> + } else {
>> + ret = cppc_get_epp_caps(cpudata->cpu, &perf_caps);
>> + if (ret < 0) {
>> + pr_debug("Could not retrieve energy perf value (%d)\n", ret);
>> + return -EIO;
>> + }
>> + epp = (s16) perf_caps.energy_perf;
>> + }
>> +
>> + return epp;
>> +}
>> +#endif
>> +
>> +static int amd_pstate_get_energy_pref_index(struct amd_cpudata *cpudata, int *raw_epp)
>> +{
>> + s16 epp;
>> + int index = -EINVAL;
>> +
>> + *raw_epp = 0;
>> + epp = amd_pstate_get_epp(cpudata, 0);
>> + if (epp < 0)
>> + return epp;
>> +
>> + switch (epp) {
>> + case AMD_CPPC_EPP_PERFORMANCE:
>> + index = EPP_INDEX_PERFORMANCE;
>> + break;
>> + case AMD_CPPC_EPP_BALANCE_PERFORMANCE:
>> + index = EPP_INDEX_BALANCE_PERFORMANCE;
>> + break;
>> + case AMD_CPPC_EPP_BALANCE_POWERSAVE:
>> + index = EPP_INDEX_BALANCE_POWERSAVE;
>> + break;
>> + case AMD_CPPC_EPP_POWERSAVE:
>> + index = EPP_INDEX_POWERSAVE;
>> + break;
>> + default:
>> + *raw_epp = epp;
>> + index = 0;
>> + }
>> +
>> + return index;
>> +}
>> +
>> +#ifdef CONFIG_ACPI_CPPC_LIB
>> +static int amd_pstate_set_epp(struct amd_cpudata *cpudata, u32 epp)
>> +{
>> + int ret;
>> + struct cppc_perf_ctrls perf_ctrls;
>> +
>> + if (boot_cpu_has(X86_FEATURE_CPPC)) {
>> + u64 value = READ_ONCE(cpudata->cppc_req_cached);
>> +
>> + value &= ~GENMASK_ULL(31, 24);
>> + value |= (u64)epp << 24;
>> + WRITE_ONCE(cpudata->cppc_req_cached, value);
>> +
>> + ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
>> + if (!ret)
>> + cpudata->epp_cached = epp;
>> + } else {
>> + perf_ctrls.energy_perf = epp;
>> + ret = cppc_set_epp_perf(cpudata->cpu, &perf_ctrls);
>> + if (ret) {
>> + pr_debug("failed to set energy perf value (%d)\n", ret);
>> + return ret;
>> + }
>> + cpudata->epp_cached = epp;
>> + }
>> +
>> + return ret;
>> +}
>> +
>> +static int amd_pstate_set_energy_pref_index(struct amd_cpudata *cpudata,
>> + int pref_index, bool use_raw,
>> + u32 raw_epp)
>> +{
>> + int epp = -EINVAL;
>> + int ret;
>> +
>> + if (!pref_index) {
>> + pr_debug("EPP pref_index is invalid\n");
>> + return -EINVAL;
>> + }
>> +
>> + if (use_raw)
>> + epp = raw_epp;
>> + else if (epp == -EINVAL)
>> + epp = epp_values[pref_index];
>> +
>> + if (epp > 0 && cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) {
>> + pr_debug("EPP cannot be set under performance policy\n");
>> + return -EBUSY;
>> + }
>> +
>> + ret = amd_pstate_set_epp(cpudata, epp);
>> +
>> + return ret;
>> +}
>> +#endif
>> static inline int pstate_enable(bool enable)
>> {
>> @@ -71,11 +199,25 @@ static inline int pstate_enable(bool enable)
>> static int cppc_enable(bool enable)
>> {
>> int cpu, ret = 0;
>> + struct cppc_perf_ctrls perf_ctrls;
>> for_each_present_cpu(cpu) {
>> ret = cppc_set_enable(cpu, enable);
>> if (ret)
>> return ret;
>> +
>> + /* Enable autonomous mode for EPP */
>> + if (!cppc_active) {
>> + ret = cppc_set_auto_epp(cpu, enable);
>> + if (ret)
>> + return ret;
>> +
>> + /* Set desired perf as zero to allow EPP firmware control */
>> + perf_ctrls.desired_perf = 0;
>> + ret = cppc_set_perf(cpu, &perf_ctrls);
>> + if (ret)
>> + return ret;
>> + }
>> }
>> return ret;
>> @@ -418,7 +560,7 @@ static void amd_pstate_boost_init(struct amd_cpudata *cpudata)
>> return;
>> cpudata->boost_supported = true;
>> - amd_pstate_driver.boost_enabled = true;
>> + default_pstate_driver->boost_enabled = true;
>> }
>> static int amd_pstate_cpu_init(struct cpufreq_policy *policy)
>> @@ -582,10 +724,74 @@ static ssize_t show_amd_pstate_highest_perf(struct cpufreq_policy *policy,
>> return sprintf(&buf[0], "%u\n", perf);
>> }
>> +static ssize_t show_energy_performance_available_preferences(
>> + struct cpufreq_policy *policy, char *buf)
>> +{
>> + int i = 0;
>> + int ret = 0;
>> +
>> + while (energy_perf_strings[i] != NULL)
>> + ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
>> +
>> + ret += sprintf(&buf[ret], "\n");
>> +
>> + return ret;
>> +}
>> +
>> +static ssize_t store_energy_performance_preference(
>> + struct cpufreq_policy *policy, const char *buf, size_t count)
>> +{
>> + struct amd_cpudata *cpudata = policy->driver_data;
>> + char str_preference[21];
>> + bool raw = false;
>> + ssize_t ret;
>> + u32 epp = 0;
>> +
>> + ret = sscanf(buf, "%20s", str_preference);
>> + if (ret != 1)
>> + return -EINVAL;
>> +
>> + ret = match_string(energy_perf_strings, -1, str_preference);
>> + if (ret < 0) {
>> + ret = kstrtouint(buf, 10, &epp);
>> + if (ret)
>> + return ret;
>> +
>> + if ((epp > 255) || (epp < 0))
>> + return -EINVAL;
>> +
>> + raw = true;
>> + }
>
> What's the reason for supporting putting the raw number in here for stuff "in between"? I think this is going to pretty confusing to userspace that you can use string values or integer values. It also means that if userspace writes an integer with a mapping to string and tries to read it back they'll get the string rather than the integer!
>
> I can understand using the raw values for internal characterization and development to possibly introduce a new mapping string, but I don't think that makes sense in the kernel.
>
This is really doing what Intel does for handling EPP settings. Yes, writing a value and getting back a string
could be a bit confusing bit it is already done from the Intel side. I think keeping EPP value setting common
would be a good thing if we can do it.
I don't think we should remove the ability to set raw values, we're allowed a range of 0 - 255 for the EPP
setting. Why we then limit ourselves to only 4 or so values?
-Nathan
>> +
>> + mutex_lock(&amd_pstate_limits_lock);
>> + ret = amd_pstate_set_energy_pref_index(cpudata, ret, raw, epp);
>> + mutex_unlock(&amd_pstate_limits_lock);
>> +
>> + return ret ?: count;
>> +}
>> +
>> +static ssize_t show_energy_performance_preference(
>> + struct cpufreq_policy *policy, char *buf)
>> +{
>> + struct amd_cpudata *cpudata = policy->driver_data;
>> + int preference, raw_epp;
>> +
>> + preference = amd_pstate_get_energy_pref_index(cpudata, &raw_epp);
>> + if (preference < 0)
>> + return preference;
>> +
>> + if (raw_epp)
>> + return sprintf(buf, "%d\n", raw_epp);
>> + else
>> + return sprintf(buf, "%s\n", energy_perf_strings[preference]);
>> +}
>> +
>> cpufreq_freq_attr_ro(amd_pstate_max_freq);
>> cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq);
>> cpufreq_freq_attr_ro(amd_pstate_highest_perf);
>> +cpufreq_freq_attr_rw(energy_performance_preference);
>> +cpufreq_freq_attr_ro(energy_performance_available_preferences);
>> static struct freq_attr *amd_pstate_attr[] = {
>> &amd_pstate_max_freq,
>> @@ -594,6 +800,415 @@ static struct freq_attr *amd_pstate_attr[] = {
>> NULL,
>> };
>> +static struct freq_attr *amd_pstate_epp_attr[] = {
>> + &amd_pstate_max_freq,
>> + &amd_pstate_lowest_nonlinear_freq,
>> + &amd_pstate_highest_perf,
>> + &energy_performance_preference,
>> + &energy_performance_available_preferences,
>> + NULL,
>> +};
>> +
>> +static inline void update_boost_state(void)
>> +{
>> + u64 misc_en;
>> + struct amd_cpudata *cpudata;
>> +
>> + cpudata = all_cpu_data[0];
>> + rdmsrl(MSR_K7_HWCR, misc_en);
>> + global_params.cppc_boost_disabled = misc_en & BIT_ULL(25);
>> +}
>> +
>> +static int amd_pstate_init_cpu(unsigned int cpunum)
>> +{
>> + struct amd_cpudata *cpudata;
>> +
>> + cpudata = all_cpu_data[cpunum];
>> + if (!cpudata) {
>> + cpudata = kzalloc(sizeof(*cpudata), GFP_KERNEL);
>> + if (!cpudata)
>> + return -ENOMEM;
>> + WRITE_ONCE(all_cpu_data[cpunum], cpudata);
>> +
>> + cpudata->cpu = cpunum;
>> + }
>> + cpudata->epp_powersave = -EINVAL;
>> + cpudata->epp_policy = 0;
>> + pr_debug("controlling: cpu %d\n", cpunum);
>> + return 0;
>> +}
>> +
>> +static int __amd_pstate_cpu_init(struct cpufreq_policy *policy)
>> +{
>> + int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret;
>> + struct amd_cpudata *cpudata;
>> + struct device *dev;
>> + int rc;
>> + u64 value;
>> +
>> + rc = amd_pstate_init_cpu(policy->cpu);
>> + if (rc)
>> + return rc;
>> +
>> + cpudata = all_cpu_data[policy->cpu];
>> +
>> + dev = get_cpu_device(policy->cpu);
>> + if (!dev)
>> + goto free_cpudata1;
>> +
>> + rc = amd_pstate_init_perf(cpudata);
>> + if (rc)
>> + goto free_cpudata1;
>> +
>> + min_freq = amd_get_min_freq(cpudata);
>> + max_freq = amd_get_max_freq(cpudata);
>> + nominal_freq = amd_get_nominal_freq(cpudata);
>> + lowest_nonlinear_freq = amd_get_lowest_nonlinear_freq(cpudata);
>> + if (min_freq < 0 || max_freq < 0 || min_freq > max_freq) {
>> + dev_err(dev, "min_freq(%d) or max_freq(%d) value is incorrect\n",
>> + min_freq, max_freq);
>> + ret = -EINVAL;
>> + goto free_cpudata1;
>> + }
>> +
>> + policy->min = min_freq;
>> + policy->max = max_freq;
>> +
>> + policy->cpuinfo.min_freq = min_freq;
>> + policy->cpuinfo.max_freq = max_freq;
>> + /* It will be updated by governor */
>> + policy->cur = policy->cpuinfo.min_freq;
>> +
>> + /* Initial processor data capability frequencies */
>> + cpudata->max_freq = max_freq;
>> + cpudata->min_freq = min_freq;
>> + cpudata->nominal_freq = nominal_freq;
>> + cpudata->lowest_nonlinear_freq = lowest_nonlinear_freq;
>> +
>> + policy->driver_data = cpudata;
>> +
>> + update_boost_state();
>> + cpudata->epp_cached = amd_pstate_get_epp(cpudata, value);
>> +
>> + policy->min = policy->cpuinfo.min_freq;
>> + policy->max = policy->cpuinfo.max_freq;
>> +
>> + if (boot_cpu_has(X86_FEATURE_CPPC))
>> + policy->fast_switch_possible = true;
>> +
>> + if (!shared_mem && boot_cpu_has(X86_FEATURE_CPPC)) {
>> + ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value);
>> + if (ret)
>> + return ret;
>> + WRITE_ONCE(cpudata->cppc_req_cached, value);
>> +
>> + ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, &value);
>> + if (ret)
>> + return ret;
>> + WRITE_ONCE(cpudata->cppc_cap1_cached, value);
>> + }
>> + amd_pstate_boost_init(cpudata);
>> +
>> + return 0;
>> +
>> +free_cpudata1:
>> + kfree(cpudata);
>> + return ret;
>> +}
>> +
>> +static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy)
>> +{
>> + int ret;
>> +
>> + ret = __amd_pstate_cpu_init(policy);
>> + if (ret)
>> + return ret;
>> + /*
>> + * Set the policy to powersave to provide a valid fallback value in case
>> + * the default cpufreq governor is neither powersave nor performance.
>> + */
>> + policy->policy = CPUFREQ_POLICY_POWERSAVE;
>> +
>> + return 0;
>> +}
>> +
>> +static int amd_pstate_epp_cpu_exit(struct cpufreq_policy *policy)
>> +{
>> + pr_debug("amd-pstate: CPU %d exiting\n", policy->cpu);
>
> Drop the "amd-pstate:", this file has pr_fmt.
>
>> + policy->fast_switch_possible = false;
>> + return 0;
>> +}
>> +
>> +static void amd_pstate_update_max_freq(unsigned int cpu)
>> +{
>> + struct cpufreq_policy *policy = policy = cpufreq_cpu_get(cpu);
>> +
>> + if (!policy)
>> + return;
>> +
>> + refresh_frequency_limits(policy);
>> + cpufreq_cpu_put(policy);
>> +}
>> +
>> +static void amd_pstate_epp_update_limits(unsigned int cpu)
>> +{
>> + mutex_lock(&amd_pstate_driver_lock);
>> + update_boost_state();
>> + if (global_params.cppc_boost_disabled) {
>> + for_each_possible_cpu(cpu)
>> + amd_pstate_update_max_freq(cpu);
>> + } else {
>> + cpufreq_update_policy(cpu);
>> + }
>> + mutex_unlock(&amd_pstate_driver_lock);
>> +}
>> +
>> +static int cppc_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
>> +
>> +static inline void amd_pstate_boost_up(struct amd_cpudata *cpudata)
>> +{
>> + u64 hwp_req = READ_ONCE(cpudata->cppc_req_cached);
>> + u64 hwp_cap = READ_ONCE(cpudata->cppc_cap1_cached);
>> + u32 max_limit = (hwp_req & 0xff);
>> + u32 min_limit = (hwp_req & 0xff00) >> 8;
>> + u32 boost_level1;
>> +
>> + /* If max and min are equal or already at max, nothing to boost */
>> + if (max_limit == min_limit)
>> + return;
>> +
>> + /* Set boost max and min to initial value */
>> + if (!cpudata->cppc_boost_min)
>> + cpudata->cppc_boost_min = min_limit;
>> +
>> + boost_level1 = ((AMD_CPPC_NOMINAL_PERF(hwp_cap) + min_limit) >> 1);
>> +
>> + if (cpudata->cppc_boost_min < boost_level1)
>> + cpudata->cppc_boost_min = boost_level1;
>> + else if (cpudata->cppc_boost_min < AMD_CPPC_NOMINAL_PERF(hwp_cap))
>> + cpudata->cppc_boost_min = AMD_CPPC_NOMINAL_PERF(hwp_cap);
>> + else if (cpudata->cppc_boost_min == AMD_CPPC_NOMINAL_PERF(hwp_cap))
>> + cpudata->cppc_boost_min = max_limit;
>> + else
>> + return;
>> +
>> + hwp_req &= ~AMD_CPPC_MIN_PERF(~0L);
>> + hwp_req |= AMD_CPPC_MIN_PERF(cpudata->cppc_boost_min);
>> + wrmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, hwp_req);
>> + cpudata->last_update = cpudata->sample.time;
>> +}
>> +
>> +static inline void amd_pstate_boost_down(struct amd_cpudata *cpudata)
>> +{
>> + bool expired;
>> +
>> + if (cpudata->cppc_boost_min) {
>> + expired = time_after64(cpudata->sample.time, cpudata->last_update +
>> + cppc_boost_hold_time_ns);
>> +
>> + if (expired) {
>> + wrmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ,
>> + cpudata->cppc_req_cached);
>> + cpudata->cppc_boost_min = 0;
>> + }
>> + }
>> +
>> + cpudata->last_update = cpudata->sample.time;
>> +}
>> +
>> +static inline void amd_pstate_boost_update_util(struct amd_cpudata *cpudata,
>> + u64 time)
>> +{
>> + cpudata->sample.time = time;
>> + if (smp_processor_id() != cpudata->cpu)
>> + return;
>> +
>> + if (cpudata->sched_flags & SCHED_CPUFREQ_IOWAIT) {
>> + bool do_io = false;
>> +
>> + cpudata->sched_flags = 0;
>> + /*
>> + * Set iowait_boost flag and update time. Since IO WAIT flag
>> + * is set all the time, we can't just conclude that there is
>> + * some IO bound activity is scheduled on this CPU with just
>> + * one occurrence. If we receive at least two in two
>> + * consecutive ticks, then we treat as boost candidate.
>> + * This is leveraged from Intel Pstate driver.
>> + */
>> + if (time_before64(time, cpudata->last_io_update + 2 * TICK_NSEC))
>> + do_io = true;
>> +
>> + cpudata->last_io_update = time;
>> +
>> + if (do_io)
>> + amd_pstate_boost_up(cpudata);
>> +
>> + } else {
>> + amd_pstate_boost_down(cpudata);
>> + }
>> +}
>> +
>> +static inline void amd_pstate_cppc_update_hook(struct update_util_data *data,
>> + u64 time, unsigned int flags)
>> +{
>> + struct amd_cpudata *cpudata = container_of(data,
>> + struct amd_cpudata, update_util);
>> +
>> + cpudata->sched_flags |= flags;
>> +
>> + if (smp_processor_id() == cpudata->cpu)
>> + amd_pstate_boost_update_util(cpudata, time);
>> +}
>> +
>> +static void amd_pstate_clear_update_util_hook(unsigned int cpu)
>> +{
>> + struct amd_cpudata *cpudata = all_cpu_data[cpu];
>> +
>> + if (!cpudata->update_util_set)
>> + return;
>> +
>> + cpufreq_remove_update_util_hook(cpu);
>> + cpudata->update_util_set = false;
>> + synchronize_rcu();
>> +}
>> +
>> +static void amd_pstate_set_update_util_hook(unsigned int cpu_num)
>> +{
>> + struct amd_cpudata *cpudata = all_cpu_data[cpu_num];
>> +
>> + if (!cppc_boost) {
>> + if (cpudata->update_util_set)
>> + amd_pstate_clear_update_util_hook(cpudata->cpu);
>> + return;
>> + }
>> +
>> + if (cpudata->update_util_set)
>> + return;
>> +
>> + cpudata->sample.time = 0;
>> + cpufreq_add_update_util_hook(cpu_num, &cpudata->update_util,
>> + amd_pstate_cppc_update_hook);
>> + cpudata->update_util_set = true;
>> +}
>> +
>> +static void amd_pstate_epp_init(unsigned int cpu)
>> +{
>> + struct amd_cpudata *cpudata = all_cpu_data[cpu];
>> + u32 max_perf, min_perf;
>> + u64 value;
>> + s16 epp;
>> + int ret;
>> +
>> + max_perf = READ_ONCE(cpudata->highest_perf);
>> + min_perf = READ_ONCE(cpudata->lowest_perf);
>> +
>> + value = READ_ONCE(cpudata->cppc_req_cached);
>> +
>> + if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE)
>> + min_perf = max_perf;
>> +
>> + /* Initial min/max values for CPPC Performance Controls Register */
>> + value &= ~AMD_CPPC_MIN_PERF(~0L);
>> + value |= AMD_CPPC_MIN_PERF(min_perf);
>> +
>> + value &= ~AMD_CPPC_MAX_PERF(~0L);
>> + value |= AMD_CPPC_MAX_PERF(max_perf);
>> +
>> + /* CPPC EPP feature require to set zero to the desire perf bit */
>> + value &= ~AMD_CPPC_DES_PERF(~0L);
>> + value |= AMD_CPPC_DES_PERF(0);
>> +
>> + if (cpudata->epp_policy == cpudata->policy)
>> + goto skip_epp;
>> +
>> + cpudata->epp_policy = cpudata->policy;
>> +
>> + if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) {
>> + epp = amd_pstate_get_epp(cpudata, value);
>> + cpudata->epp_powersave = epp;
>> + if (epp < 0)
>> + goto skip_epp;
>> + /* force the epp value to be zero for performance policy */
>> + epp = 0;
>> + } else {
>> + if (cpudata->epp_powersave < 0)
>> + goto skip_epp;
>> + /* Get BIOS pre-defined epp value */
>> + epp = amd_pstate_get_epp(cpudata, value);
>> + if (epp)
>> + goto skip_epp;
>> + epp = cpudata->epp_powersave;
>> + }
>> + /* Set initial EPP value */
>> + if (boot_cpu_has(X86_FEATURE_CPPC)) {
>> + value &= ~GENMASK_ULL(31, 24);
>> + value |= (u64)epp << 24;
>> + }
>> +
>> +skip_epp:
>> + WRITE_ONCE(cpudata->cppc_req_cached, value);
>> + ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
>> + if (!ret)
>> + cpudata->epp_cached = epp;
>> +}
>> +
>> +static void amd_pstate_set_max_limits(struct amd_cpudata *cpudata)
>> +{
>> + u64 hwp_cap = READ_ONCE(cpudata->cppc_cap1_cached);
>> + u64 hwp_req = READ_ONCE(cpudata->cppc_req_cached);
>> + u32 max_limit = (hwp_cap >> 24) & 0xff;
>> +
>> + hwp_req &= ~AMD_CPPC_MIN_PERF(~0L);
>> + hwp_req |= AMD_CPPC_MIN_PERF(max_limit);
>> + wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, hwp_req);
>> +}
>> +
>> +static int amd_pstate_epp_set_policy(struct cpufreq_policy *policy)
>> +{
>> + struct amd_cpudata *cpudata;
>> +
>> + if (!policy->cpuinfo.max_freq)
>> + return -ENODEV;
>> +
>> + pr_debug("set_policy: cpuinfo.max %u policy->max %u\n",
>> + policy->cpuinfo.max_freq, policy->max);
>> +
>> + cpudata = all_cpu_data[policy->cpu];
>> + cpudata->policy = policy->policy;
>> +
>> + if (boot_cpu_has(X86_FEATURE_CPPC)) {
>> + mutex_lock(&amd_pstate_limits_lock);
>> +
>> + if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) {
>> + amd_pstate_clear_update_util_hook(policy->cpu);
>> + amd_pstate_set_max_limits(cpudata);
>> + } else {
>> + amd_pstate_set_update_util_hook(policy->cpu);
>> + }
>> +
>> + if (boot_cpu_has(X86_FEATURE_CPPC))
>> + amd_pstate_epp_init(policy->cpu);
>> +
>> + mutex_unlock(&amd_pstate_limits_lock);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static void amd_pstate_verify_cpu_policy(struct amd_cpudata *cpudata,
>> + struct cpufreq_policy_data *policy)
>> +{
>> + update_boost_state();
>> + cpufreq_verify_within_cpu_limits(policy);
>> +}
>> +
>> +static int amd_pstate_epp_verify_policy(struct cpufreq_policy_data *policy)
>> +{
>> + amd_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy);
>> + pr_debug("policy_max =%d, policy_min=%d\n", policy->max, policy->min);
>> + return 0;
>> +}
>> +
>> static struct cpufreq_driver amd_pstate_driver = {
>> .flags = CPUFREQ_CONST_LOOPS | CPUFREQ_NEED_UPDATE_LIMITS,
>> .verify = amd_pstate_verify,
>> @@ -607,8 +1222,20 @@ static struct cpufreq_driver amd_pstate_driver = {
>> .attr = amd_pstate_attr,
>> };
>> +static struct cpufreq_driver amd_pstate_epp_driver = {
>> + .flags = CPUFREQ_CONST_LOOPS,
>> + .verify = amd_pstate_epp_verify_policy,
>> + .setpolicy = amd_pstate_epp_set_policy,
>> + .init = amd_pstate_epp_cpu_init,
>> + .exit = amd_pstate_epp_cpu_exit,
>> + .update_limits = amd_pstate_epp_update_limits,
>> + .name = "amd_pstate_epp",
>> + .attr = amd_pstate_epp_attr,
>> +};
>> +
>> static int __init amd_pstate_init(void)
>> {
>> + static struct amd_cpudata **cpudata;
>> int ret;
>> if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
>> @@ -623,10 +1250,18 @@ static int __init amd_pstate_init(void)
>> if (cpufreq_get_current_driver())
>> return -EEXIST;
>> + if (!epp_off) {
>> + WRITE_ONCE(cppc_active, 1);
>> + if (!default_pstate_driver)
>> + default_pstate_driver = &amd_pstate_epp_driver;
>> + }
>> + pr_info("AMD CPPC loading with %s driver instance.\n", default_pstate_driver->name);
>
> This is pretty noisy, do we really need it on every boot if we can easily check it from sysfs?
>
>> +
>> /* capability check */
>> if (boot_cpu_has(X86_FEATURE_CPPC)) {
>> + if (!cppc_active)
>> + default_pstate_driver->adjust_perf = amd_pstate_adjust_perf;
>> pr_debug("AMD CPPC MSR based functionality is supported\n");
>> - amd_pstate_driver.adjust_perf = amd_pstate_adjust_perf;
>> } else if (shared_mem) {
>> static_call_update(amd_pstate_enable, cppc_enable);
>> static_call_update(amd_pstate_init_perf, cppc_init_perf);
>> @@ -636,6 +1271,10 @@ static int __init amd_pstate_init(void)
>> return -ENODEV;
>> }
>> + cpudata = vzalloc(array_size(sizeof(void *), num_possible_cpus()));
>> + if (!cpudata)
>> + return -ENOMEM;
>> + WRITE_ONCE(all_cpu_data, cpudata);
>> /* enable amd pstate feature */
>> ret = amd_pstate_enable(true);
>> if (ret) {
>> @@ -643,9 +1282,9 @@ static int __init amd_pstate_init(void)
>> return ret;
>> }
>> - ret = cpufreq_register_driver(&amd_pstate_driver);
>> + ret = cpufreq_register_driver(default_pstate_driver);
>> if (ret)
>> - pr_err("failed to register amd_pstate_driver with return %d\n",
>> + pr_err("failed to register amd pstate driver with return %d\n",
>> ret);
>> return ret;
>> @@ -657,6 +1296,15 @@ static int __init amd_pstate_param(char *str)
>> if (!str)
>> return -EINVAL;
>> + if (!strcmp(str, "disable"))
>> + disable_pstate_load = 1;
>> + else if (!strcmp(str, "active")) {
>> + default_pstate_driver = &amd_pstate_epp_driver;
>> + } else if (!strcmp(str, "passive")) {
>> + epp_off = 1;
>> + default_pstate_driver = &amd_pstate_driver;
>> + }
>> +
>> /* enable shared memory type CPPC ,if you processor has no MSR, you have to add this
>> * to your grub to make cppc driver loaded successfully.
>> */
>> diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h
>> index 1c4b8659f171..7e6e8cab97b3 100644
>> --- a/include/linux/amd-pstate.h
>> +++ b/include/linux/amd-pstate.h
>> @@ -25,6 +25,7 @@ struct amd_aperf_mperf {
>> u64 aperf;
>> u64 mperf;
>> u64 tsc;
>> + u64 time;
>> };
>> /**
>> @@ -47,6 +48,18 @@ struct amd_aperf_mperf {
>> * @prev: Last Aperf/Mperf/tsc count value read from register
>> * @freq: current cpu frequency value
>> * @boost_supported: check whether the Processor or SBIOS supports boost mode
>> + * @epp_powersave: Last saved CPPC energy performance preference
>> + when policy switched to performance
>> + * @epp_policy: Last saved policy used to set energy-performance preference
>> + * @epp_cached: Cached CPPC energy-performance preference value
>> + * @policy: Cpufreq policy value
>> + * @sched_flags: Store scheduler flags for possible cross CPU update
>> + * @update_util_set: CPUFreq utility callback is set
>> + * @last_update: Time stamp of the last performance state update
>> + * @cppc_boost_min: Last CPPC boosted min performance state
>> + * @cppc_cap1_cached: Cached value of the last CPPC Capabilities MSR
>> + * @update_util: Cpufreq utility callback information
>> + * @sample: the stored performance sample
>> *
>> * The amd_cpudata is key private data for each CPU thread in AMD P-State, and
>> * represents all the attributes and goals that AMD P-State requests at runtime.
>> @@ -72,6 +85,74 @@ struct amd_cpudata {
>> u64 freq;
>> bool boost_supported;
>> +
>> + /* EPP feature related attributes*/
>> + s16 epp_powersave;
>> + s16 epp_policy;
>> + s16 epp_cached;
>> + u32 policy;
>> + u32 sched_flags;
>> + bool update_util_set;
>> + u64 last_update;
>> + u64 last_io_update;
>> + u32 cppc_boost_min;
>> + u64 cppc_cap1_cached;
>> + struct update_util_data update_util;
>> + struct amd_aperf_mperf sample;
>> +};
>> +
>> +/**
>> + * struct amd_pstate_params - global parameters for the performance control
>> + * @ cppc_boost_disabled wheher the core performance boost disabled
>> + */
>> +struct amd_pstate_params {
>> + bool cppc_boost_disabled;
>> +};
>> +
>> +#define AMD_CPPC_EPP_PERFORMANCE 0x00
>> +#define AMD_CPPC_EPP_BALANCE_PERFORMANCE 0x80
>> +#define AMD_CPPC_EPP_BALANCE_POWERSAVE 0xBF
>> +#define AMD_CPPC_EPP_POWERSAVE 0xFF
>> +
>> +/*
>> + * AMD Energy Preference Performance (EPP)
>> + * The EPP is used in the CCLK DPM controller to drive
>> + * the frequency that a core is going to operate during
>> + * short periods of activity. EPP values will be utilized for
>> + * different OS profiles (balanced, performance, power savings)
>> + * display strings corresponding to EPP index in the
>> + * energy_perf_strings[]
>> + * index String
>> + *-------------------------------------
>> + * 0 default
>> + * 1 performance
>> + * 2 balance_performance
>> + * 3 balance_power
>> + * 4 power
>> + */
>> +enum energy_perf_value_index {
>> + EPP_INDEX_DEFAULT = 0,
>> + EPP_INDEX_PERFORMANCE,
>> + EPP_INDEX_BALANCE_PERFORMANCE,
>> + EPP_INDEX_BALANCE_POWERSAVE,
>> + EPP_INDEX_POWERSAVE,
>> +};
>> +
>> +static const char * const energy_perf_strings[] = {
>> + [EPP_INDEX_DEFAULT] = "default",
>> + [EPP_INDEX_PERFORMANCE] = "performance",
>> + [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance",
>> + [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power",
>> + [EPP_INDEX_POWERSAVE] = "power",
>> + NULL
>> +};
>> +
>> +static unsigned int epp_values[] = {
>> + [EPP_INDEX_DEFAULT] = 0,
>> + [EPP_INDEX_PERFORMANCE] = AMD_CPPC_EPP_PERFORMANCE,
>> + [EPP_INDEX_BALANCE_PERFORMANCE] = AMD_CPPC_EPP_BALANCE_PERFORMANCE,
>> + [EPP_INDEX_BALANCE_POWERSAVE] = AMD_CPPC_EPP_BALANCE_POWERSAVE,
>> + [EPP_INDEX_POWERSAVE] = AMD_CPPC_EPP_POWERSAVE,
>> };
>> #endif /* _LINUX_AMD_PSTATE_H */
>
^ permalink raw reply [flat|nested] 35+ messages in thread* RE: [PATCH v3 4/8] cpufreq: amd_pstate: add AMD Pstate EPP support for the MSR based processors
2022-11-10 15:59 ` Nathan Fontenot
@ 2022-11-10 16:22 ` Yuan, Perry
0 siblings, 0 replies; 35+ messages in thread
From: Yuan, Perry @ 2022-11-10 16:22 UTC (permalink / raw)
To: Fontenot, Nathan, Limonciello, Mario, rafael.j.wysocki@intel.com,
Huang, Ray, viresh.kumar@linaro.org
Cc: Sharma, Deepak, Deucher, Alexander, Huang, Shimmer, Du, Xiaojian,
Meng, Li (Jassmine), linux-pm@vger.kernel.org,
linux-kernel@vger.kernel.org
[AMD Official Use Only - General]
Hi Nathan.
> -----Original Message-----
> From: Fontenot, Nathan <Nathan.Fontenot@amd.com>
> Sent: Friday, November 11, 2022 12:00 AM
> To: Limonciello, Mario <Mario.Limonciello@amd.com>; Yuan, Perry
> <Perry.Yuan@amd.com>; rafael.j.wysocki@intel.com; Huang, Ray
> <Ray.Huang@amd.com>; viresh.kumar@linaro.org
> Cc: Sharma, Deepak <Deepak.Sharma@amd.com>; Deucher, Alexander
> <Alexander.Deucher@amd.com>; Huang, Shimmer
> <Shimmer.Huang@amd.com>; Du, Xiaojian <Xiaojian.Du@amd.com>; Meng,
> Li (Jassmine) <Li.Meng@amd.com>; linux-pm@vger.kernel.org; linux-
> kernel@vger.kernel.org
> Subject: Re: [PATCH v3 4/8] cpufreq: amd_pstate: add AMD Pstate EPP
> support for the MSR based processors
>
>
>
> On 11/7/22 14:32, Limonciello, Mario wrote:
> > On 11/7/2022 11:57, Perry Yuan wrote:
> >> Add EPP driver support for those AMD CPUs which has full MSR feature
> >> enabled, The EPP is used in the DPM controller to drive the frequency
> >> that a core is going to operate during short periods of activity.
> >
> > To avoid the run on sentence, here is a different wording proposal.
> >
> > Add EPP driver support for AMD SoCs which support a dedicated MSR for
> CPPC. EPP is used by the DPM controller to configure the frequency that a
> core operates at during short periods of activity.
> >
> >>
> >> EPP values will be utilized for different OS profiles (balanced,
> >> performance, power savings). cppc performance can be controlled by
> >> the user space interface sys attributes for min and max frequency
> >> limits, when pstate driver is working under power save policy.
> >>
> >> EPP scale is 0 - 255, 0 is the max performance and 255 is min level.
> >> balance_performance (0x80) can provide best balance performance and
> >> watt for most of system, meanwhile user can choose performance policy
> on needs.
> >
> > As a user reading this message it is confusing that there are values and then
> there are strings, but you don't know the linkage between the two. My
> proposal for rewording this:
> >
> > The SoC EPP targets are configured on a scale from 0 to 255 where 0
> represents maximum performance and 255 represents maximum efficiency.
> >
> > The amd-pstate driver exports profile string names to userspace that are
> tied to specific EPP values.
> >
> > The balance_performance string (0x80) provides the best balance for
> efficiency versus power on most systems, but users can choose other strings
> to meet their needs as well.
> >
> >>
> >> $ cat
> >>
> /sys/devices/system/cpu/cpufreq/policy0/energy_performance_available_
> >> preferences default performance balance_performance balance_power
> >> power
> >>
> >> $ cat
> >>
> /sys/devices/system/cpu/cpufreq/policy0/energy_performance_preferenc
> e
> >> balance_performance
> >>
> >> Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
> >> ---
> >> drivers/cpufreq/amd-pstate.c | 658
> >> ++++++++++++++++++++++++++++++++++-
> >> include/linux/amd-pstate.h | 81 +++++
> >> 2 files changed, 734 insertions(+), 5 deletions(-)
> >>
> >> diff --git a/drivers/cpufreq/amd-pstate.c
> >> b/drivers/cpufreq/amd-pstate.c index 14906431dc15..eb82bc6a7f66
> >> 100644
> >> --- a/drivers/cpufreq/amd-pstate.c
> >> +++ b/drivers/cpufreq/amd-pstate.c
> >> @@ -60,8 +60,136 @@
> >> * module parameter to be able to enable it manually for debugging.
> >> */
> >> static bool shared_mem __read_mostly;
> >> +static int cppc_active __read_mostly; static int disable_pstate_load
> >> +__initdata; static int epp_off __initdata;
> >> -static struct cpufreq_driver amd_pstate_driver;
> >> +static struct cpufreq_driver *default_pstate_driver; static struct
> >> +amd_cpudata **all_cpu_data;
> >> +
> >> +static struct amd_pstate_params global_params;
> >> +
> >> +static DEFINE_MUTEX(amd_pstate_limits_lock);
> >> +static DEFINE_MUTEX(amd_pstate_driver_lock);
> >> +
> >> +static bool cppc_boost __read_mostly; struct kobject
> >> +*amd_pstate_kobj;
> >> +
> >> +#ifdef CONFIG_ACPI_CPPC_LIB
> >> +static s16 amd_pstate_get_epp(struct amd_cpudata *cpudata, u64
> >> +cppc_req_cached) {
> >> + s16 epp;
> >> + struct cppc_perf_caps perf_caps;
> >> + int ret;
> >> +
> >> + if (boot_cpu_has(X86_FEATURE_CPPC)) {
> >> + if (!cppc_req_cached) {
> >> + epp = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ,
> >> + &cppc_req_cached);
> >> + if (epp)
> >> + return epp;
> >> + }
> >> + epp = (cppc_req_cached >> 24) & 0xFF;
> >> + } else {
> >> + ret = cppc_get_epp_caps(cpudata->cpu, &perf_caps);
> >> + if (ret < 0) {
> >> + pr_debug("Could not retrieve energy perf value (%d)\n",
> >> +ret);
> >> + return -EIO;
> >> + }
> >> + epp = (s16) perf_caps.energy_perf;
> >> + }
> >> +
> >> + return epp;
> >> +}
> >> +#endif
> >> +
> >> +static int amd_pstate_get_energy_pref_index(struct amd_cpudata
> >> +*cpudata, int *raw_epp) {
> >> + s16 epp;
> >> + int index = -EINVAL;
> >> +
> >> + *raw_epp = 0;
> >> + epp = amd_pstate_get_epp(cpudata, 0);
> >> + if (epp < 0)
> >> + return epp;
> >> +
> >> + switch (epp) {
> >> + case AMD_CPPC_EPP_PERFORMANCE:
> >> + index = EPP_INDEX_PERFORMANCE;
> >> + break;
> >> + case AMD_CPPC_EPP_BALANCE_PERFORMANCE:
> >> + index = EPP_INDEX_BALANCE_PERFORMANCE;
> >> + break;
> >> + case AMD_CPPC_EPP_BALANCE_POWERSAVE:
> >> + index = EPP_INDEX_BALANCE_POWERSAVE;
> >> + break;
> >> + case AMD_CPPC_EPP_POWERSAVE:
> >> + index = EPP_INDEX_POWERSAVE;
> >> + break;
> >> + default:
> >> + *raw_epp = epp;
> >> + index = 0;
> >> + }
> >> +
> >> + return index;
> >> +}
> >> +
> >> +#ifdef CONFIG_ACPI_CPPC_LIB
> >> +static int amd_pstate_set_epp(struct amd_cpudata *cpudata, u32 epp)
> >> +{
> >> + int ret;
> >> + struct cppc_perf_ctrls perf_ctrls;
> >> +
> >> + if (boot_cpu_has(X86_FEATURE_CPPC)) {
> >> + u64 value = READ_ONCE(cpudata->cppc_req_cached);
> >> +
> >> + value &= ~GENMASK_ULL(31, 24);
> >> + value |= (u64)epp << 24;
> >> + WRITE_ONCE(cpudata->cppc_req_cached, value);
> >> +
> >> + ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
> >> + if (!ret)
> >> + cpudata->epp_cached = epp;
> >> + } else {
> >> + perf_ctrls.energy_perf = epp;
> >> + ret = cppc_set_epp_perf(cpudata->cpu, &perf_ctrls);
> >> + if (ret) {
> >> + pr_debug("failed to set energy perf value (%d)\n", ret);
> >> + return ret;
> >> + }
> >> + cpudata->epp_cached = epp;
> >> + }
> >> +
> >> + return ret;
> >> +}
> >> +
> >> +static int amd_pstate_set_energy_pref_index(struct amd_cpudata
> >> +*cpudata,
> >> + int pref_index, bool use_raw,
> >> + u32 raw_epp) {
> >> + int epp = -EINVAL;
> >> + int ret;
> >> +
> >> + if (!pref_index) {
> >> + pr_debug("EPP pref_index is invalid\n");
> >> + return -EINVAL;
> >> + }
> >> +
> >> + if (use_raw)
> >> + epp = raw_epp;
> >> + else if (epp == -EINVAL)
> >> + epp = epp_values[pref_index];
> >> +
> >> + if (epp > 0 && cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) {
> >> + pr_debug("EPP cannot be set under performance policy\n");
> >> + return -EBUSY;
> >> + }
> >> +
> >> + ret = amd_pstate_set_epp(cpudata, epp);
> >> +
> >> + return ret;
> >> +}
> >> +#endif
> >> static inline int pstate_enable(bool enable)
> >> {
> >> @@ -71,11 +199,25 @@ static inline int pstate_enable(bool enable)
> >> static int cppc_enable(bool enable)
> >> {
> >> int cpu, ret = 0;
> >> + struct cppc_perf_ctrls perf_ctrls;
> >> for_each_present_cpu(cpu) {
> >> ret = cppc_set_enable(cpu, enable);
> >> if (ret)
> >> return ret;
> >> +
> >> + /* Enable autonomous mode for EPP */
> >> + if (!cppc_active) {
> >> + ret = cppc_set_auto_epp(cpu, enable);
> >> + if (ret)
> >> + return ret;
> >> +
> >> + /* Set desired perf as zero to allow EPP firmware
> >> +control */
> >> + perf_ctrls.desired_perf = 0;
> >> + ret = cppc_set_perf(cpu, &perf_ctrls);
> >> + if (ret)
> >> + return ret;
> >> + }
> >> }
> >> return ret;
> >> @@ -418,7 +560,7 @@ static void amd_pstate_boost_init(struct
> >> amd_cpudata *cpudata)
> >> return;
> >> cpudata->boost_supported = true;
> >> - amd_pstate_driver.boost_enabled = true;
> >> + default_pstate_driver->boost_enabled = true;
> >> }
> >> static int amd_pstate_cpu_init(struct cpufreq_policy *policy) @@
> >> -582,10 +724,74 @@ static ssize_t show_amd_pstate_highest_perf(struct
> >> cpufreq_policy *policy,
> >> return sprintf(&buf[0], "%u\n", perf);
> >> }
> >> +static ssize_t show_energy_performance_available_preferences(
> >> + struct cpufreq_policy *policy, char *buf) {
> >> + int i = 0;
> >> + int ret = 0;
> >> +
> >> + while (energy_perf_strings[i] != NULL)
> >> + ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
> >> +
> >> + ret += sprintf(&buf[ret], "\n");
> >> +
> >> + return ret;
> >> +}
> >> +
> >> +static ssize_t store_energy_performance_preference(
> >> + struct cpufreq_policy *policy, const char *buf, size_t
> >> +count) {
> >> + struct amd_cpudata *cpudata = policy->driver_data;
> >> + char str_preference[21];
> >> + bool raw = false;
> >> + ssize_t ret;
> >> + u32 epp = 0;
> >> +
> >> + ret = sscanf(buf, "%20s", str_preference);
> >> + if (ret != 1)
> >> + return -EINVAL;
> >> +
> >> + ret = match_string(energy_perf_strings, -1, str_preference);
> >> + if (ret < 0) {
> >> + ret = kstrtouint(buf, 10, &epp);
> >> + if (ret)
> >> + return ret;
> >> +
> >> + if ((epp > 255) || (epp < 0))
> >> + return -EINVAL;
> >> +
> >> + raw = true;
> >> + }
> >
> > What's the reason for supporting putting the raw number in here for stuff
> "in between"? I think this is going to pretty confusing to userspace that you
> can use string values or integer values. It also means that if userspace writes
> an integer with a mapping to string and tries to read it back they'll get the
> string rather than the integer!
> >
> > I can understand using the raw values for internal characterization and
> development to possibly introduce a new mapping string, but I don't think
> that makes sense in the kernel.
> >
>
> This is really doing what Intel does for handling EPP settings. Yes, writing a
> value and getting back a string could be a bit confusing bit it is already done
> from the Intel side. I think keeping EPP value setting common would be a
> good thing if we can do it.
>
> I don't think we should remove the ability to set raw values, we're allowed a
> range of 0 - 255 for the EPP setting. Why we then limit ourselves to only 4 or
> so values?
>
> -Nathan
The raw values are userd for tunning , we have another utility to fine tune the performance/power under development.
So from the customer perspective, we do not need to keep the raw epp set any more in my opinion.
And Mario also has strong justification for the change.
Perry.
>
> >> +
> >> + mutex_lock(&amd_pstate_limits_lock);
> >> + ret = amd_pstate_set_energy_pref_index(cpudata, ret, raw, epp);
> >> + mutex_unlock(&amd_pstate_limits_lock);
> >> +
> >> + return ret ?: count;
> >> +}
> >> +
> >> +static ssize_t show_energy_performance_preference(
> >> + struct cpufreq_policy *policy, char *buf) {
> >> + struct amd_cpudata *cpudata = policy->driver_data;
> >> + int preference, raw_epp;
> >> +
> >> + preference = amd_pstate_get_energy_pref_index(cpudata,
> >> +&raw_epp);
> >> + if (preference < 0)
> >> + return preference;
> >> +
> >> + if (raw_epp)
> >> + return sprintf(buf, "%d\n", raw_epp);
> >> + else
> >> + return sprintf(buf, "%s\n",
> >> +energy_perf_strings[preference]); }
> >> +
> >> cpufreq_freq_attr_ro(amd_pstate_max_freq);
> >> cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq);
> >> cpufreq_freq_attr_ro(amd_pstate_highest_perf);
> >> +cpufreq_freq_attr_rw(energy_performance_preference);
> >> +cpufreq_freq_attr_ro(energy_performance_available_preferences);
> >> static struct freq_attr *amd_pstate_attr[] = {
> >> &amd_pstate_max_freq,
> >> @@ -594,6 +800,415 @@ static struct freq_attr *amd_pstate_attr[] = {
> >> NULL,
> >> };
> >> +static struct freq_attr *amd_pstate_epp_attr[] = {
> >> + &amd_pstate_max_freq,
> >> + &amd_pstate_lowest_nonlinear_freq,
> >> + &amd_pstate_highest_perf,
> >> + &energy_performance_preference,
> >> + &energy_performance_available_preferences,
> >> + NULL,
> >> +};
> >> +
> >> +static inline void update_boost_state(void) {
> >> + u64 misc_en;
> >> + struct amd_cpudata *cpudata;
> >> +
> >> + cpudata = all_cpu_data[0];
> >> + rdmsrl(MSR_K7_HWCR, misc_en);
> >> + global_params.cppc_boost_disabled = misc_en & BIT_ULL(25); }
> >> +
> >> +static int amd_pstate_init_cpu(unsigned int cpunum) {
> >> + struct amd_cpudata *cpudata;
> >> +
> >> + cpudata = all_cpu_data[cpunum];
> >> + if (!cpudata) {
> >> + cpudata = kzalloc(sizeof(*cpudata), GFP_KERNEL);
> >> + if (!cpudata)
> >> + return -ENOMEM;
> >> + WRITE_ONCE(all_cpu_data[cpunum], cpudata);
> >> +
> >> + cpudata->cpu = cpunum;
> >> + }
> >> + cpudata->epp_powersave = -EINVAL;
> >> + cpudata->epp_policy = 0;
> >> + pr_debug("controlling: cpu %d\n", cpunum);
> >> + return 0;
> >> +}
> >> +
> >> +static int __amd_pstate_cpu_init(struct cpufreq_policy *policy) {
> >> + int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq,
> >> +ret;
> >> + struct amd_cpudata *cpudata;
> >> + struct device *dev;
> >> + int rc;
> >> + u64 value;
> >> +
> >> + rc = amd_pstate_init_cpu(policy->cpu);
> >> + if (rc)
> >> + return rc;
> >> +
> >> + cpudata = all_cpu_data[policy->cpu];
> >> +
> >> + dev = get_cpu_device(policy->cpu);
> >> + if (!dev)
> >> + goto free_cpudata1;
> >> +
> >> + rc = amd_pstate_init_perf(cpudata);
> >> + if (rc)
> >> + goto free_cpudata1;
> >> +
> >> + min_freq = amd_get_min_freq(cpudata);
> >> + max_freq = amd_get_max_freq(cpudata);
> >> + nominal_freq = amd_get_nominal_freq(cpudata);
> >> + lowest_nonlinear_freq = amd_get_lowest_nonlinear_freq(cpudata);
> >> + if (min_freq < 0 || max_freq < 0 || min_freq > max_freq) {
> >> + dev_err(dev, "min_freq(%d) or max_freq(%d) value is
> >> +incorrect\n",
> >> + min_freq, max_freq);
> >> + ret = -EINVAL;
> >> + goto free_cpudata1;
> >> + }
> >> +
> >> + policy->min = min_freq;
> >> + policy->max = max_freq;
> >> +
> >> + policy->cpuinfo.min_freq = min_freq;
> >> + policy->cpuinfo.max_freq = max_freq;
> >> + /* It will be updated by governor */
> >> + policy->cur = policy->cpuinfo.min_freq;
> >> +
> >> + /* Initial processor data capability frequencies */
> >> + cpudata->max_freq = max_freq;
> >> + cpudata->min_freq = min_freq;
> >> + cpudata->nominal_freq = nominal_freq;
> >> + cpudata->lowest_nonlinear_freq = lowest_nonlinear_freq;
> >> +
> >> + policy->driver_data = cpudata;
> >> +
> >> + update_boost_state();
> >> + cpudata->epp_cached = amd_pstate_get_epp(cpudata, value);
> >> +
> >> + policy->min = policy->cpuinfo.min_freq;
> >> + policy->max = policy->cpuinfo.max_freq;
> >> +
> >> + if (boot_cpu_has(X86_FEATURE_CPPC))
> >> + policy->fast_switch_possible = true;
> >> +
> >> + if (!shared_mem && boot_cpu_has(X86_FEATURE_CPPC)) {
> >> + ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value);
> >> + if (ret)
> >> + return ret;
> >> + WRITE_ONCE(cpudata->cppc_req_cached, value);
> >> +
> >> + ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1,
> >> +&value);
> >> + if (ret)
> >> + return ret;
> >> + WRITE_ONCE(cpudata->cppc_cap1_cached, value);
> >> + }
> >> + amd_pstate_boost_init(cpudata);
> >> +
> >> + return 0;
> >> +
> >> +free_cpudata1:
> >> + kfree(cpudata);
> >> + return ret;
> >> +}
> >> +
> >> +static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) {
> >> + int ret;
> >> +
> >> + ret = __amd_pstate_cpu_init(policy);
> >> + if (ret)
> >> + return ret;
> >> + /*
> >> + * Set the policy to powersave to provide a valid fallback value
> >> +in case
> >> + * the default cpufreq governor is neither powersave nor performance.
> >> + */
> >> + policy->policy = CPUFREQ_POLICY_POWERSAVE;
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static int amd_pstate_epp_cpu_exit(struct cpufreq_policy *policy) {
> >> + pr_debug("amd-pstate: CPU %d exiting\n", policy->cpu);
> >
> > Drop the "amd-pstate:", this file has pr_fmt.
> >
> >> + policy->fast_switch_possible = false;
> >> + return 0;
> >> +}
> >> +
> >> +static void amd_pstate_update_max_freq(unsigned int cpu) {
> >> + struct cpufreq_policy *policy = policy = cpufreq_cpu_get(cpu);
> >> +
> >> + if (!policy)
> >> + return;
> >> +
> >> + refresh_frequency_limits(policy);
> >> + cpufreq_cpu_put(policy);
> >> +}
> >> +
> >> +static void amd_pstate_epp_update_limits(unsigned int cpu) {
> >> + mutex_lock(&amd_pstate_driver_lock);
> >> + update_boost_state();
> >> + if (global_params.cppc_boost_disabled) {
> >> + for_each_possible_cpu(cpu)
> >> + amd_pstate_update_max_freq(cpu);
> >> + } else {
> >> + cpufreq_update_policy(cpu);
> >> + }
> >> + mutex_unlock(&amd_pstate_driver_lock);
> >> +}
> >> +
> >> +static int cppc_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
> >> +
> >> +static inline void amd_pstate_boost_up(struct amd_cpudata *cpudata)
> >> +{
> >> + u64 hwp_req = READ_ONCE(cpudata->cppc_req_cached);
> >> + u64 hwp_cap = READ_ONCE(cpudata->cppc_cap1_cached);
> >> + u32 max_limit = (hwp_req & 0xff);
> >> + u32 min_limit = (hwp_req & 0xff00) >> 8;
> >> + u32 boost_level1;
> >> +
> >> + /* If max and min are equal or already at max, nothing to boost
> >> +*/
> >> + if (max_limit == min_limit)
> >> + return;
> >> +
> >> + /* Set boost max and min to initial value */
> >> + if (!cpudata->cppc_boost_min)
> >> + cpudata->cppc_boost_min = min_limit;
> >> +
> >> + boost_level1 = ((AMD_CPPC_NOMINAL_PERF(hwp_cap) +
> min_limit) >>
> >> +1);
> >> +
> >> + if (cpudata->cppc_boost_min < boost_level1)
> >> + cpudata->cppc_boost_min = boost_level1;
> >> + else if (cpudata->cppc_boost_min <
> >> +AMD_CPPC_NOMINAL_PERF(hwp_cap))
> >> + cpudata->cppc_boost_min =
> AMD_CPPC_NOMINAL_PERF(hwp_cap);
> >> + else if (cpudata->cppc_boost_min ==
> >> +AMD_CPPC_NOMINAL_PERF(hwp_cap))
> >> + cpudata->cppc_boost_min = max_limit;
> >> + else
> >> + return;
> >> +
> >> + hwp_req &= ~AMD_CPPC_MIN_PERF(~0L);
> >> + hwp_req |= AMD_CPPC_MIN_PERF(cpudata->cppc_boost_min);
> >> + wrmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ,
> hwp_req);
> >> + cpudata->last_update = cpudata->sample.time; }
> >> +
> >> +static inline void amd_pstate_boost_down(struct amd_cpudata
> >> +*cpudata) {
> >> + bool expired;
> >> +
> >> + if (cpudata->cppc_boost_min) {
> >> + expired = time_after64(cpudata->sample.time,
> >> +cpudata->last_update +
> >> + cppc_boost_hold_time_ns);
> >> +
> >> + if (expired) {
> >> + wrmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ,
> >> + cpudata->cppc_req_cached);
> >> + cpudata->cppc_boost_min = 0;
> >> + }
> >> + }
> >> +
> >> + cpudata->last_update = cpudata->sample.time; }
> >> +
> >> +static inline void amd_pstate_boost_update_util(struct amd_cpudata
> >> +*cpudata,
> >> + u64 time) {
> >> + cpudata->sample.time = time;
> >> + if (smp_processor_id() != cpudata->cpu)
> >> + return;
> >> +
> >> + if (cpudata->sched_flags & SCHED_CPUFREQ_IOWAIT) {
> >> + bool do_io = false;
> >> +
> >> + cpudata->sched_flags = 0;
> >> + /*
> >> + * Set iowait_boost flag and update time. Since IO WAIT flag
> >> + * is set all the time, we can't just conclude that there is
> >> + * some IO bound activity is scheduled on this CPU with just
> >> + * one occurrence. If we receive at least two in two
> >> + * consecutive ticks, then we treat as boost candidate.
> >> + * This is leveraged from Intel Pstate driver.
> >> + */
> >> + if (time_before64(time, cpudata->last_io_update + 2 *
> >> +TICK_NSEC))
> >> + do_io = true;
> >> +
> >> + cpudata->last_io_update = time;
> >> +
> >> + if (do_io)
> >> + amd_pstate_boost_up(cpudata);
> >> +
> >> + } else {
> >> + amd_pstate_boost_down(cpudata);
> >> + }
> >> +}
> >> +
> >> +static inline void amd_pstate_cppc_update_hook(struct
> >> +update_util_data *data,
> >> + u64 time, unsigned int flags) {
> >> + struct amd_cpudata *cpudata = container_of(data,
> >> + struct amd_cpudata, update_util);
> >> +
> >> + cpudata->sched_flags |= flags;
> >> +
> >> + if (smp_processor_id() == cpudata->cpu)
> >> + amd_pstate_boost_update_util(cpudata, time); }
> >> +
> >> +static void amd_pstate_clear_update_util_hook(unsigned int cpu) {
> >> + struct amd_cpudata *cpudata = all_cpu_data[cpu];
> >> +
> >> + if (!cpudata->update_util_set)
> >> + return;
> >> +
> >> + cpufreq_remove_update_util_hook(cpu);
> >> + cpudata->update_util_set = false;
> >> + synchronize_rcu();
> >> +}
> >> +
> >> +static void amd_pstate_set_update_util_hook(unsigned int cpu_num) {
> >> + struct amd_cpudata *cpudata = all_cpu_data[cpu_num];
> >> +
> >> + if (!cppc_boost) {
> >> + if (cpudata->update_util_set)
> >> + amd_pstate_clear_update_util_hook(cpudata->cpu);
> >> + return;
> >> + }
> >> +
> >> + if (cpudata->update_util_set)
> >> + return;
> >> +
> >> + cpudata->sample.time = 0;
> >> + cpufreq_add_update_util_hook(cpu_num, &cpudata->update_util,
> >> + amd_pstate_cppc_update_hook);
> >> + cpudata->update_util_set = true; }
> >> +
> >> +static void amd_pstate_epp_init(unsigned int cpu) {
> >> + struct amd_cpudata *cpudata = all_cpu_data[cpu];
> >> + u32 max_perf, min_perf;
> >> + u64 value;
> >> + s16 epp;
> >> + int ret;
> >> +
> >> + max_perf = READ_ONCE(cpudata->highest_perf);
> >> + min_perf = READ_ONCE(cpudata->lowest_perf);
> >> +
> >> + value = READ_ONCE(cpudata->cppc_req_cached);
> >> +
> >> + if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE)
> >> + min_perf = max_perf;
> >> +
> >> + /* Initial min/max values for CPPC Performance Controls Register
> >> +*/
> >> + value &= ~AMD_CPPC_MIN_PERF(~0L);
> >> + value |= AMD_CPPC_MIN_PERF(min_perf);
> >> +
> >> + value &= ~AMD_CPPC_MAX_PERF(~0L);
> >> + value |= AMD_CPPC_MAX_PERF(max_perf);
> >> +
> >> + /* CPPC EPP feature require to set zero to the desire perf bit
> >> +*/
> >> + value &= ~AMD_CPPC_DES_PERF(~0L);
> >> + value |= AMD_CPPC_DES_PERF(0);
> >> +
> >> + if (cpudata->epp_policy == cpudata->policy)
> >> + goto skip_epp;
> >> +
> >> + cpudata->epp_policy = cpudata->policy;
> >> +
> >> + if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) {
> >> + epp = amd_pstate_get_epp(cpudata, value);
> >> + cpudata->epp_powersave = epp;
> >> + if (epp < 0)
> >> + goto skip_epp;
> >> + /* force the epp value to be zero for performance policy */
> >> + epp = 0;
> >> + } else {
> >> + if (cpudata->epp_powersave < 0)
> >> + goto skip_epp;
> >> + /* Get BIOS pre-defined epp value */
> >> + epp = amd_pstate_get_epp(cpudata, value);
> >> + if (epp)
> >> + goto skip_epp;
> >> + epp = cpudata->epp_powersave;
> >> + }
> >> + /* Set initial EPP value */
> >> + if (boot_cpu_has(X86_FEATURE_CPPC)) {
> >> + value &= ~GENMASK_ULL(31, 24);
> >> + value |= (u64)epp << 24;
> >> + }
> >> +
> >> +skip_epp:
> >> + WRITE_ONCE(cpudata->cppc_req_cached, value);
> >> + ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
> >> + if (!ret)
> >> + cpudata->epp_cached = epp;
> >> +}
> >> +
> >> +static void amd_pstate_set_max_limits(struct amd_cpudata *cpudata) {
> >> + u64 hwp_cap = READ_ONCE(cpudata->cppc_cap1_cached);
> >> + u64 hwp_req = READ_ONCE(cpudata->cppc_req_cached);
> >> + u32 max_limit = (hwp_cap >> 24) & 0xff;
> >> +
> >> + hwp_req &= ~AMD_CPPC_MIN_PERF(~0L);
> >> + hwp_req |= AMD_CPPC_MIN_PERF(max_limit);
> >> + wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, hwp_req); }
> >> +
> >> +static int amd_pstate_epp_set_policy(struct cpufreq_policy *policy)
> >> +{
> >> + struct amd_cpudata *cpudata;
> >> +
> >> + if (!policy->cpuinfo.max_freq)
> >> + return -ENODEV;
> >> +
> >> + pr_debug("set_policy: cpuinfo.max %u policy->max %u\n",
> >> + policy->cpuinfo.max_freq, policy->max);
> >> +
> >> + cpudata = all_cpu_data[policy->cpu];
> >> + cpudata->policy = policy->policy;
> >> +
> >> + if (boot_cpu_has(X86_FEATURE_CPPC)) {
> >> + mutex_lock(&amd_pstate_limits_lock);
> >> +
> >> + if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) {
> >> + amd_pstate_clear_update_util_hook(policy->cpu);
> >> + amd_pstate_set_max_limits(cpudata);
> >> + } else {
> >> + amd_pstate_set_update_util_hook(policy->cpu);
> >> + }
> >> +
> >> + if (boot_cpu_has(X86_FEATURE_CPPC))
> >> + amd_pstate_epp_init(policy->cpu);
> >> +
> >> + mutex_unlock(&amd_pstate_limits_lock);
> >> + }
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static void amd_pstate_verify_cpu_policy(struct amd_cpudata
> >> +*cpudata,
> >> + struct cpufreq_policy_data *policy) {
> >> + update_boost_state();
> >> + cpufreq_verify_within_cpu_limits(policy);
> >> +}
> >> +
> >> +static int amd_pstate_epp_verify_policy(struct cpufreq_policy_data
> >> +*policy) {
> >> + amd_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy);
> >> + pr_debug("policy_max =%d, policy_min=%d\n", policy->max,
> >> +policy->min);
> >> + return 0;
> >> +}
> >> +
> >> static struct cpufreq_driver amd_pstate_driver = {
> >> .flags = CPUFREQ_CONST_LOOPS |
> >> CPUFREQ_NEED_UPDATE_LIMITS,
> >> .verify = amd_pstate_verify, @@ -607,8 +1222,20 @@
> >> static struct cpufreq_driver amd_pstate_driver = {
> >> .attr = amd_pstate_attr,
> >> };
> >> +static struct cpufreq_driver amd_pstate_epp_driver = {
> >> + .flags = CPUFREQ_CONST_LOOPS,
> >> + .verify = amd_pstate_epp_verify_policy,
> >> + .setpolicy = amd_pstate_epp_set_policy,
> >> + .init = amd_pstate_epp_cpu_init,
> >> + .exit = amd_pstate_epp_cpu_exit,
> >> + .update_limits = amd_pstate_epp_update_limits,
> >> + .name = "amd_pstate_epp",
> >> + .attr = amd_pstate_epp_attr, };
> >> +
> >> static int __init amd_pstate_init(void)
> >> {
> >> + static struct amd_cpudata **cpudata;
> >> int ret;
> >> if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) @@ -623,10
> >> +1250,18 @@ static int __init amd_pstate_init(void)
> >> if (cpufreq_get_current_driver())
> >> return -EEXIST;
> >> + if (!epp_off) {
> >> + WRITE_ONCE(cppc_active, 1);
> >> + if (!default_pstate_driver)
> >> + default_pstate_driver = &amd_pstate_epp_driver;
> >> + }
> >> + pr_info("AMD CPPC loading with %s driver instance.\n",
> >> +default_pstate_driver->name);
> >
> > This is pretty noisy, do we really need it on every boot if we can easily
> check it from sysfs?
> >
> >> +
> >> /* capability check */
> >> if (boot_cpu_has(X86_FEATURE_CPPC)) {
> >> + if (!cppc_active)
> >> + default_pstate_driver->adjust_perf =
> >> +amd_pstate_adjust_perf;
> >> pr_debug("AMD CPPC MSR based functionality is
> >> supported\n");
> >> - amd_pstate_driver.adjust_perf = amd_pstate_adjust_perf;
> >> } else if (shared_mem) {
> >> static_call_update(amd_pstate_enable, cppc_enable);
> >> static_call_update(amd_pstate_init_perf, cppc_init_perf);
> >> @@ -636,6 +1271,10 @@ static int __init amd_pstate_init(void)
> >> return -ENODEV;
> >> }
> >> + cpudata = vzalloc(array_size(sizeof(void *),
> >> num_possible_cpus()));
> >> + if (!cpudata)
> >> + return -ENOMEM;
> >> + WRITE_ONCE(all_cpu_data, cpudata);
> >> /* enable amd pstate feature */
> >> ret = amd_pstate_enable(true);
> >> if (ret) {
> >> @@ -643,9 +1282,9 @@ static int __init amd_pstate_init(void)
> >> return ret;
> >> }
> >> - ret = cpufreq_register_driver(&amd_pstate_driver);
> >> + ret = cpufreq_register_driver(default_pstate_driver);
> >> if (ret)
> >> - pr_err("failed to register amd_pstate_driver with return
> >> %d\n",
> >> + pr_err("failed to register amd pstate driver with return
> >> +%d\n",
> >> ret);
> >> return ret;
> >> @@ -657,6 +1296,15 @@ static int __init amd_pstate_param(char *str)
> >> if (!str)
> >> return -EINVAL;
> >> + if (!strcmp(str, "disable"))
> >> + disable_pstate_load = 1;
> >> + else if (!strcmp(str, "active")) {
> >> + default_pstate_driver = &amd_pstate_epp_driver;
> >> + } else if (!strcmp(str, "passive")) {
> >> + epp_off = 1;
> >> + default_pstate_driver = &amd_pstate_driver;
> >> + }
> >> +
> >> /* enable shared memory type CPPC ,if you processor has no MSR,
> >> you have to add this
> >> * to your grub to make cppc driver loaded successfully.
> >> */
> >> diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h
> >> index 1c4b8659f171..7e6e8cab97b3 100644
> >> --- a/include/linux/amd-pstate.h
> >> +++ b/include/linux/amd-pstate.h
> >> @@ -25,6 +25,7 @@ struct amd_aperf_mperf {
> >> u64 aperf;
> >> u64 mperf;
> >> u64 tsc;
> >> + u64 time;
> >> };
> >> /**
> >> @@ -47,6 +48,18 @@ struct amd_aperf_mperf {
> >> * @prev: Last Aperf/Mperf/tsc count value read from register
> >> * @freq: current cpu frequency value
> >> * @boost_supported: check whether the Processor or SBIOS supports
> >> boost mode
> >> + * @epp_powersave: Last saved CPPC energy performance preference
> >> + when policy switched to performance
> >> + * @epp_policy: Last saved policy used to set energy-performance
> >> +preference
> >> + * @epp_cached: Cached CPPC energy-performance preference value
> >> + * @policy: Cpufreq policy value
> >> + * @sched_flags: Store scheduler flags for possible cross CPU update
> >> + * @update_util_set: CPUFreq utility callback is set
> >> + * @last_update: Time stamp of the last performance state update
> >> + * @cppc_boost_min: Last CPPC boosted min performance state
> >> + * @cppc_cap1_cached: Cached value of the last CPPC Capabilities MSR
> >> + * @update_util: Cpufreq utility callback information
> >> + * @sample: the stored performance sample
> >> *
> >> * The amd_cpudata is key private data for each CPU thread in AMD
> >> P-State, and
> >> * represents all the attributes and goals that AMD P-State requests at
> runtime.
> >> @@ -72,6 +85,74 @@ struct amd_cpudata {
> >> u64 freq;
> >> bool boost_supported;
> >> +
> >> + /* EPP feature related attributes*/
> >> + s16 epp_powersave;
> >> + s16 epp_policy;
> >> + s16 epp_cached;
> >> + u32 policy;
> >> + u32 sched_flags;
> >> + bool update_util_set;
> >> + u64 last_update;
> >> + u64 last_io_update;
> >> + u32 cppc_boost_min;
> >> + u64 cppc_cap1_cached;
> >> + struct update_util_data update_util;
> >> + struct amd_aperf_mperf sample; };
> >> +
> >> +/**
> >> + * struct amd_pstate_params - global parameters for the performance
> >> +control
> >> + * @ cppc_boost_disabled wheher the core performance boost disabled
> >> +*/ struct amd_pstate_params {
> >> + bool cppc_boost_disabled;
> >> +};
> >> +
> >> +#define AMD_CPPC_EPP_PERFORMANCE 0x00 #define
> >> +AMD_CPPC_EPP_BALANCE_PERFORMANCE 0x80 #define
> >> +AMD_CPPC_EPP_BALANCE_POWERSAVE 0xBF #define
> >> +AMD_CPPC_EPP_POWERSAVE 0xFF
> >> +
> >> +/*
> >> + * AMD Energy Preference Performance (EPP)
> >> + * The EPP is used in the CCLK DPM controller to drive
> >> + * the frequency that a core is going to operate during
> >> + * short periods of activity. EPP values will be utilized for
> >> + * different OS profiles (balanced, performance, power savings)
> >> + * display strings corresponding to EPP index in the
> >> + * energy_perf_strings[]
> >> + * index String
> >> + *-------------------------------------
> >> + * 0 default
> >> + * 1 performance
> >> + * 2 balance_performance
> >> + * 3 balance_power
> >> + * 4 power
> >> + */
> >> +enum energy_perf_value_index {
> >> + EPP_INDEX_DEFAULT = 0,
> >> + EPP_INDEX_PERFORMANCE,
> >> + EPP_INDEX_BALANCE_PERFORMANCE,
> >> + EPP_INDEX_BALANCE_POWERSAVE,
> >> + EPP_INDEX_POWERSAVE,
> >> +};
> >> +
> >> +static const char * const energy_perf_strings[] = {
> >> + [EPP_INDEX_DEFAULT] = "default",
> >> + [EPP_INDEX_PERFORMANCE] = "performance",
> >> + [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance",
> >> + [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power",
> >> + [EPP_INDEX_POWERSAVE] = "power",
> >> + NULL
> >> +};
> >> +
> >> +static unsigned int epp_values[] = {
> >> + [EPP_INDEX_DEFAULT] = 0,
> >> + [EPP_INDEX_PERFORMANCE] = AMD_CPPC_EPP_PERFORMANCE,
> >> + [EPP_INDEX_BALANCE_PERFORMANCE] =
> >> +AMD_CPPC_EPP_BALANCE_PERFORMANCE,
> >> + [EPP_INDEX_BALANCE_POWERSAVE] =
> AMD_CPPC_EPP_BALANCE_POWERSAVE,
> >> + [EPP_INDEX_POWERSAVE] = AMD_CPPC_EPP_POWERSAVE,
> >> };
> >> #endif /* _LINUX_AMD_PSTATE_H */
> >
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v3 5/8] cpufreq: amd_pstate: implement amd pstate cpu online and offline callback
2022-11-07 17:56 [PATCH v3 0/8] Implement AMD Pstate EPP Driver Perry Yuan
` (3 preceding siblings ...)
2022-11-07 17:57 ` [PATCH v3 4/8] cpufreq: amd_pstate: add AMD Pstate EPP support for the MSR based processors Perry Yuan
@ 2022-11-07 17:57 ` Perry Yuan
2022-11-07 18:22 ` Limonciello, Mario
2022-11-07 17:57 ` [PATCH v3 6/8] cpufreq: amd-pstate: implement suspend and resume callbacks Perry Yuan
` (2 subsequent siblings)
7 siblings, 1 reply; 35+ messages in thread
From: Perry Yuan @ 2022-11-07 17:57 UTC (permalink / raw)
To: rafael.j.wysocki, ray.huang, viresh.kumar
Cc: Deepak.Sharma, Mario.Limonciello, Nathan.Fontenot,
Alexander.Deucher, Shimmer.Huang, Xiaojian.Du, Li.Meng, linux-pm,
linux-kernel, Perry Yuan
Adds online and offline driver callback support to allow cpu cores go
offline and help to restore the previous working states when core goes
back online later for EPP driver mode.
Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
---
drivers/cpufreq/amd-pstate.c | 89 ++++++++++++++++++++++++++++++++++++
include/linux/amd-pstate.h | 1 +
2 files changed, 90 insertions(+)
diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
index eb82bc6a7f66..6ce9fca0a128 100644
--- a/drivers/cpufreq/amd-pstate.c
+++ b/drivers/cpufreq/amd-pstate.c
@@ -1195,6 +1195,93 @@ static int amd_pstate_epp_set_policy(struct cpufreq_policy *policy)
return 0;
}
+static void amd_pstate_epp_reenable(struct amd_cpudata *cpudata)
+{
+ struct cppc_perf_ctrls perf_ctrls;
+ u64 value, max_perf;
+ int ret;
+
+ ret = amd_pstate_enable(true);
+ if (ret)
+ pr_err("failed to enable amd pstate during resume, return %d\n", ret);
+
+ value = READ_ONCE(cpudata->cppc_req_cached);
+ max_perf = READ_ONCE(cpudata->highest_perf);
+
+ if (boot_cpu_has(X86_FEATURE_CPPC)) {
+ wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
+ } else {
+ perf_ctrls.max_perf = max_perf;
+ perf_ctrls.energy_perf = AMD_CPPC_ENERGY_PERF_PREF(cpudata->epp_cached);
+ cppc_set_perf(cpudata->cpu, &perf_ctrls);
+ }
+}
+
+static int amd_pstate_epp_cpu_online(struct cpufreq_policy *policy)
+{
+ struct amd_cpudata *cpudata = all_cpu_data[policy->cpu];
+
+ pr_debug("AMD CPU Core %d going online\n", cpudata->cpu);
+
+ if (cppc_active) {
+ amd_pstate_epp_reenable(cpudata);
+ cpudata->suspended = false;
+ }
+
+ return 0;
+}
+
+static void amd_pstate_epp_offline(struct cpufreq_policy *policy)
+{
+ struct amd_cpudata *cpudata = all_cpu_data[policy->cpu];
+ struct cppc_perf_ctrls perf_ctrls;
+ int min_perf;
+ u64 value;
+
+ min_perf = READ_ONCE(cpudata->lowest_perf);
+ value = READ_ONCE(cpudata->cppc_req_cached);
+
+ mutex_lock(&amd_pstate_limits_lock);
+ if (boot_cpu_has(X86_FEATURE_CPPC)) {
+ cpudata->epp_policy = CPUFREQ_POLICY_UNKNOWN;
+
+ /* Set max perf same as min perf */
+ value &= ~AMD_CPPC_MAX_PERF(~0L);
+ value |= AMD_CPPC_MAX_PERF(min_perf);
+ value &= ~AMD_CPPC_MIN_PERF(~0L);
+ value |= AMD_CPPC_MIN_PERF(min_perf);
+ wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
+ } else {
+ perf_ctrls.desired_perf = 0;
+ perf_ctrls.max_perf = min_perf;
+ perf_ctrls.energy_perf = AMD_CPPC_ENERGY_PERF_PREF(AMD_CPPC_EPP_POWERSAVE);
+ cppc_set_perf(cpudata->cpu, &perf_ctrls);
+ }
+ mutex_unlock(&amd_pstate_limits_lock);
+}
+
+static int amd_pstate_cpu_offline(struct cpufreq_policy *policy)
+{
+ struct amd_cpudata *cpudata = all_cpu_data[policy->cpu];
+
+ pr_debug("AMD CPU Core %d going offline\n", cpudata->cpu);
+
+ if (cpudata->suspended)
+ return 0;
+
+ if (cppc_active)
+ amd_pstate_epp_offline(policy);
+
+ return 0;
+}
+
+static int amd_pstate_epp_cpu_offline(struct cpufreq_policy *policy)
+{
+ amd_pstate_clear_update_util_hook(policy->cpu);
+
+ return amd_pstate_cpu_offline(policy);
+}
+
static void amd_pstate_verify_cpu_policy(struct amd_cpudata *cpudata,
struct cpufreq_policy_data *policy)
{
@@ -1229,6 +1316,8 @@ static struct cpufreq_driver amd_pstate_epp_driver = {
.init = amd_pstate_epp_cpu_init,
.exit = amd_pstate_epp_cpu_exit,
.update_limits = amd_pstate_epp_update_limits,
+ .offline = amd_pstate_epp_cpu_offline,
+ .online = amd_pstate_epp_cpu_online,
.name = "amd_pstate_epp",
.attr = amd_pstate_epp_attr,
};
diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h
index 7e6e8cab97b3..c0ad7eedcae3 100644
--- a/include/linux/amd-pstate.h
+++ b/include/linux/amd-pstate.h
@@ -99,6 +99,7 @@ struct amd_cpudata {
u64 cppc_cap1_cached;
struct update_util_data update_util;
struct amd_aperf_mperf sample;
+ bool suspended;
};
/**
--
2.34.1
^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [PATCH v3 5/8] cpufreq: amd_pstate: implement amd pstate cpu online and offline callback
2022-11-07 17:57 ` [PATCH v3 5/8] cpufreq: amd_pstate: implement amd pstate cpu online and offline callback Perry Yuan
@ 2022-11-07 18:22 ` Limonciello, Mario
2022-11-13 16:19 ` Yuan, Perry
0 siblings, 1 reply; 35+ messages in thread
From: Limonciello, Mario @ 2022-11-07 18:22 UTC (permalink / raw)
To: Perry Yuan, rafael.j.wysocki, ray.huang, viresh.kumar
Cc: Deepak.Sharma, Nathan.Fontenot, Alexander.Deucher, Shimmer.Huang,
Xiaojian.Du, Li.Meng, linux-pm, linux-kernel
On 11/7/2022 11:57, Perry Yuan wrote:
> Adds online and offline driver callback support to allow cpu cores go
> offline and help to restore the previous working states when core goes
> back online later for EPP driver mode.
>
> Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
> ---
> drivers/cpufreq/amd-pstate.c | 89 ++++++++++++++++++++++++++++++++++++
> include/linux/amd-pstate.h | 1 +
> 2 files changed, 90 insertions(+)
>
> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
> index eb82bc6a7f66..6ce9fca0a128 100644
> --- a/drivers/cpufreq/amd-pstate.c
> +++ b/drivers/cpufreq/amd-pstate.c
> @@ -1195,6 +1195,93 @@ static int amd_pstate_epp_set_policy(struct cpufreq_policy *policy)
> return 0;
> }
>
> +static void amd_pstate_epp_reenable(struct amd_cpudata *cpudata)
> +{
> + struct cppc_perf_ctrls perf_ctrls;
> + u64 value, max_perf;
> + int ret;
> +
> + ret = amd_pstate_enable(true);
> + if (ret)
> + pr_err("failed to enable amd pstate during resume, return %d\n", ret);
> +
> + value = READ_ONCE(cpudata->cppc_req_cached);
> + max_perf = READ_ONCE(cpudata->highest_perf);
> +
> + if (boot_cpu_has(X86_FEATURE_CPPC)) {
> + wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
> + } else {
> + perf_ctrls.max_perf = max_perf;
> + perf_ctrls.energy_perf = AMD_CPPC_ENERGY_PERF_PREF(cpudata->epp_cached);
> + cppc_set_perf(cpudata->cpu, &perf_ctrls);
> + }
> +}
> +
> +static int amd_pstate_epp_cpu_online(struct cpufreq_policy *policy)
> +{
> + struct amd_cpudata *cpudata = all_cpu_data[policy->cpu];
> +
> + pr_debug("AMD CPU Core %d going online\n", cpudata->cpu);
> +
> + if (cppc_active) {
> + amd_pstate_epp_reenable(cpudata);
> + cpudata->suspended = false;
> + }
> +
> + return 0;
> +}
> +
> +static void amd_pstate_epp_offline(struct cpufreq_policy *policy)
> +{
> + struct amd_cpudata *cpudata = all_cpu_data[policy->cpu];
> + struct cppc_perf_ctrls perf_ctrls;
> + int min_perf;
> + u64 value;
> +
> + min_perf = READ_ONCE(cpudata->lowest_perf);
> + value = READ_ONCE(cpudata->cppc_req_cached);
> +
> + mutex_lock(&amd_pstate_limits_lock);
> + if (boot_cpu_has(X86_FEATURE_CPPC)) {
> + cpudata->epp_policy = CPUFREQ_POLICY_UNKNOWN;
> +
> + /* Set max perf same as min perf */
> + value &= ~AMD_CPPC_MAX_PERF(~0L);
> + value |= AMD_CPPC_MAX_PERF(min_perf);
> + value &= ~AMD_CPPC_MIN_PERF(~0L);
> + value |= AMD_CPPC_MIN_PERF(min_perf);
> + wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
> + } else {
> + perf_ctrls.desired_perf = 0;
> + perf_ctrls.max_perf = min_perf;
> + perf_ctrls.energy_perf = AMD_CPPC_ENERGY_PERF_PREF(AMD_CPPC_EPP_POWERSAVE);
> + cppc_set_perf(cpudata->cpu, &perf_ctrls);
> + }
> + mutex_unlock(&amd_pstate_limits_lock);
> +}
> +
> +static int amd_pstate_cpu_offline(struct cpufreq_policy *policy)
> +{
> + struct amd_cpudata *cpudata = all_cpu_data[policy->cpu];
> +
> + pr_debug("AMD CPU Core %d going offline\n", cpudata->cpu);
> +
> + if (cpudata->suspended)
> + return 0;
> +
> + if (cppc_active)
> + amd_pstate_epp_offline(policy);
> +
> + return 0;
> +}
> +
> +static int amd_pstate_epp_cpu_offline(struct cpufreq_policy *policy)
> +{
> + amd_pstate_clear_update_util_hook(policy->cpu);
> +
> + return amd_pstate_cpu_offline(policy);
> +}
> +
> static void amd_pstate_verify_cpu_policy(struct amd_cpudata *cpudata,
> struct cpufreq_policy_data *policy)
> {
> @@ -1229,6 +1316,8 @@ static struct cpufreq_driver amd_pstate_epp_driver = {
> .init = amd_pstate_epp_cpu_init,
> .exit = amd_pstate_epp_cpu_exit,
> .update_limits = amd_pstate_epp_update_limits,
> + .offline = amd_pstate_epp_cpu_offline,
> + .online = amd_pstate_epp_cpu_online,
> .name = "amd_pstate_epp",
> .attr = amd_pstate_epp_attr,
> };
> diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h
> index 7e6e8cab97b3..c0ad7eedcae3 100644
> --- a/include/linux/amd-pstate.h
> +++ b/include/linux/amd-pstate.h
> @@ -99,6 +99,7 @@ struct amd_cpudata {
> u64 cppc_cap1_cached;
> struct update_util_data update_util;
> struct amd_aperf_mperf sample;
> + bool suspended;
> };
>
> /**
^ permalink raw reply [flat|nested] 35+ messages in thread* RE: [PATCH v3 5/8] cpufreq: amd_pstate: implement amd pstate cpu online and offline callback
2022-11-07 18:22 ` Limonciello, Mario
@ 2022-11-13 16:19 ` Yuan, Perry
0 siblings, 0 replies; 35+ messages in thread
From: Yuan, Perry @ 2022-11-13 16:19 UTC (permalink / raw)
To: Limonciello, Mario, rafael.j.wysocki@intel.com, Huang, Ray,
viresh.kumar@linaro.org
Cc: Sharma, Deepak, Fontenot, Nathan, Deucher, Alexander,
Huang, Shimmer, Du, Xiaojian, Meng, Li (Jassmine),
linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org
[AMD Official Use Only - General]
> -----Original Message-----
> From: Limonciello, Mario <Mario.Limonciello@amd.com>
> Sent: Tuesday, November 8, 2022 2:22 AM
> To: Yuan, Perry <Perry.Yuan@amd.com>; rafael.j.wysocki@intel.com; Huang,
> Ray <Ray.Huang@amd.com>; viresh.kumar@linaro.org
> Cc: Sharma, Deepak <Deepak.Sharma@amd.com>; Fontenot, Nathan
> <Nathan.Fontenot@amd.com>; Deucher, Alexander
> <Alexander.Deucher@amd.com>; Huang, Shimmer
> <Shimmer.Huang@amd.com>; Du, Xiaojian <Xiaojian.Du@amd.com>; Meng,
> Li (Jassmine) <Li.Meng@amd.com>; linux-pm@vger.kernel.org; linux-
> kernel@vger.kernel.org
> Subject: Re: [PATCH v3 5/8] cpufreq: amd_pstate: implement amd pstate cpu
> online and offline callback
>
> On 11/7/2022 11:57, Perry Yuan wrote:
> > Adds online and offline driver callback support to allow cpu cores go
> > offline and help to restore the previous working states when core goes
> > back online later for EPP driver mode.
> >
> > Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
>
> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Thank you.
I pick up the RB tag in the V4.
Perry.
>
> > ---
> > drivers/cpufreq/amd-pstate.c | 89
> ++++++++++++++++++++++++++++++++++++
> > include/linux/amd-pstate.h | 1 +
> > 2 files changed, 90 insertions(+)
> >
> > diff --git a/drivers/cpufreq/amd-pstate.c
> > b/drivers/cpufreq/amd-pstate.c index eb82bc6a7f66..6ce9fca0a128 100644
> > --- a/drivers/cpufreq/amd-pstate.c
> > +++ b/drivers/cpufreq/amd-pstate.c
> > @@ -1195,6 +1195,93 @@ static int amd_pstate_epp_set_policy(struct
> cpufreq_policy *policy)
> > return 0;
> > }
> >
> > +static void amd_pstate_epp_reenable(struct amd_cpudata *cpudata) {
> > + struct cppc_perf_ctrls perf_ctrls;
> > + u64 value, max_perf;
> > + int ret;
> > +
> > + ret = amd_pstate_enable(true);
> > + if (ret)
> > + pr_err("failed to enable amd pstate during resume,
> return %d\n",
> > +ret);
> > +
> > + value = READ_ONCE(cpudata->cppc_req_cached);
> > + max_perf = READ_ONCE(cpudata->highest_perf);
> > +
> > + if (boot_cpu_has(X86_FEATURE_CPPC)) {
> > + wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
> > + } else {
> > + perf_ctrls.max_perf = max_perf;
> > + perf_ctrls.energy_perf =
> AMD_CPPC_ENERGY_PERF_PREF(cpudata->epp_cached);
> > + cppc_set_perf(cpudata->cpu, &perf_ctrls);
> > + }
> > +}
> > +
> > +static int amd_pstate_epp_cpu_online(struct cpufreq_policy *policy) {
> > + struct amd_cpudata *cpudata = all_cpu_data[policy->cpu];
> > +
> > + pr_debug("AMD CPU Core %d going online\n", cpudata->cpu);
> > +
> > + if (cppc_active) {
> > + amd_pstate_epp_reenable(cpudata);
> > + cpudata->suspended = false;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static void amd_pstate_epp_offline(struct cpufreq_policy *policy) {
> > + struct amd_cpudata *cpudata = all_cpu_data[policy->cpu];
> > + struct cppc_perf_ctrls perf_ctrls;
> > + int min_perf;
> > + u64 value;
> > +
> > + min_perf = READ_ONCE(cpudata->lowest_perf);
> > + value = READ_ONCE(cpudata->cppc_req_cached);
> > +
> > + mutex_lock(&amd_pstate_limits_lock);
> > + if (boot_cpu_has(X86_FEATURE_CPPC)) {
> > + cpudata->epp_policy = CPUFREQ_POLICY_UNKNOWN;
> > +
> > + /* Set max perf same as min perf */
> > + value &= ~AMD_CPPC_MAX_PERF(~0L);
> > + value |= AMD_CPPC_MAX_PERF(min_perf);
> > + value &= ~AMD_CPPC_MIN_PERF(~0L);
> > + value |= AMD_CPPC_MIN_PERF(min_perf);
> > + wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
> > + } else {
> > + perf_ctrls.desired_perf = 0;
> > + perf_ctrls.max_perf = min_perf;
> > + perf_ctrls.energy_perf =
> AMD_CPPC_ENERGY_PERF_PREF(AMD_CPPC_EPP_POWERSAVE);
> > + cppc_set_perf(cpudata->cpu, &perf_ctrls);
> > + }
> > + mutex_unlock(&amd_pstate_limits_lock);
> > +}
> > +
> > +static int amd_pstate_cpu_offline(struct cpufreq_policy *policy) {
> > + struct amd_cpudata *cpudata = all_cpu_data[policy->cpu];
> > +
> > + pr_debug("AMD CPU Core %d going offline\n", cpudata->cpu);
> > +
> > + if (cpudata->suspended)
> > + return 0;
> > +
> > + if (cppc_active)
> > + amd_pstate_epp_offline(policy);
> > +
> > + return 0;
> > +}
> > +
> > +static int amd_pstate_epp_cpu_offline(struct cpufreq_policy *policy)
> > +{
> > + amd_pstate_clear_update_util_hook(policy->cpu);
> > +
> > + return amd_pstate_cpu_offline(policy); }
> > +
> > static void amd_pstate_verify_cpu_policy(struct amd_cpudata *cpudata,
> > struct cpufreq_policy_data *policy)
> > {
> > @@ -1229,6 +1316,8 @@ static struct cpufreq_driver
> amd_pstate_epp_driver = {
> > .init = amd_pstate_epp_cpu_init,
> > .exit = amd_pstate_epp_cpu_exit,
> > .update_limits = amd_pstate_epp_update_limits,
> > + .offline = amd_pstate_epp_cpu_offline,
> > + .online = amd_pstate_epp_cpu_online,
> > .name = "amd_pstate_epp",
> > .attr = amd_pstate_epp_attr,
> > };
> > diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h
> > index 7e6e8cab97b3..c0ad7eedcae3 100644
> > --- a/include/linux/amd-pstate.h
> > +++ b/include/linux/amd-pstate.h
> > @@ -99,6 +99,7 @@ struct amd_cpudata {
> > u64 cppc_cap1_cached;
> > struct update_util_data update_util;
> > struct amd_aperf_mperf sample;
> > + bool suspended;
> > };
> >
> > /**
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v3 6/8] cpufreq: amd-pstate: implement suspend and resume callbacks
2022-11-07 17:56 [PATCH v3 0/8] Implement AMD Pstate EPP Driver Perry Yuan
` (4 preceding siblings ...)
2022-11-07 17:57 ` [PATCH v3 5/8] cpufreq: amd_pstate: implement amd pstate cpu online and offline callback Perry Yuan
@ 2022-11-07 17:57 ` Perry Yuan
2022-11-07 18:18 ` Limonciello, Mario
2022-11-10 16:19 ` Nathan Fontenot
2022-11-07 17:57 ` [PATCH v3 7/8] cpufreq: amd-pstate: add frequency dynamic boost sysfs control Perry Yuan
2022-11-07 17:57 ` [PATCH v3 8/8] cpufreq: amd_pstate: add driver working mode status sysfs entry Perry Yuan
7 siblings, 2 replies; 35+ messages in thread
From: Perry Yuan @ 2022-11-07 17:57 UTC (permalink / raw)
To: rafael.j.wysocki, ray.huang, viresh.kumar
Cc: Deepak.Sharma, Mario.Limonciello, Nathan.Fontenot,
Alexander.Deucher, Shimmer.Huang, Xiaojian.Du, Li.Meng, linux-pm,
linux-kernel, Perry Yuan
add suspend and resume support for the AMD processors by amd_pstate_epp
driver instance.
When the CPPC is suspended, EPP driver will set EPP profile to 'power'
profile and set max/min perf to lowest perf value.
When resume happens, it will restore the MSR registers with
previous cached value.
Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
---
drivers/cpufreq/amd-pstate.c | 40 ++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
index 6ce9fca0a128..841b1e2383b8 100644
--- a/drivers/cpufreq/amd-pstate.c
+++ b/drivers/cpufreq/amd-pstate.c
@@ -1282,6 +1282,44 @@ static int amd_pstate_epp_cpu_offline(struct cpufreq_policy *policy)
return amd_pstate_cpu_offline(policy);
}
+static int amd_pstate_epp_suspend(struct cpufreq_policy *policy)
+{
+ struct amd_cpudata *cpudata = all_cpu_data[policy->cpu];
+ int ret;
+
+ /* avoid suspending when EPP is not enabled */
+ if (!cppc_active)
+ return 0;
+
+ /* set this flag to avoid setting core offline*/
+ cpudata->suspended = true;
+
+ /* disable CPPC in lowlevel firmware */
+ ret = amd_pstate_enable(false);
+ if (ret)
+ pr_err("failed to suspend, return %d\n", ret);
+
+ return 0;
+}
+
+static int amd_pstate_epp_resume(struct cpufreq_policy *policy)
+{
+ struct amd_cpudata *cpudata = all_cpu_data[policy->cpu];
+
+ if (cpudata->suspended) {
+ mutex_lock(&amd_pstate_limits_lock);
+
+ /* enable amd pstate from suspend state*/
+ amd_pstate_epp_reenable(cpudata);
+
+ mutex_unlock(&amd_pstate_limits_lock);
+
+ cpudata->suspended = false;
+ }
+
+ return 0;
+}
+
static void amd_pstate_verify_cpu_policy(struct amd_cpudata *cpudata,
struct cpufreq_policy_data *policy)
{
@@ -1318,6 +1356,8 @@ static struct cpufreq_driver amd_pstate_epp_driver = {
.update_limits = amd_pstate_epp_update_limits,
.offline = amd_pstate_epp_cpu_offline,
.online = amd_pstate_epp_cpu_online,
+ .suspend = amd_pstate_epp_suspend,
+ .resume = amd_pstate_epp_resume,
.name = "amd_pstate_epp",
.attr = amd_pstate_epp_attr,
};
--
2.34.1
^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [PATCH v3 6/8] cpufreq: amd-pstate: implement suspend and resume callbacks
2022-11-07 17:57 ` [PATCH v3 6/8] cpufreq: amd-pstate: implement suspend and resume callbacks Perry Yuan
@ 2022-11-07 18:18 ` Limonciello, Mario
2022-11-13 16:19 ` Yuan, Perry
2022-11-10 16:19 ` Nathan Fontenot
1 sibling, 1 reply; 35+ messages in thread
From: Limonciello, Mario @ 2022-11-07 18:18 UTC (permalink / raw)
To: Perry Yuan, rafael.j.wysocki, ray.huang, viresh.kumar
Cc: Deepak.Sharma, Nathan.Fontenot, Alexander.Deucher, Shimmer.Huang,
Xiaojian.Du, Li.Meng, linux-pm, linux-kernel
On 11/7/2022 11:57, Perry Yuan wrote:
> add suspend and resume support for the AMD processors by amd_pstate_epp
> driver instance.
>
> When the CPPC is suspended, EPP driver will set EPP profile to 'power'
> profile and set max/min perf to lowest perf value.
> When resume happens, it will restore the MSR registers with
> previous cached value.
>
> Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
> ---
> drivers/cpufreq/amd-pstate.c | 40 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
> index 6ce9fca0a128..841b1e2383b8 100644
> --- a/drivers/cpufreq/amd-pstate.c
> +++ b/drivers/cpufreq/amd-pstate.c
> @@ -1282,6 +1282,44 @@ static int amd_pstate_epp_cpu_offline(struct cpufreq_policy *policy)
> return amd_pstate_cpu_offline(policy);
> }
>
> +static int amd_pstate_epp_suspend(struct cpufreq_policy *policy)
> +{
> + struct amd_cpudata *cpudata = all_cpu_data[policy->cpu];
> + int ret;
> +
> + /* avoid suspending when EPP is not enabled */
> + if (!cppc_active)
> + return 0;
> +
> + /* set this flag to avoid setting core offline*/
> + cpudata->suspended = true;
> +
> + /* disable CPPC in lowlevel firmware */
> + ret = amd_pstate_enable(false);
> + if (ret)
> + pr_err("failed to suspend, return %d\n", ret);
> +
> + return 0;
> +}
> +
> +static int amd_pstate_epp_resume(struct cpufreq_policy *policy)
> +{
> + struct amd_cpudata *cpudata = all_cpu_data[policy->cpu];
> +
> + if (cpudata->suspended) {
> + mutex_lock(&amd_pstate_limits_lock);
> +
> + /* enable amd pstate from suspend state*/
> + amd_pstate_epp_reenable(cpudata);
> +
> + mutex_unlock(&amd_pstate_limits_lock);
> +
> + cpudata->suspended = false;
> + }
> +
> + return 0;
> +}
> +
> static void amd_pstate_verify_cpu_policy(struct amd_cpudata *cpudata,
> struct cpufreq_policy_data *policy)
> {
> @@ -1318,6 +1356,8 @@ static struct cpufreq_driver amd_pstate_epp_driver = {
> .update_limits = amd_pstate_epp_update_limits,
> .offline = amd_pstate_epp_cpu_offline,
> .online = amd_pstate_epp_cpu_online,
> + .suspend = amd_pstate_epp_suspend,
> + .resume = amd_pstate_epp_resume,
> .name = "amd_pstate_epp",
> .attr = amd_pstate_epp_attr,
> };
^ permalink raw reply [flat|nested] 35+ messages in thread* RE: [PATCH v3 6/8] cpufreq: amd-pstate: implement suspend and resume callbacks
2022-11-07 18:18 ` Limonciello, Mario
@ 2022-11-13 16:19 ` Yuan, Perry
0 siblings, 0 replies; 35+ messages in thread
From: Yuan, Perry @ 2022-11-13 16:19 UTC (permalink / raw)
To: Limonciello, Mario, rafael.j.wysocki@intel.com, Huang, Ray,
viresh.kumar@linaro.org
Cc: Sharma, Deepak, Fontenot, Nathan, Deucher, Alexander,
Huang, Shimmer, Du, Xiaojian, Meng, Li (Jassmine),
linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org
[AMD Official Use Only - General]
Hi Mario.
> -----Original Message-----
> From: Limonciello, Mario <Mario.Limonciello@amd.com>
> Sent: Tuesday, November 8, 2022 2:18 AM
> To: Yuan, Perry <Perry.Yuan@amd.com>; rafael.j.wysocki@intel.com; Huang,
> Ray <Ray.Huang@amd.com>; viresh.kumar@linaro.org
> Cc: Sharma, Deepak <Deepak.Sharma@amd.com>; Fontenot, Nathan
> <Nathan.Fontenot@amd.com>; Deucher, Alexander
> <Alexander.Deucher@amd.com>; Huang, Shimmer
> <Shimmer.Huang@amd.com>; Du, Xiaojian <Xiaojian.Du@amd.com>; Meng,
> Li (Jassmine) <Li.Meng@amd.com>; linux-pm@vger.kernel.org; linux-
> kernel@vger.kernel.org
> Subject: Re: [PATCH v3 6/8] cpufreq: amd-pstate: implement suspend and
> resume callbacks
>
> On 11/7/2022 11:57, Perry Yuan wrote:
> > add suspend and resume support for the AMD processors by
> > amd_pstate_epp driver instance.
> >
> > When the CPPC is suspended, EPP driver will set EPP profile to 'power'
> > profile and set max/min perf to lowest perf value.
> > When resume happens, it will restore the MSR registers with previous
> > cached value.
> >
> > Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
>
> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Thank you.
I pick up the RB tag in the V4.
Perry.
>
> > ---
> > drivers/cpufreq/amd-pstate.c | 40
> ++++++++++++++++++++++++++++++++++++
> > 1 file changed, 40 insertions(+)
> >
> > diff --git a/drivers/cpufreq/amd-pstate.c
> > b/drivers/cpufreq/amd-pstate.c index 6ce9fca0a128..841b1e2383b8
> 100644
> > --- a/drivers/cpufreq/amd-pstate.c
> > +++ b/drivers/cpufreq/amd-pstate.c
> > @@ -1282,6 +1282,44 @@ static int amd_pstate_epp_cpu_offline(struct
> cpufreq_policy *policy)
> > return amd_pstate_cpu_offline(policy);
> > }
> >
> > +static int amd_pstate_epp_suspend(struct cpufreq_policy *policy) {
> > + struct amd_cpudata *cpudata = all_cpu_data[policy->cpu];
> > + int ret;
> > +
> > + /* avoid suspending when EPP is not enabled */
> > + if (!cppc_active)
> > + return 0;
> > +
> > + /* set this flag to avoid setting core offline*/
> > + cpudata->suspended = true;
> > +
> > + /* disable CPPC in lowlevel firmware */
> > + ret = amd_pstate_enable(false);
> > + if (ret)
> > + pr_err("failed to suspend, return %d\n", ret);
> > +
> > + return 0;
> > +}
> > +
> > +static int amd_pstate_epp_resume(struct cpufreq_policy *policy) {
> > + struct amd_cpudata *cpudata = all_cpu_data[policy->cpu];
> > +
> > + if (cpudata->suspended) {
> > + mutex_lock(&amd_pstate_limits_lock);
> > +
> > + /* enable amd pstate from suspend state*/
> > + amd_pstate_epp_reenable(cpudata);
> > +
> > + mutex_unlock(&amd_pstate_limits_lock);
> > +
> > + cpudata->suspended = false;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > static void amd_pstate_verify_cpu_policy(struct amd_cpudata *cpudata,
> > struct cpufreq_policy_data *policy)
> > {
> > @@ -1318,6 +1356,8 @@ static struct cpufreq_driver
> amd_pstate_epp_driver = {
> > .update_limits = amd_pstate_epp_update_limits,
> > .offline = amd_pstate_epp_cpu_offline,
> > .online = amd_pstate_epp_cpu_online,
> > + .suspend = amd_pstate_epp_suspend,
> > + .resume = amd_pstate_epp_resume,
> > .name = "amd_pstate_epp",
> > .attr = amd_pstate_epp_attr,
> > };
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v3 6/8] cpufreq: amd-pstate: implement suspend and resume callbacks
2022-11-07 17:57 ` [PATCH v3 6/8] cpufreq: amd-pstate: implement suspend and resume callbacks Perry Yuan
2022-11-07 18:18 ` Limonciello, Mario
@ 2022-11-10 16:19 ` Nathan Fontenot
1 sibling, 0 replies; 35+ messages in thread
From: Nathan Fontenot @ 2022-11-10 16:19 UTC (permalink / raw)
To: Perry Yuan, rafael.j.wysocki, ray.huang, viresh.kumar
Cc: Deepak.Sharma, Mario.Limonciello, Alexander.Deucher,
Shimmer.Huang, Xiaojian.Du, Li.Meng, linux-pm, linux-kernel
On 11/7/22 11:57, Perry Yuan wrote:
> add suspend and resume support for the AMD processors by amd_pstate_epp
> driver instance.
>
> When the CPPC is suspended, EPP driver will set EPP profile to 'power'
> profile and set max/min perf to lowest perf value.
> When resume happens, it will restore the MSR registers with
> previous cached value.
>
> Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
> ---
> drivers/cpufreq/amd-pstate.c | 40 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
> index 6ce9fca0a128..841b1e2383b8 100644
> --- a/drivers/cpufreq/amd-pstate.c
> +++ b/drivers/cpufreq/amd-pstate.c
> @@ -1282,6 +1282,44 @@ static int amd_pstate_epp_cpu_offline(struct cpufreq_policy *policy)
> return amd_pstate_cpu_offline(policy);
> }
>
> +static int amd_pstate_epp_suspend(struct cpufreq_policy *policy)
> +{
> + struct amd_cpudata *cpudata = all_cpu_data[policy->cpu];
> + int ret;
> +
> + /* avoid suspending when EPP is not enabled */
> + if (!cppc_active)
> + return 0;
> +
> + /* set this flag to avoid setting core offline*/
> + cpudata->suspended = true;
Shouldn't we set this only after the amd_pstate_enable(false) call succeeds?
> +
> + /* disable CPPC in lowlevel firmware */
> + ret = amd_pstate_enable(false);
> + if (ret)
> + pr_err("failed to suspend, return %d\n", ret);
> +
> + return 0;
You could drop the checking of ret here and just return ret. The caller
cpufreq.c:cpufreq_suspend() already does a check of the return code and
prints an error message.
> +}
> +
> +static int amd_pstate_epp_resume(struct cpufreq_policy *policy)
> +{
> + struct amd_cpudata *cpudata = all_cpu_data[policy->cpu];
> +
> + if (cpudata->suspended) {
> + mutex_lock(&amd_pstate_limits_lock);
> +
> + /* enable amd pstate from suspend state*/
> + amd_pstate_epp_reenable(cpudata);
This call can fail, we should check the return code.
-Nathan
> +
> + mutex_unlock(&amd_pstate_limits_lock);
> +
> + cpudata->suspended = false;
> + }
> +
> + return 0;
> +}
> +
> static void amd_pstate_verify_cpu_policy(struct amd_cpudata *cpudata,
> struct cpufreq_policy_data *policy)
> {
> @@ -1318,6 +1356,8 @@ static struct cpufreq_driver amd_pstate_epp_driver = {
> .update_limits = amd_pstate_epp_update_limits,
> .offline = amd_pstate_epp_cpu_offline,
> .online = amd_pstate_epp_cpu_online,
> + .suspend = amd_pstate_epp_suspend,
> + .resume = amd_pstate_epp_resume,
> .name = "amd_pstate_epp",
> .attr = amd_pstate_epp_attr,
> };
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v3 7/8] cpufreq: amd-pstate: add frequency dynamic boost sysfs control
2022-11-07 17:56 [PATCH v3 0/8] Implement AMD Pstate EPP Driver Perry Yuan
` (5 preceding siblings ...)
2022-11-07 17:57 ` [PATCH v3 6/8] cpufreq: amd-pstate: implement suspend and resume callbacks Perry Yuan
@ 2022-11-07 17:57 ` Perry Yuan
2022-11-07 18:16 ` Limonciello, Mario
2022-11-07 17:57 ` [PATCH v3 8/8] cpufreq: amd_pstate: add driver working mode status sysfs entry Perry Yuan
7 siblings, 1 reply; 35+ messages in thread
From: Perry Yuan @ 2022-11-07 17:57 UTC (permalink / raw)
To: rafael.j.wysocki, ray.huang, viresh.kumar
Cc: Deepak.Sharma, Mario.Limonciello, Nathan.Fontenot,
Alexander.Deucher, Shimmer.Huang, Xiaojian.Du, Li.Meng, linux-pm,
linux-kernel, Perry Yuan
Add one sysfs entry to control the CPU cores frequency boost state
The attribute file can allow user to set max performance boosted or
keeping at normal perf level.
Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
---
drivers/cpufreq/amd-pstate.c | 53 ++++++++++++++++++++++++++++++++++++
1 file changed, 53 insertions(+)
diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
index 841b1e2383b8..6958c5fd9e1c 100644
--- a/drivers/cpufreq/amd-pstate.c
+++ b/drivers/cpufreq/amd-pstate.c
@@ -786,12 +786,46 @@ static ssize_t show_energy_performance_preference(
return sprintf(buf, "%s\n", energy_perf_strings[preference]);
}
+static void amd_pstate_update_policies(void)
+{
+ int cpu;
+
+ for_each_possible_cpu(cpu)
+ cpufreq_update_policy(cpu);
+}
+
+static ssize_t show_pstate_dynamic_boost(struct kobject *kobj,
+ struct kobj_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%u\n", cppc_boost);
+}
+
+static ssize_t store_pstate_dynamic_boost(struct kobject *a,
+ struct kobj_attribute *b,
+ const char *buf, size_t count)
+{
+ unsigned int input;
+ int ret;
+
+ ret = kstrtouint(buf, 10, &input);
+ if (ret)
+ return ret;
+
+ mutex_lock(&amd_pstate_driver_lock);
+ cppc_boost = !!input;
+ amd_pstate_update_policies();
+ mutex_unlock(&amd_pstate_driver_lock);
+
+ return count;
+}
+
cpufreq_freq_attr_ro(amd_pstate_max_freq);
cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq);
cpufreq_freq_attr_ro(amd_pstate_highest_perf);
cpufreq_freq_attr_rw(energy_performance_preference);
cpufreq_freq_attr_ro(energy_performance_available_preferences);
+define_one_global_rw(pstate_dynamic_boost);
static struct freq_attr *amd_pstate_attr[] = {
&amd_pstate_max_freq,
@@ -809,6 +843,15 @@ static struct freq_attr *amd_pstate_epp_attr[] = {
NULL,
};
+static struct attribute *pstate_global_attributes[] = {
+ &pstate_dynamic_boost.attr,
+ NULL
+};
+
+static const struct attribute_group amd_pstate_global_attr_group = {
+ .attrs = pstate_global_attributes,
+};
+
static inline void update_boost_state(void)
{
u64 misc_en;
@@ -1416,6 +1459,16 @@ static int __init amd_pstate_init(void)
pr_err("failed to register amd pstate driver with return %d\n",
ret);
+ amd_pstate_kobj = kobject_create_and_add("amd-pstate", &cpu_subsys.dev_root->kobj);
+ if (!amd_pstate_kobj)
+ pr_err("amd-pstate: Global sysfs registration failed.\n");
+
+ ret = sysfs_create_group(amd_pstate_kobj, &amd_pstate_global_attr_group);
+ if (ret) {
+ pr_err("amd-pstate: Sysfs attribute export failed with error %d.\n",
+ ret);
+ }
+
return ret;
}
device_initcall(amd_pstate_init);
--
2.34.1
^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [PATCH v3 7/8] cpufreq: amd-pstate: add frequency dynamic boost sysfs control
2022-11-07 17:57 ` [PATCH v3 7/8] cpufreq: amd-pstate: add frequency dynamic boost sysfs control Perry Yuan
@ 2022-11-07 18:16 ` Limonciello, Mario
2022-11-07 19:09 ` Limonciello, Mario
0 siblings, 1 reply; 35+ messages in thread
From: Limonciello, Mario @ 2022-11-07 18:16 UTC (permalink / raw)
To: Perry Yuan, rafael.j.wysocki, ray.huang, viresh.kumar
Cc: Deepak.Sharma, Nathan.Fontenot, Alexander.Deucher, Shimmer.Huang,
Xiaojian.Du, Li.Meng, linux-pm, linux-kernel, wyes.karny
+wyes.karny@amd.com
On 11/7/2022 11:57, Perry Yuan wrote:
> Add one sysfs entry to control the CPU cores frequency boost state
> The attribute file can allow user to set max performance boosted or
> keeping at normal perf level.
>
> Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
> ---
> drivers/cpufreq/amd-pstate.c | 53 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 53 insertions(+)
Make sure that you update the documentation for this new sysfs file as well.
>
> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
> index 841b1e2383b8..6958c5fd9e1c 100644
> --- a/drivers/cpufreq/amd-pstate.c
> +++ b/drivers/cpufreq/amd-pstate.c
> @@ -786,12 +786,46 @@ static ssize_t show_energy_performance_preference(
> return sprintf(buf, "%s\n", energy_perf_strings[preference]);
> }
>
> +static void amd_pstate_update_policies(void)
> +{
> + int cpu;
> +
> + for_each_possible_cpu(cpu)
> + cpufreq_update_policy(cpu);
> +}
> +
> +static ssize_t show_pstate_dynamic_boost(struct kobject *kobj,
> + struct kobj_attribute *attr, char *buf)
> +{
> + return sprintf(buf, "%u\n", cppc_boost);
> +}
> +
> +static ssize_t store_pstate_dynamic_boost(struct kobject *a,
> + struct kobj_attribute *b,
> + const char *buf, size_t count)
> +{
> + unsigned int input;
> + int ret;
> +
> + ret = kstrtouint(buf, 10, &input);
> + if (ret)
> + return ret;
To be more flexible maybe kstrtobool would be better here instead?
> +
> + mutex_lock(&amd_pstate_driver_lock);
> + cppc_boost = !!input;
> + amd_pstate_update_policies();
> + mutex_unlock(&amd_pstate_driver_lock);
> +
> + return count;
> +}
> +
> cpufreq_freq_attr_ro(amd_pstate_max_freq);
> cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq);
>
> cpufreq_freq_attr_ro(amd_pstate_highest_perf);
> cpufreq_freq_attr_rw(energy_performance_preference);
> cpufreq_freq_attr_ro(energy_performance_available_preferences);
> +define_one_global_rw(pstate_dynamic_boost);
>
> static struct freq_attr *amd_pstate_attr[] = {
> &amd_pstate_max_freq,
> @@ -809,6 +843,15 @@ static struct freq_attr *amd_pstate_epp_attr[] = {
> NULL,
> };
>
> +static struct attribute *pstate_global_attributes[] = {
> + &pstate_dynamic_boost.attr,
> + NULL
> +};
> +
> +static const struct attribute_group amd_pstate_global_attr_group = {
> + .attrs = pstate_global_attributes,
> +};
> +
> static inline void update_boost_state(void)
> {
> u64 misc_en;
> @@ -1416,6 +1459,16 @@ static int __init amd_pstate_init(void)
> pr_err("failed to register amd pstate driver with return %d\n",
> ret);
>
> + amd_pstate_kobj = kobject_create_and_add("amd-pstate", &cpu_subsys.dev_root->kobj);
> + if (!amd_pstate_kobj)
> + pr_err("amd-pstate: Global sysfs registration failed.\n");
> +
> + ret = sysfs_create_group(amd_pstate_kobj, &amd_pstate_global_attr_group);
> + if (ret) {
> + pr_err("amd-pstate: Sysfs attribute export failed with error %d.\n",
> + ret);
amd-pstate can currently be a module too. So don't you need the
matching cleanup path for this code too?
Also, regarding the error messages you don't need to prefix with
"amd-pstate: ", amd-pstate.c already sets `pr_fmt`.
> + }
> +
> return ret;
> }
> device_initcall(amd_pstate_init);
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [PATCH v3 7/8] cpufreq: amd-pstate: add frequency dynamic boost sysfs control
2022-11-07 18:16 ` Limonciello, Mario
@ 2022-11-07 19:09 ` Limonciello, Mario
0 siblings, 0 replies; 35+ messages in thread
From: Limonciello, Mario @ 2022-11-07 19:09 UTC (permalink / raw)
To: Perry Yuan, rafael.j.wysocki, ray.huang, viresh.kumar
Cc: Deepak.Sharma, Nathan.Fontenot, Alexander.Deucher, Shimmer.Huang,
Xiaojian.Du, Li.Meng, linux-pm, linux-kernel, wyes.karny
On 11/7/2022 12:16, Limonciello, Mario wrote:
> +wyes.karny@amd.com
>
> On 11/7/2022 11:57, Perry Yuan wrote:
>> Add one sysfs entry to control the CPU cores frequency boost state
>> The attribute file can allow user to set max performance boosted or
>> keeping at normal perf level.
>>
>> Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
>> ---
>> drivers/cpufreq/amd-pstate.c | 53 ++++++++++++++++++++++++++++++++++++
>> 1 file changed, 53 insertions(+)
>
> Make sure that you update the documentation for this new sysfs file as
> well.
>
>>
>> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
>> index 841b1e2383b8..6958c5fd9e1c 100644
>> --- a/drivers/cpufreq/amd-pstate.c
>> +++ b/drivers/cpufreq/amd-pstate.c
>> @@ -786,12 +786,46 @@ static ssize_t show_energy_performance_preference(
>> return sprintf(buf, "%s\n", energy_perf_strings[preference]);
>> }
>> +static void amd_pstate_update_policies(void)
>> +{
>> + int cpu;
>> +
>> + for_each_possible_cpu(cpu)
>> + cpufreq_update_policy(cpu);
>> +}
>> +
>> +static ssize_t show_pstate_dynamic_boost(struct kobject *kobj,
>> + struct kobj_attribute *attr, char *buf)
>> +{
>> + return sprintf(buf, "%u\n", cppc_boost);
>> +}
>> +
>> +static ssize_t store_pstate_dynamic_boost(struct kobject *a,
>> + struct kobj_attribute *b,
>> + const char *buf, size_t count)
>> +{
>> + unsigned int input;
>> + int ret;
>> +
>> + ret = kstrtouint(buf, 10, &input);
>> + if (ret)
>> + return ret;
>
> To be more flexible maybe kstrtobool would be better here instead?
>
>> +
>> + mutex_lock(&amd_pstate_driver_lock);
>> + cppc_boost = !!input;
>> + amd_pstate_update_policies();
>> + mutex_unlock(&amd_pstate_driver_lock);
>> +
>> + return count;
>> +}
>> +
>> cpufreq_freq_attr_ro(amd_pstate_max_freq);
>> cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq);
>> cpufreq_freq_attr_ro(amd_pstate_highest_perf);
>> cpufreq_freq_attr_rw(energy_performance_preference);
>> cpufreq_freq_attr_ro(energy_performance_available_preferences);
>> +define_one_global_rw(pstate_dynamic_boost);
>> static struct freq_attr *amd_pstate_attr[] = {
>> &amd_pstate_max_freq,
>> @@ -809,6 +843,15 @@ static struct freq_attr *amd_pstate_epp_attr[] = {
>> NULL,
>> };
>> +static struct attribute *pstate_global_attributes[] = {
>> + &pstate_dynamic_boost.attr,
>> + NULL
>> +};
>> +
>> +static const struct attribute_group amd_pstate_global_attr_group = {
>> + .attrs = pstate_global_attributes,
>> +};
>> +
>> static inline void update_boost_state(void)
>> {
>> u64 misc_en;
>> @@ -1416,6 +1459,16 @@ static int __init amd_pstate_init(void)
>> pr_err("failed to register amd pstate driver with return %d\n",
>> ret);
>> + amd_pstate_kobj = kobject_create_and_add("amd-pstate",
>> &cpu_subsys.dev_root->kobj);
>> + if (!amd_pstate_kobj)
>> + pr_err("amd-pstate: Global sysfs registration failed.\n");
>> +
>> + ret = sysfs_create_group(amd_pstate_kobj,
>> &amd_pstate_global_attr_group);
>> + if (ret) {
>> + pr_err("amd-pstate: Sysfs attribute export failed with error
>> %d.\n",
>> + ret);
>
> amd-pstate can currently be a module too. So don't you need the
> matching cleanup path for this code too?
I noticed your patch 3/8 makes this change, so this specific comment
might not be as important anymore.
>
> Also, regarding the error messages you don't need to prefix with
> "amd-pstate: ", amd-pstate.c already sets `pr_fmt`.
Also, shouldn't failing to make these attributes fail the rest of
amd-pstate init rather than just showing error messages?
>
>> + }
>> +
>> return ret;
>> }
>> device_initcall(amd_pstate_init);
>
^ permalink raw reply [flat|nested] 35+ messages in thread
* [PATCH v3 8/8] cpufreq: amd_pstate: add driver working mode status sysfs entry
2022-11-07 17:56 [PATCH v3 0/8] Implement AMD Pstate EPP Driver Perry Yuan
` (6 preceding siblings ...)
2022-11-07 17:57 ` [PATCH v3 7/8] cpufreq: amd-pstate: add frequency dynamic boost sysfs control Perry Yuan
@ 2022-11-07 17:57 ` Perry Yuan
2022-11-07 18:10 ` Limonciello, Mario
2022-11-10 16:06 ` Nathan Fontenot
7 siblings, 2 replies; 35+ messages in thread
From: Perry Yuan @ 2022-11-07 17:57 UTC (permalink / raw)
To: rafael.j.wysocki, ray.huang, viresh.kumar
Cc: Deepak.Sharma, Mario.Limonciello, Nathan.Fontenot,
Alexander.Deucher, Shimmer.Huang, Xiaojian.Du, Li.Meng, linux-pm,
linux-kernel, Perry Yuan
While amd-pstate driver was loaded with specific driver mode, it will
need to check which mode is enabled for the pstate driver,add this sysfs
entry to show the current status
$ cat /sys/devices/system/cpu/amd-pstate/status
active
Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
---
drivers/cpufreq/amd-pstate.c | 44 ++++++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
index 6958c5fd9e1c..eadcc9d61d39 100644
--- a/drivers/cpufreq/amd-pstate.c
+++ b/drivers/cpufreq/amd-pstate.c
@@ -65,6 +65,8 @@ static int disable_pstate_load __initdata;
static int epp_off __initdata;
static struct cpufreq_driver *default_pstate_driver;
+static struct cpufreq_driver amd_pstate_epp_driver;
+static struct cpufreq_driver amd_pstate_driver;
static struct amd_cpudata **all_cpu_data;
static struct amd_pstate_params global_params;
@@ -819,6 +821,46 @@ static ssize_t store_pstate_dynamic_boost(struct kobject *a,
return count;
}
+static ssize_t amd_pstate_show_status(char *buf)
+{
+ if (!default_pstate_driver)
+ return sprintf(buf, "off\n");
+
+ return sprintf(buf, "%s\n", default_pstate_driver == &amd_pstate_epp_driver ?
+ "active" : "passive");
+}
+
+static int amd_pstate_update_status(const char *buf, size_t size)
+{
+ /* FIXME: add driver dynamic switching code */
+ return 0;
+}
+
+static ssize_t show_status(struct kobject *kobj,
+ struct kobj_attribute *attr, char *buf)
+{
+ ssize_t ret;
+
+ mutex_lock(&amd_pstate_driver_lock);
+ ret = amd_pstate_show_status(buf);
+ mutex_unlock(&amd_pstate_driver_lock);
+
+ return ret;
+}
+
+static ssize_t store_status(struct kobject *a, struct kobj_attribute *b,
+ const char *buf, size_t count)
+{
+ char *p = memchr(buf, '\n', count);
+ int ret;
+
+ mutex_lock(&amd_pstate_driver_lock);
+ ret = amd_pstate_update_status(buf, p ? p - buf : count);
+ mutex_unlock(&amd_pstate_driver_lock);
+
+ return ret < 0 ? ret : count;
+}
+
cpufreq_freq_attr_ro(amd_pstate_max_freq);
cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq);
@@ -826,6 +868,7 @@ cpufreq_freq_attr_ro(amd_pstate_highest_perf);
cpufreq_freq_attr_rw(energy_performance_preference);
cpufreq_freq_attr_ro(energy_performance_available_preferences);
define_one_global_rw(pstate_dynamic_boost);
+define_one_global_rw(status);
static struct freq_attr *amd_pstate_attr[] = {
&amd_pstate_max_freq,
@@ -845,6 +888,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = {
static struct attribute *pstate_global_attributes[] = {
&pstate_dynamic_boost.attr,
+ &status.attr,
NULL
};
--
2.34.1
^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [PATCH v3 8/8] cpufreq: amd_pstate: add driver working mode status sysfs entry
2022-11-07 17:57 ` [PATCH v3 8/8] cpufreq: amd_pstate: add driver working mode status sysfs entry Perry Yuan
@ 2022-11-07 18:10 ` Limonciello, Mario
2022-11-13 16:18 ` Yuan, Perry
2022-11-10 16:06 ` Nathan Fontenot
1 sibling, 1 reply; 35+ messages in thread
From: Limonciello, Mario @ 2022-11-07 18:10 UTC (permalink / raw)
To: Perry Yuan, rafael.j.wysocki, ray.huang, viresh.kumar
Cc: Deepak.Sharma, Nathan.Fontenot, Alexander.Deucher, Shimmer.Huang,
Xiaojian.Du, Li.Meng, linux-pm, linux-kernel
On 11/7/2022 11:57, Perry Yuan wrote:
> While amd-pstate driver was loaded with specific driver mode, it will
> need to check which mode is enabled for the pstate driver,add this sysfs
> entry to show the current status
>
> $ cat /sys/devices/system/cpu/amd-pstate/status
> active >
> Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
> ---
> drivers/cpufreq/amd-pstate.c | 44 ++++++++++++++++++++++++++++++++++++
You should update the matching amd-pstate documentation for this new
sysfs file.
> 1 file changed, 44 insertions(+)
>
> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
> index 6958c5fd9e1c..eadcc9d61d39 100644
> --- a/drivers/cpufreq/amd-pstate.c
> +++ b/drivers/cpufreq/amd-pstate.c
> @@ -65,6 +65,8 @@ static int disable_pstate_load __initdata;
> static int epp_off __initdata;
>
> static struct cpufreq_driver *default_pstate_driver;
> +static struct cpufreq_driver amd_pstate_epp_driver;
> +static struct cpufreq_driver amd_pstate_driver;
> static struct amd_cpudata **all_cpu_data;
>
> static struct amd_pstate_params global_params;
> @@ -819,6 +821,46 @@ static ssize_t store_pstate_dynamic_boost(struct kobject *a,
> return count;
> }
>
> +static ssize_t amd_pstate_show_status(char *buf)
> +{
> + if (!default_pstate_driver)
> + return sprintf(buf, "off\n");
> +
> + return sprintf(buf, "%s\n", default_pstate_driver == &amd_pstate_epp_driver ?
> + "active" : "passive");
> +}
> +
> +static int amd_pstate_update_status(const char *buf, size_t size)
> +{
> + /* FIXME: add driver dynamic switching code */
> + return 0;
> +}
So "Effectively" this is read only right now. I think it's better to
mark the sysfs file as read only and not bother to populate "store"
callback until you're ready to allow dynamically swapping back and forth.
If you want to keep the code there, then I think you should return an
-EOPNOTSUPP error code for amd_pstate_update_status.
> +
> +static ssize_t show_status(struct kobject *kobj,
> + struct kobj_attribute *attr, char *buf)
> +{
> + ssize_t ret;
> +
> + mutex_lock(&amd_pstate_driver_lock);
> + ret = amd_pstate_show_status(buf);
> + mutex_unlock(&amd_pstate_driver_lock);
> +
> + return ret;
> +}
> +
> +static ssize_t store_status(struct kobject *a, struct kobj_attribute *b,
> + const char *buf, size_t count)
> +{
> + char *p = memchr(buf, '\n', count);
> + int ret;
> +
> + mutex_lock(&amd_pstate_driver_lock);
> + ret = amd_pstate_update_status(buf, p ? p - buf : count);
> + mutex_unlock(&amd_pstate_driver_lock);
> +
> + return ret < 0 ? ret : count;
> +}
> +
> cpufreq_freq_attr_ro(amd_pstate_max_freq);
> cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq);
>
> @@ -826,6 +868,7 @@ cpufreq_freq_attr_ro(amd_pstate_highest_perf);
> cpufreq_freq_attr_rw(energy_performance_preference);
> cpufreq_freq_attr_ro(energy_performance_available_preferences);
> define_one_global_rw(pstate_dynamic_boost);
> +define_one_global_rw(status);
>
> static struct freq_attr *amd_pstate_attr[] = {
> &amd_pstate_max_freq,
> @@ -845,6 +888,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = {
>
> static struct attribute *pstate_global_attributes[] = {
> &pstate_dynamic_boost.attr,
> + &status.attr,
> NULL
> };
>
^ permalink raw reply [flat|nested] 35+ messages in thread* RE: [PATCH v3 8/8] cpufreq: amd_pstate: add driver working mode status sysfs entry
2022-11-07 18:10 ` Limonciello, Mario
@ 2022-11-13 16:18 ` Yuan, Perry
0 siblings, 0 replies; 35+ messages in thread
From: Yuan, Perry @ 2022-11-13 16:18 UTC (permalink / raw)
To: Limonciello, Mario, rafael.j.wysocki@intel.com, Huang, Ray,
viresh.kumar@linaro.org
Cc: Sharma, Deepak, Fontenot, Nathan, Deucher, Alexander,
Huang, Shimmer, Du, Xiaojian, Meng, Li (Jassmine),
linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org
[AMD Official Use Only - General]
Hi Mario.
> -----Original Message-----
> From: Limonciello, Mario <Mario.Limonciello@amd.com>
> Sent: Tuesday, November 8, 2022 2:10 AM
> To: Yuan, Perry <Perry.Yuan@amd.com>; rafael.j.wysocki@intel.com; Huang,
> Ray <Ray.Huang@amd.com>; viresh.kumar@linaro.org
> Cc: Sharma, Deepak <Deepak.Sharma@amd.com>; Fontenot, Nathan
> <Nathan.Fontenot@amd.com>; Deucher, Alexander
> <Alexander.Deucher@amd.com>; Huang, Shimmer
> <Shimmer.Huang@amd.com>; Du, Xiaojian <Xiaojian.Du@amd.com>; Meng,
> Li (Jassmine) <Li.Meng@amd.com>; linux-pm@vger.kernel.org; linux-
> kernel@vger.kernel.org
> Subject: Re: [PATCH v3 8/8] cpufreq: amd_pstate: add driver working mode
> status sysfs entry
>
> On 11/7/2022 11:57, Perry Yuan wrote:
> > While amd-pstate driver was loaded with specific driver mode, it will
> > need to check which mode is enabled for the pstate driver,add this
> > sysfs entry to show the current status
> >
> > $ cat /sys/devices/system/cpu/amd-pstate/status
> > active >
> > Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
> > ---
> > drivers/cpufreq/amd-pstate.c | 44
> > ++++++++++++++++++++++++++++++++++++
>
> You should update the matching amd-pstate documentation for this new
> sysfs file.
>
> > 1 file changed, 44 insertions(+)
> >
> > diff --git a/drivers/cpufreq/amd-pstate.c
> > b/drivers/cpufreq/amd-pstate.c index 6958c5fd9e1c..eadcc9d61d39
> 100644
> > --- a/drivers/cpufreq/amd-pstate.c
> > +++ b/drivers/cpufreq/amd-pstate.c
> > @@ -65,6 +65,8 @@ static int disable_pstate_load __initdata;
> > static int epp_off __initdata;
> >
> > static struct cpufreq_driver *default_pstate_driver;
> > +static struct cpufreq_driver amd_pstate_epp_driver; static struct
> > +cpufreq_driver amd_pstate_driver;
> > static struct amd_cpudata **all_cpu_data;
> >
> > static struct amd_pstate_params global_params; @@ -819,6 +821,46 @@
> > static ssize_t store_pstate_dynamic_boost(struct kobject *a,
> > return count;
> > }
> >
> > +static ssize_t amd_pstate_show_status(char *buf) {
> > + if (!default_pstate_driver)
> > + return sprintf(buf, "off\n");
> > +
> > + return sprintf(buf, "%s\n", default_pstate_driver ==
> &amd_pstate_epp_driver ?
> > + "active" : "passive");
> > +}
> > +
> > +static int amd_pstate_update_status(const char *buf, size_t size) {
> > + /* FIXME: add driver dynamic switching code */
> > + return 0;
> > +}
>
> So "Effectively" this is read only right now. I think it's better to mark the sysfs
> file as read only and not bother to populate "store"
> callback until you're ready to allow dynamically swapping back and forth.
>
> If you want to keep the code there, then I think you should return an -
> EOPNOTSUPP error code for amd_pstate_update_status.
Yes, changed to return EOPNOTSUPP code in V4.
Please help to take a look.
Thanks .
Perry.
>
> > +
> > +static ssize_t show_status(struct kobject *kobj,
> > + struct kobj_attribute *attr, char *buf) {
> > + ssize_t ret;
> > +
> > + mutex_lock(&amd_pstate_driver_lock);
> > + ret = amd_pstate_show_status(buf);
> > + mutex_unlock(&amd_pstate_driver_lock);
> > +
> > + return ret;
> > +}
> > +
> > +static ssize_t store_status(struct kobject *a, struct kobj_attribute *b,
> > + const char *buf, size_t count) {
> > + char *p = memchr(buf, '\n', count);
> > + int ret;
> > +
> > + mutex_lock(&amd_pstate_driver_lock);
> > + ret = amd_pstate_update_status(buf, p ? p - buf : count);
> > + mutex_unlock(&amd_pstate_driver_lock);
> > +
> > + return ret < 0 ? ret : count;
> > +}
> > +
> > cpufreq_freq_attr_ro(amd_pstate_max_freq);
> > cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq);
> >
> > @@ -826,6 +868,7 @@ cpufreq_freq_attr_ro(amd_pstate_highest_perf);
> > cpufreq_freq_attr_rw(energy_performance_preference);
> > cpufreq_freq_attr_ro(energy_performance_available_preferences);
> > define_one_global_rw(pstate_dynamic_boost);
> > +define_one_global_rw(status);
> >
> > static struct freq_attr *amd_pstate_attr[] = {
> > &amd_pstate_max_freq,
> > @@ -845,6 +888,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = {
> >
> > static struct attribute *pstate_global_attributes[] = {
> > &pstate_dynamic_boost.attr,
> > + &status.attr,
> > NULL
> > };
> >
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [PATCH v3 8/8] cpufreq: amd_pstate: add driver working mode status sysfs entry
2022-11-07 17:57 ` [PATCH v3 8/8] cpufreq: amd_pstate: add driver working mode status sysfs entry Perry Yuan
2022-11-07 18:10 ` Limonciello, Mario
@ 2022-11-10 16:06 ` Nathan Fontenot
2022-11-10 16:49 ` Yuan, Perry
1 sibling, 1 reply; 35+ messages in thread
From: Nathan Fontenot @ 2022-11-10 16:06 UTC (permalink / raw)
To: Perry Yuan, rafael.j.wysocki, ray.huang, viresh.kumar
Cc: Deepak.Sharma, Mario.Limonciello, Alexander.Deucher,
Shimmer.Huang, Xiaojian.Du, Li.Meng, linux-pm, linux-kernel
On 11/7/22 11:57, Perry Yuan wrote:
> While amd-pstate driver was loaded with specific driver mode, it will
> need to check which mode is enabled for the pstate driver,add this sysfs
> entry to show the current status
>
> $ cat /sys/devices/system/cpu/amd-pstate/status
> active
>
> Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
> ---
> drivers/cpufreq/amd-pstate.c | 44 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 44 insertions(+)
>
> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
> index 6958c5fd9e1c..eadcc9d61d39 100644
> --- a/drivers/cpufreq/amd-pstate.c
> +++ b/drivers/cpufreq/amd-pstate.c
> @@ -65,6 +65,8 @@ static int disable_pstate_load __initdata;
> static int epp_off __initdata;
>
> static struct cpufreq_driver *default_pstate_driver;
> +static struct cpufreq_driver amd_pstate_epp_driver;
> +static struct cpufreq_driver amd_pstate_driver;
> static struct amd_cpudata **all_cpu_data;
>
> static struct amd_pstate_params global_params;
> @@ -819,6 +821,46 @@ static ssize_t store_pstate_dynamic_boost(struct kobject *a,
> return count;
> }
>
> +static ssize_t amd_pstate_show_status(char *buf)
> +{
> + if (!default_pstate_driver)
> + return sprintf(buf, "off\n");
> +
> + return sprintf(buf, "%s\n", default_pstate_driver == &amd_pstate_epp_driver ?
> + "active" : "passive");
> +}
> +
> +static int amd_pstate_update_status(const char *buf, size_t size)
> +{
> + /* FIXME: add driver dynamic switching code */
> + return 0;
> +}
> +
> +static ssize_t show_status(struct kobject *kobj,
> + struct kobj_attribute *attr, char *buf)
> +{
> + ssize_t ret;
> +
> + mutex_lock(&amd_pstate_driver_lock);
> + ret = amd_pstate_show_status(buf);
> + mutex_unlock(&amd_pstate_driver_lock);
Do we really need to take a lock to show the driver status?
-Nathan
> +
> + return ret;
> +}
> +
> +static ssize_t store_status(struct kobject *a, struct kobj_attribute *b,
> + const char *buf, size_t count)
> +{
> + char *p = memchr(buf, '\n', count);
> + int ret;
> +
> + mutex_lock(&amd_pstate_driver_lock);
> + ret = amd_pstate_update_status(buf, p ? p - buf : count);
> + mutex_unlock(&amd_pstate_driver_lock);
> +
> + return ret < 0 ? ret : count;
> +}
> +
> cpufreq_freq_attr_ro(amd_pstate_max_freq);
> cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq);
>
> @@ -826,6 +868,7 @@ cpufreq_freq_attr_ro(amd_pstate_highest_perf);
> cpufreq_freq_attr_rw(energy_performance_preference);
> cpufreq_freq_attr_ro(energy_performance_available_preferences);
> define_one_global_rw(pstate_dynamic_boost);
> +define_one_global_rw(status);
>
> static struct freq_attr *amd_pstate_attr[] = {
> &amd_pstate_max_freq,
> @@ -845,6 +888,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = {
>
> static struct attribute *pstate_global_attributes[] = {
> &pstate_dynamic_boost.attr,
> + &status.attr,
> NULL
> };
>
^ permalink raw reply [flat|nested] 35+ messages in thread* RE: [PATCH v3 8/8] cpufreq: amd_pstate: add driver working mode status sysfs entry
2022-11-10 16:06 ` Nathan Fontenot
@ 2022-11-10 16:49 ` Yuan, Perry
0 siblings, 0 replies; 35+ messages in thread
From: Yuan, Perry @ 2022-11-10 16:49 UTC (permalink / raw)
To: Fontenot, Nathan, rafael.j.wysocki@intel.com, Huang, Ray,
viresh.kumar@linaro.org
Cc: Sharma, Deepak, Limonciello, Mario, Deucher, Alexander,
Huang, Shimmer, Du, Xiaojian, Meng, Li (Jassmine),
linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org
[AMD Official Use Only - General]
Hi Nathan.
> -----Original Message-----
> From: Fontenot, Nathan <Nathan.Fontenot@amd.com>
> Sent: Friday, November 11, 2022 12:07 AM
> To: Yuan, Perry <Perry.Yuan@amd.com>; rafael.j.wysocki@intel.com; Huang,
> Ray <Ray.Huang@amd.com>; viresh.kumar@linaro.org
> Cc: Sharma, Deepak <Deepak.Sharma@amd.com>; Limonciello, Mario
> <Mario.Limonciello@amd.com>; Deucher, Alexander
> <Alexander.Deucher@amd.com>; Huang, Shimmer
> <Shimmer.Huang@amd.com>; Du, Xiaojian <Xiaojian.Du@amd.com>; Meng,
> Li (Jassmine) <Li.Meng@amd.com>; linux-pm@vger.kernel.org; linux-
> kernel@vger.kernel.org
> Subject: Re: [PATCH v3 8/8] cpufreq: amd_pstate: add driver working mode
> status sysfs entry
>
> On 11/7/22 11:57, Perry Yuan wrote:
> > While amd-pstate driver was loaded with specific driver mode, it will
> > need to check which mode is enabled for the pstate driver,add this
> > sysfs entry to show the current status
> >
> > $ cat /sys/devices/system/cpu/amd-pstate/status
> > active
> >
> > Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
> > ---
> > drivers/cpufreq/amd-pstate.c | 44
> > ++++++++++++++++++++++++++++++++++++
> > 1 file changed, 44 insertions(+)
> >
> > diff --git a/drivers/cpufreq/amd-pstate.c
> > b/drivers/cpufreq/amd-pstate.c index 6958c5fd9e1c..eadcc9d61d39 100644
> > --- a/drivers/cpufreq/amd-pstate.c
> > +++ b/drivers/cpufreq/amd-pstate.c
> > @@ -65,6 +65,8 @@ static int disable_pstate_load __initdata; static
> > int epp_off __initdata;
> >
> > static struct cpufreq_driver *default_pstate_driver;
> > +static struct cpufreq_driver amd_pstate_epp_driver; static struct
> > +cpufreq_driver amd_pstate_driver;
> > static struct amd_cpudata **all_cpu_data;
> >
> > static struct amd_pstate_params global_params; @@ -819,6 +821,46 @@
> > static ssize_t store_pstate_dynamic_boost(struct kobject *a,
> > return count;
> > }
> >
> > +static ssize_t amd_pstate_show_status(char *buf) {
> > + if (!default_pstate_driver)
> > + return sprintf(buf, "off\n");
> > +
> > + return sprintf(buf, "%s\n", default_pstate_driver ==
> &amd_pstate_epp_driver ?
> > + "active" : "passive");
> > +}
> > +
> > +static int amd_pstate_update_status(const char *buf, size_t size) {
> > + /* FIXME: add driver dynamic switching code */
> > + return 0;
> > +}
> > +
> > +static ssize_t show_status(struct kobject *kobj,
> > + struct kobj_attribute *attr, char *buf) {
> > + ssize_t ret;
> > +
> > + mutex_lock(&amd_pstate_driver_lock);
> > + ret = amd_pstate_show_status(buf);
> > + mutex_unlock(&amd_pstate_driver_lock);
>
> Do we really need to take a lock to show the driver status?
Yes.
It needs to check the current status from sysfs now and it will support to switch the EPP and Non EPP driver through this sysfs node.
Perry.
>
> -Nathan
>
> > +
> > + return ret;
> > +}
> > +
> > +static ssize_t store_status(struct kobject *a, struct kobj_attribute *b,
> > + const char *buf, size_t count) {
> > + char *p = memchr(buf, '\n', count);
> > + int ret;
> > +
> > + mutex_lock(&amd_pstate_driver_lock);
> > + ret = amd_pstate_update_status(buf, p ? p - buf : count);
> > + mutex_unlock(&amd_pstate_driver_lock);
> > +
> > + return ret < 0 ? ret : count;
> > +}
> > +
> > cpufreq_freq_attr_ro(amd_pstate_max_freq);
> > cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq);
> >
> > @@ -826,6 +868,7 @@ cpufreq_freq_attr_ro(amd_pstate_highest_perf);
> > cpufreq_freq_attr_rw(energy_performance_preference);
> > cpufreq_freq_attr_ro(energy_performance_available_preferences);
> > define_one_global_rw(pstate_dynamic_boost);
> > +define_one_global_rw(status);
> >
> > static struct freq_attr *amd_pstate_attr[] = {
> > &amd_pstate_max_freq,
> > @@ -845,6 +888,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = {
> >
> > static struct attribute *pstate_global_attributes[] = {
> > &pstate_dynamic_boost.attr,
> > + &status.attr,
> > NULL
> > };
> >
^ permalink raw reply [flat|nested] 35+ messages in thread