Re: [RESEND v4 2/2] PM / devfreq: mediatek: Introduce MediaTek CCI devfreq driver

[Johnson Wang <johnson.wang@mediatek.com>]

On Thu, 2022-05-19 at 11:24 +0800, Chen-Yu Tsai wrote:
> On Wed, May 18, 2022 at 8:19 PM Johnson Wang <
> johnson.wang@mediatek.com> wrote:
> > 
> > Hi Chen-Yu,
> > 
> > On Fri, 2022-05-13 at 11:54 +0800, Chen-Yu Tsai wrote:
> > > On Fri, May 13, 2022 at 11:31 AM Johnson Wang <
> > > johnson.wang@mediatek.com> wrote:
> > > > 
> > > > We introduce a devfreq driver for the MediaTek Cache Coherent
> > > > Interconnect
> > > > (CCI) used by some MediaTek SoCs.
> > > > 
> > > > In this driver, we use the passive devfreq driver to get target
> > > > frequencies
> > > > and adjust voltages accordingly. In MT8183 and MT8186, the
> > > > MediaTek
> > > > CCI
> > > > is supplied by the same regulators with the little core CPUs.
> > > > 
> > > > Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> > > > Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
> > > > Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
> > > > ---
> > > > This patch depends on "devfreq-testing"[1].
> > > > [1]
> > > > 
https://urldefense.com/v3/__https://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git/log/?h=devfreq-testing__;!!CTRNKA9wMg0ARbw!zzOSoso9udvDV3h6kYlmizFtbn3ACA5aS2jCAjKyvtu4z0fobv1mD5uF9YbPSme8l_NnR05unTxkZfDdzohu8asWZQ$
> > > > 
> > > > ---
> > > >  drivers/devfreq/Kconfig           |  10 +
> > > >  drivers/devfreq/Makefile          |   1 +
> > > >  drivers/devfreq/mtk-cci-devfreq.c | 474
> > > > ++++++++++++++++++++++++++++++
> > > >  3 files changed, 485 insertions(+)
> > > >  create mode 100644 drivers/devfreq/mtk-cci-devfreq.c
> > > > 
> > > > diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
> > > > index 87eb2b837e68..9754d8b31621 100644
> > > > --- a/drivers/devfreq/Kconfig
> > > > +++ b/drivers/devfreq/Kconfig
> > > > @@ -120,6 +120,16 @@ config ARM_TEGRA_DEVFREQ
> > > >           It reads ACTMON counters of memory controllers and
> > > > adjusts the
> > > >           operating frequencies and voltages with OPP support.
> > > > 
> > > > +config ARM_MEDIATEK_CCI_DEVFREQ
> > > > +       tristate "MEDIATEK CCI DEVFREQ Driver"
> > > > +       depends on ARM_MEDIATEK_CPUFREQ || COMPILE_TEST
> > > > +       select DEVFREQ_GOV_PASSIVE
> > > > +       help
> > > > +         This adds a devfreq driver for MediaTek Cache
> > > > Coherent
> > > > Interconnect
> > > > +         which is shared the same regulators with the cpu
> > > > cluster.
> > > > It can track
> > > > +         buck voltages and update a proper CCI frequency. Use
> > > > the
> > > > notification
> > > > +         to get the regulator status.
> > > > +
> > > >  config ARM_RK3399_DMC_DEVFREQ
> > > >         tristate "ARM RK3399 DMC DEVFREQ Driver"
> > > >         depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
> > > > diff --git a/drivers/devfreq/Makefile
> > > > b/drivers/devfreq/Makefile
> > > > index 0b6be92a25d9..bf40d04928d0 100644
> > > > --- a/drivers/devfreq/Makefile
> > > > +++ b/drivers/devfreq/Makefile
> > > > @@ -11,6 +11,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE)     +=
> > > > governor_passive.o
> > > >  obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ)   += exynos-bus.o
> > > >  obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ)      += imx-bus.o
> > > >  obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ)   += imx8m-ddrc.o
> > > > +obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ) += mtk-cci-devfreq.o
> > > >  obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ)   += rk3399_dmc.o
> > > >  obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ)       += sun8i-a33-
> > > > mbus.o
> > > >  obj-$(CONFIG_ARM_TEGRA_DEVFREQ)                += tegra30-
> > > > devfreq.o
> > > > diff --git a/drivers/devfreq/mtk-cci-devfreq.c
> > > > b/drivers/devfreq/mtk-cci-devfreq.c
> > > > new file mode 100644
> > > > index 000000000000..aa8c37eb4a06
> > > > --- /dev/null
> > > > +++ b/drivers/devfreq/mtk-cci-devfreq.c
> > > > @@ -0,0 +1,474 @@
> 
> [...]
> 
> > > > +       if (IS_ERR(drv->sram_reg))
> > > > +               drv->sram_reg = NULL;
> > > > +       else {
> > > > +               ret = regulator_enable(drv->sram_reg);
> > > > +               if (ret) {
> > > > +                       dev_err(dev, "failed to enable sram
> > > > regulator\n");
> > > > +                       goto out_free_resources;
> > > > +               }
> > > > +       }
> > > > +
> > > > +       /*
> > > > +        * We assume min voltage is 0 and tracking target
> > > > voltage
> > > > using
> > > > +        * min_volt_shift for each iteration.
> > > > +        * The retry_max is 3 times of expeted iteration count.
> > > 
> > > expected?
> > > 
> > 
> > Maybe "the maximum" will be more appropriate?
> 
> 
> I was merely pointing out a typo in "expeted".
> 
> Looking at it again, I'm not sure why retry attempts are tied to the
> voltage.
> 
> 
> ChenYu

Hi Chen-Yu,

Thanks for you reminder.

Whenever the voltages are scaled up/down one step,
meaning that there is another iteration in the while loop.

Thus, our thought is to use times of the voltages step up/down to set
iteration limit.

BRs,
Johnson Wang