From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kumar Gala Subject: Re: [PATCH v6 1/5] qcom: spm: Add Subsystem Power Manager driver Date: Wed, 24 Sep 2014 12:53:08 -0500 Message-ID: <4BFC9B4E-A3D0-422E-9B55-0DB9F4B04EE9@codeaurora.org> References: <1411516281-58328-1-git-send-email-lina.iyer@linaro.org> <1411516281-58328-2-git-send-email-lina.iyer@linaro.org> <20140924172151.GD422@ilina-mac> Mime-Version: 1.0 (Mac OS X Mail 7.3 \(1878.6\)) Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: In-Reply-To: <20140924172151.GD422@ilina-mac> Sender: linux-arm-msm-owner@vger.kernel.org To: Lina Iyer Cc: sboyd@codeaurora.org, daniel.lezcano@linaro.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, khilman@linaro.org, msivasub@codeaurora.org, lorenzo.pieralisi@arm.com, linux-pm@vger.kernel.org List-Id: linux-pm@vger.kernel.org On Sep 24, 2014, at 12:21 PM, Lina Iyer wrote: > On Wed, Sep 24 2014 at 10:33 -0600, Kumar Gala wrote: >>=20 >> On Sep 23, 2014, at 6:51 PM, Lina Iyer wrote: >>=20 >>> Based on work by many authors, available at codeaurora.org >>>=20 >>> SPM is a hardware block that controls the peripheral logic surround= ing >>> the application cores (cpu/l$). When the core executes WFI instruct= ion, >>> the SPM takes over the putting the core in low power state as >>> configured. The wake up for the SPM is an interrupt at the GIC, whi= ch >>> then completes the rest of low power mode sequence and brings the c= ore >>> out of low power mode. >>>=20 >>> The SPM has a set of control registers that configure the SPMs >>> individually based on the type of the core and the runtime conditio= ns. >>> SPM is a finite state machine block to which a sequence is provided= and >>> it interprets the bytes and executes them in sequence. Each low po= wer >>> mode that the core can enter into is provided to the SPM as a seque= nce. >>>=20 >>> Configure the SPM to set the core (cpu or L2) into its low power mo= de, >>> the index of the first command in the sequence is set in the SPM_CT= L >>> register. When the core executes ARM wfi instruction, it triggers t= he >>> SPM state machine to start executing from that index. The SPM state >>> machine waits until the interrupt occurs and starts executing the r= est >>> of the sequence until it hits the end of the sequence. The end of t= he >>> sequence jumps the core out of its low power mode. >>>=20 >>> Signed-off-by: Lina Iyer >>> [lina: simplify the driver for initial submission, clean up and upd= ate >>> commit text] >>> --- >>> Documentation/devicetree/bindings/arm/msm/spm.txt | 43 +++ >>> drivers/soc/qcom/Kconfig | 8 + >>> drivers/soc/qcom/Makefile | 1 + >>> drivers/soc/qcom/spm.c | 388 +++++++++++= +++++++++++ >>> include/soc/qcom/spm.h | 38 +++ >>> 5 files changed, 478 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/arm/msm/spm.tx= t >>> create mode 100644 drivers/soc/qcom/spm.c >>> create mode 100644 include/soc/qcom/spm.h >>>=20 >>> diff --git a/Documentation/devicetree/bindings/arm/msm/spm.txt b/Do= cumentation/devicetree/bindings/arm/msm/spm.txt >>> new file mode 100644 >>> index 0000000..2ff2454 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/arm/msm/spm.txt >>> @@ -0,0 +1,43 @@ >>> +* Subsystem Power Manager (SPM) >>> + >>> +Qualcomm Snapdragons have SPM hardware blocks to control the Appli= cation >>> +Processor Sub-System power. These SPM blocks run individual state = machine >>> +to determine what the core (L2 or Krait/Scorpion) would do when th= e WFI >>> +instruction is executed by the core. >>> + >>> +The devicetree representation of the SPM block should be: >>> + >>> +Required properties >>> + >>> +- compatible: Must be - >>> + "qcom,spm-v2.1" >>> +- reg: The physical address and the size of the SPM's memory mappe= d registers >>> +- qcom,cpu: phandle for the CPU that the SPM block is attached to. >>> + This field is required on only for SPMs that control the CPU. >>=20 >> Let=92s make this just cpu-handle instead of qcom,cpu. The concept = of a handle to a cpu is pretty generic. >>=20 > Okay. Will look into it. > You mean just the property name, right? Correct. >=20 >>> +- qcom,saw2-clk-div: SAW2 configuration register to program the SP= M runtime >>> + clocks. The register for this property is MSM_SPM_REG_SAW2_CFG. >>=20 >> (add details on how this is used to compute timer tick. Is it timer= tick =3D saw_clk/saw2-clk-div? What is valid range of values) >>=20 > The SPM spec is not available for open use. The range of values is > irrelevant for the SPM clocks, usually, its a constant for an SoC, bu= t > may vary between the SoC. Its how the SPM on the SoC interprets it. Does the meaning of the divisor value change from SoC to SoC (not the v= alue itself)? Is it not always: timer tick =3D sys_ref_clk / (qcom,saw2-clk-div + 1) =20 >>> +- qcom,saw2-delays: The SPM delay values that SPM sequences would = refer to. >>> + The register for this property is MSM_SPM_REG_SAW2_SPM_DLY. >>=20 >> Didn=92t Stephen asked about splitting this up? Or at least treating= it as an array of 3 values? >>=20 > Yes he did. My response was similar to the clk-div values, its not > something you can change without hardware spec documentation. > And I need to mix the three values up, anyways before I write to the > register. Splitting it up, doesnt help understanding/configuring the = SPM > any better, so didnt change it. Hmm, will this value change from SPM to SPM on the same SoC? I=92m not= a fan of allowing random register values to get poked into the HW from= DT. While this one case might end up being acceptable, its a terrible= practice and not something I want use in the habit of doing. >>> +- qcom,saw2-enable: The SPM control register to enable/disable the= sleep state >>> + machine. The register for this property is MSM_SPM_REG_SAW2_SPM_C= TL. >>=20 >> Can this just be a boolean (exist or not), if so, probably change it= to qcom,saw2-disable (so lack of property means enable)? >>=20 > Okay, sure. >=20 >>> + >>> +Optional properties >>> + >>> +- qcom,saw2-spm-cmd-wfi: The WFI command sequence >>=20 >> probably add something like: =93array of bytes =85=94 (want to conve= y the data type somehow, is there a max length?) >>=20 > Okay. >=20 >>> +- qcom,saw2-spm-cmd-spc: The Standalone PC command sequence >>=20 >> probably add something like: =93array of bytes =85=94 (want to conve= y the data type somehow, is there a max length?) >>=20 > Okay. >=20 >>> + >>> +Example: >>> + spm@f9089000 { >>> + compatible =3D "qcom,spm-v2.1"; >>> + #address-cells =3D <1>; >>> + #size-cells =3D <1>; >>> + reg =3D <0xf9089000 0x1000>; >>> + qcom,cpu =3D <&CPU0>; >>> + qcom,saw2-clk-div =3D <0x1>; >>> + qcom,saw2-delays =3D <0x20000400>; >>> + qcom,saw2-enable =3D <0x1>; >>> + qcom,saw2-spm-cmd-wfi =3D [03 0b 0f]; >>> + qcom,saw2-spm-cmd-spc =3D [00 20 50 80 60 70 10 92 >>> + a0 b0 03 68 70 3b 92 a0 b0 >>> + 82 2b 50 10 30 02 22 30 0f]; >>> + }; >>=20 >> - k >>=20 >>=20 >> --=20 >> Employee of Qualcomm Innovation Center, Inc. >> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, h= osted by The Linux Foundation >>=20 > -- > To unsubscribe from this list: send the line "unsubscribe linux-arm-m= sm" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html --=20 Employee of Qualcomm Innovation Center, Inc. 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