Re: [PATCH 0/4] time: dynamic irq affinity

[Daniel Lezcano <daniel.lezcano@linaro.org>]

On 03/11/2013 04:24 AM, Santosh Shilimkar wrote:
> On Sunday 10 March 2013 11:52 PM, Daniel Lezcano wrote:

[ ... ]

>> I don't think it is the case for all the ARM platforms, at least we
>> tested it on vexpress TC2 and u8500, and the number of IPI were reduced
>> very significantly increasing the idle time for cpu0. TC2 will need
>> another optimization on another area for the idle wake up to gain real
>> improvements.
>>
> You are missing my point. TC2 can be an exception since the SGI can wakeup
> CPUs even from low power states where local timer's are stalled. Is that
> the case with U8500 ?

Well, the cpuidle driver is not going into a deep idle state to check
this out.

AFAICT this board has a specific firmware with the PRCMU (a device
managing the power on the board) and it replaces the GIC when going to
deep idle state, especially by reconnecting the GIC to the A9 cores
automatically when an interrupt occurs.

But definitively worth to check.

>> I will test it on OMAP but with the coupled idle state, I am not sure of
>> the behavior. Could elaborate a bit the specificity of OMAP ? I am not
>> sure to understand why I may miss some IPI wakeups.
>>
> I already mention the issue here [1]. You might not see any major issues
> because the missed asynchronous IPIs might eventually get executed when
> CPU's wakeup from deeper states because of idle wakeups. OMAP is no
> different from idle wakeup optimisation and it will surely benefit and work.
> The main reason I didn't pursue it because of not having solution for
> [1] which as discussed in past is very much essential from kernel
> functional correctness perspective. You might want to verify that by
> adding a tracepoint on IPI's on other reasons except the timer wakeup.

Oh, ok. I didn't make the connection. I got the point now.

If we can raise a fake hardware interrupt on the GIC (not sure that
could be done), may be we can implement something similar to the
broadcast timer mechanism to replace the IPI when the cores are not IPI
wakeup capable.


> [1] https://lkml.org/lkml/2013/2/27/39
> 


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