From: Leo Yan <leoy@marvell.com>
To: Achin Gupta <achin.gupta@arm.com>
Cc: Lorenzo Pieralisi <Lorenzo.Pieralisi@arm.com>,
Yu Tang <ytang5@marvell.com>, Zhou Zhu <zzhu3@marvell.com>,
Neil Zhang <zhangwm@marvell.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-pm@vger.kernel.org" <linux-pm@vger.kernel.org>
Subject: Re: [Question] Verification For arm64: suspend/resume implementation
Date: Tue, 24 Sep 2013 10:00:38 +0800 [thread overview]
Message-ID: <5240F246.6050402@marvell.com> (raw)
In-Reply-To: <20130923152606.GA6157@e102648.cambridge.arm.com>
On 09/23/2013 11:26 PM, Achin Gupta wrote:
> The foundation model (if thats what you are using) does not model an
> ARM cpu implementation. The CPUECTLR is a cpu specific register
> (imp. def.) so it is not present. The caches on the Foundation Model
> are inherently coherent so you do not need to access this register. If
> you do then the access is treated as an illegal instruction.
>
Thx for the info. So do u mean i need use FVP Model for A53?
Here have another question, ARM have the example code for boot wrapper
which will switch from EL3 to secure EL1 rather than non-secure's EL1?
Thx,
Leo Yan
next prev parent reply other threads:[~2013-09-24 2:01 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-09-13 2:53 [Question] Verification For arm64: suspend/resume implementation Leo Yan
2013-09-13 14:40 ` Lorenzo Pieralisi
2013-09-23 11:11 ` Leo Yan
2013-09-23 15:26 ` Achin Gupta
2013-09-24 2:00 ` Leo Yan [this message]
2013-09-24 9:02 ` Achin Gupta
2013-09-24 11:49 ` Leo Yan
2013-09-24 13:00 ` Catalin Marinas
2013-09-26 11:12 ` Leo Yan
2013-09-26 16:53 ` Catalin Marinas
2013-09-27 2:53 ` Leo Yan
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