From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sebastian Andrzej Siewior Subject: Re: [Patch V3 19/37] x86, irq: introduce mechanisms to support dynamically allocate IRQ for IOAPIC Date: Wed, 28 May 2014 12:39:12 +0200 Message-ID: <5385BCD0.1080802@linutronix.de> References: <1401178092-1228-1-git-send-email-jiang.liu@linux.intel.com> <1401178092-1228-20-git-send-email-jiang.liu@linux.intel.com> <538597F0.1040003@linutronix.de> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: Sender: linux-pci-owner@vger.kernel.org To: Thomas Gleixner Cc: Jiang Liu , Benjamin Herrenschmidt , Grant Likely , Ingo Molnar , "H. Peter Anvin" , "Rafael J. Wysocki" , Bjorn Helgaas , Randy Dunlap , Yinghai Lu , x86@kernel.org, Len Brown , Pavel Machek , Konrad Rzeszutek Wilk , Andrew Morton , Tony Luck , Joerg Roedel , Paul Gortmaker , Greg Kroah-Hartman , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org, Ingo Molnar , linux-pm@vger.kernel.org List-Id: linux-pm@vger.kernel.org On 05/28/2014 12:07 PM, Thomas Gleixner wrote: > > Right, so it needs the setup of irq 0 and that only happens when the > legacy_pic->nr_legacy_irqs > 0. > > Do you remember, why we switch to the null_pic later on? According to my memory all interrupts are serviced by the IOAPIC. The first 16 by the first IOAPIC, 17+ (everything behind the "PCI-bus") by the second IOAPIC. For that reason I didn't see a reason for the legacy PIC and set it to null_pic. Due to the timer problem it is delayed. > Thanks, > > tglx Sebastian