From: Mikko Perttunen <mikko.perttunen@kapsi.fi>
To: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: swarren@wwwdotorg.org, thierry.reding@gmail.com,
gnurou@gmail.com, rjw@rjwysocki.net, viresh.kumar@linaro.org,
mturquette@linaro.org, pwalmsley@nvidia.com, vinceh@nvidia.com,
pgaikwad@nvidia.com, linux-kernel@vger.kernel.org,
linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, tuomas.tynkkynen@iki.fi,
Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Subject: Re: [PATCH v7 01/16] clk: tegra: Add binding for the Tegra124 DFLL clocksource
Date: Fri, 13 Feb 2015 12:19:30 +0200 [thread overview]
Message-ID: <54DDCFB2.9070800@kapsi.fi> (raw)
In-Reply-To: <20150212135440.GG20811@tbergstrom-lnx.Nvidia.com>
On 02/12/2015 03:54 PM, Peter De Schrijver wrote:
> On Thu, Jan 08, 2015 at 03:22:04PM +0200, Mikko Perttunen wrote:
>> From: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
>>
>> The DFLL is the main clocksource for the fast CPU cluster on Tegra124
>> and also provides automatic CPU rail voltage scaling as well. The DFLL
>> is a separate IP block from the usual Tegra124 clock-and-reset
>> controller, so it gets its own node in the device tree.
>>
>
> Please add devicetree@vger.kernel.org to the next CC list.
Will do. Thanks for the acks!
>
> Peter.
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next prev parent reply other threads:[~2015-02-13 10:19 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-01-08 13:22 [PATCH v7 00/16] Tegra124 CL-DVFS / DFLL clocksource + cpufreq Mikko Perttunen
2015-01-08 13:22 ` [PATCH v7 02/16] clk: tegra: Add library for the DFLL clock source (open-loop mode) Mikko Perttunen
[not found] ` <1420723339-30735-3-git-send-email-mikko.perttunen-/1wQRMveznE@public.gmane.org>
2015-02-12 14:04 ` Peter De Schrijver
[not found] ` <1420723339-30735-1-git-send-email-mikko.perttunen-/1wQRMveznE@public.gmane.org>
2015-01-08 13:22 ` [PATCH v7 01/16] clk: tegra: Add binding for the Tegra124 DFLL clocksource Mikko Perttunen
2015-02-12 13:54 ` Peter De Schrijver
2015-02-13 10:19 ` Mikko Perttunen [this message]
2015-02-12 22:42 ` Thierry Reding
2015-02-13 9:38 ` Peter De Schrijver
2015-02-13 10:18 ` Mikko Perttunen
2015-02-16 7:11 ` Tuomas Tynkkynen
2015-01-08 13:22 ` [PATCH v7 03/16] clk: tegra: Add closed loop support for the DFLL Mikko Perttunen
2015-02-12 14:12 ` Peter De Schrijver
2015-01-08 13:22 ` [PATCH v7 16/16] ARM: tegra: enable Tegra124 cpufreq driver by default Mikko Perttunen
2015-01-08 13:22 ` [PATCH v7 04/16] clk: tegra: Add functions for parsing CVB tables Mikko Perttunen
2015-02-12 14:13 ` Peter De Schrijver
2015-01-08 13:22 ` [PATCH v7 05/16] clk: tegra: Add DFLL DVCO reset control for Tegra124 Mikko Perttunen
2015-02-12 14:19 ` Peter De Schrijver
[not found] ` <20150212141944.GK20811-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
2015-02-13 10:39 ` Mikko Perttunen
2015-02-16 9:40 ` Peter De Schrijver
2015-01-08 13:22 ` [PATCH v7 06/16] clk: tegra: Add Tegra124 DFLL clocksource platform driver Mikko Perttunen
2015-01-08 13:22 ` [PATCH v7 07/16] clk: tegra: Save/restore CCLKG_BURST_POLICY on suspend Mikko Perttunen
2015-02-12 14:24 ` Peter De Schrijver
2015-01-08 13:22 ` [PATCH v7 08/16] clk: tegra: Add the DFLL as a possible parent of the cclk_g clock Mikko Perttunen
2015-01-08 13:22 ` [PATCH v7 09/16] ARM: tegra: Add the DFLL to Tegra124 device tree Mikko Perttunen
2015-01-08 13:22 ` [PATCH v7 10/16] ARM: tegra: Enable the DFLL on the Jetson TK1 Mikko Perttunen
2015-01-08 13:22 ` [PATCH v7 11/16] cpufreq: tegra124: Add device tree bindings Mikko Perttunen
2015-01-08 13:22 ` [PATCH v7 12/16] cpufreq: tegra: Rename tegra-cpufreq to tegra20-cpufreq Mikko Perttunen
2015-01-08 13:22 ` [PATCH v7 13/16] cpufreq: Add cpufreq driver for Tegra124 Mikko Perttunen
2015-01-08 13:22 ` [PATCH v7 14/16] ARM: tegra: Add entries for cpufreq on Tegra124 Mikko Perttunen
2015-01-08 13:22 ` [PATCH v7 15/16] ARM: tegra: Add CPU regulator to the Jetson TK1 device tree Mikko Perttunen
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