From: Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
To: Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: "Stephen Warren"
<swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>,
"Alexandre Courbot"
<gnurou-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
"Philipp Zabel" <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>,
"Peter De Schrijver"
<pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
"Prashant Gaikwad"
<pgaikwad-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
"Terje Bergström"
<tbergstrom-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
"Hans de Goede"
<hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>,
"Tejun Heo" <tj-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
"Vince Hsu" <vinceh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
"Rafael J. Wysocki" <rjw-LthD3rsA81gm4RdzfppkhA@public.gmane.org>,
"Kevin Hilman" <khilman-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
"Ulf Hansson"
<ulf.hansson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH V3 08/19] soc: tegra: pmc: Clean-up PMC helper functions
Date: Tue, 21 Jul 2015 10:38:32 +0100 [thread overview]
Message-ID: <55AE1318.4030503@nvidia.com> (raw)
In-Reply-To: <20150717102546.GL3057@ulmo>
On 17/07/15 11:25, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Mon, Jul 13, 2015 at 01:39:46PM +0100, Jon Hunter wrote:
>> The following clean-ups have been made to the PMC code:
>>
>> 1. Add a macro for determining the state of a PMC powergate
>> 2. Use the readx_poll_timeout() function instead of implementing a local
>> polling loop with a timeout.
>> 3. Use a case-statement in the function that removes the powergate clamp
>> instead of multiple if-statements to improve readability.
>>
>> Signed-off-by: Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>> ---
>> drivers/soc/tegra/pmc.c | 72 ++++++++++++++++++++++++-------------------------
>> 1 file changed, 35 insertions(+), 37 deletions(-)
>>
>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
>> index c0635bdd4ee3..180d434deec5 100644
>> --- a/drivers/soc/tegra/pmc.c
>> +++ b/drivers/soc/tegra/pmc.c
>> @@ -28,6 +28,7 @@
>> #include <linux/export.h>
>> #include <linux/init.h>
>> #include <linux/io.h>
>> +#include <linux/iopoll.h>
>> #include <linux/of.h>
>> #include <linux/of_address.h>
>> #include <linux/platform_device.h>
>> @@ -56,6 +57,8 @@
>> #define PWRGATE_TOGGLE_START (1 << 8)
>>
>> #define REMOVE_CLAMPING 0x34
>> +#define REMOVE_CLAMPING_VDEC (1 << 3)
>> +#define REMOVE_CLAMPING_PCIE (1 << 4)
>>
>> #define PWRGATE_STATUS 0x38
>>
>> @@ -101,6 +104,8 @@
>>
>> #define GPU_RG_CNTRL 0x2d4
>>
>> +#define PMC_PWRGATE_STATE(val, id) (!!(val & BIT(id)))
>
> I find double-negations very difficult to read. ((value & BIT(id)) != 0)
> is clearer in my opinion. Also I'd suggest status or value as the first
> parameter name, for consistency with other parts of the driver.
>
>> +
>> struct tegra_pmc_soc {
>> unsigned int num_powergates;
>> const char *const *powergates;
>> @@ -177,15 +182,14 @@ static void tegra_pmc_writel(u32 value, unsigned long offset)
>> */
>> static int tegra_powergate_set(int id, bool new_state, bool wait)
>> {
>> - unsigned long timeout;
>> - bool status;
>> int ret = 0;
>> + u32 val;
>>
>> mutex_lock(&pmc->powergates_lock);
>>
>> - status = tegra_pmc_readl(PWRGATE_STATUS) & (1 << id);
>> + val = tegra_pmc_readl(PWRGATE_STATUS);
>>
>> - if (status == new_state) {
>> + if (PMC_PWRGATE_STATE(val, id) == new_state) {
>> mutex_unlock(&pmc->powergates_lock);
>> return 0;
>> }
>> @@ -193,17 +197,9 @@ static int tegra_powergate_set(int id, bool new_state, bool wait)
>> tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
>>
>> if (wait) {
>> - timeout = jiffies + msecs_to_jiffies(100);
>> - ret = -ETIMEDOUT;
>> -
>> - while (time_before(jiffies, timeout)) {
>> - status = !!(tegra_pmc_readl(PWRGATE_STATUS) & BIT(id));
>> - if (status == new_state) {
>> - ret = 0;
>> - break;
>> - }
>> - udelay(10);
>> - }
>> + ret = readx_poll_timeout(tegra_pmc_readl, PWRGATE_STATUS,
>> + val, PMC_PWRGATE_STATE(val, id) == new_state,
>> + 10, 100000);
>> }
>>
>> mutex_unlock(&pmc->powergates_lock);
>> @@ -242,13 +238,10 @@ EXPORT_SYMBOL(tegra_powergate_power_off);
>> */
>> int tegra_powergate_is_powered(int id)
>> {
>> - u32 status;
>> -
>> if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates)
>> return -EINVAL;
>>
>> - status = tegra_pmc_readl(PWRGATE_STATUS) & (1 << id);
>> - return !!status;
>> + return PMC_PWRGATE_STATE(tegra_pmc_readl(PWRGATE_STATUS), id);
>
> I'd prefer to keep the two steps here. As a general rule I try never to
> mix reading or writing a register with other code on the same line.
>
>> }
>>
>> /**
>> @@ -257,34 +250,39 @@ int tegra_powergate_is_powered(int id)
>> */
>> int tegra_powergate_remove_clamping(int id)
>> {
>> - u32 mask;
>> + u32 val, reg;
>
> Side note: Please use value instead of val since that's the form used
> elsewhere in the driver. Also reg would be more appropriately called
> offset or similar because that's what it really is. It would also be
> more naturally an unsized type, such as unsigned int. But...
>
>>
>> if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates)
>> return -EINVAL;
>>
>> /*
>> - * On Tegra124 and later, the clamps for the GPU are controlled by a
>> - * separate register (with different semantics).
>> + * In most cases the bit for removing the IO clamping is the same as
>> + * the powergate partition ID, however, this is not always the case.
>> + * Furthermore, on Tegra124 and later, the clamps for the GPU are
>> + * controlled by a separate register (with different semantics). The
>> + * following case-statement handles these exceptions.
>> */
>> - if (id == TEGRA_POWERGATE_3D) {
>> + val = 1 << id;
>> + reg = REMOVE_CLAMPING;
>> +
>> + switch (id) {
>> + case TEGRA_POWERGATE_3D:
>> if (pmc->soc->has_gpu_clamps) {
>> - tegra_pmc_writel(0, GPU_RG_CNTRL);
>> - return 0;
>> + val = 0;
>> + reg = GPU_RG_CNTRL;
>> }
>> + break;
>> + case TEGRA_POWERGATE_VDEC:
>> + val = REMOVE_CLAMPING_VDEC;
>> + break;
>> + case TEGRA_POWERGATE_PCIE:
>> + val = REMOVE_CLAMPING_PCIE;
>> + break;
>> + default:
>> + break;
>> }
>>
>> - /*
>> - * Tegra 2 has a bug where PCIE and VDE clamping masks are
>> - * swapped relatively to the partition ids
>> - */
>> - if (id == TEGRA_POWERGATE_VDEC)
>> - mask = (1 << TEGRA_POWERGATE_PCIE);
>> - else if (id == TEGRA_POWERGATE_PCIE)
>> - mask = (1 << TEGRA_POWERGATE_VDEC);
>> - else
>> - mask = (1 << id);
>> -
>> - tegra_pmc_writel(mask, REMOVE_CLAMPING);
>> + tegra_pmc_writel(val, reg);
>
> ... to be honest, I think the previous code was more straightforward, so
> I'd prefer if you dropped this particular hunk.
Ok, I will drop that part. Jon
next prev parent reply other threads:[~2015-07-21 9:38 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-13 12:39 [PATCH V3 00/19] Add generic PM domain support for Tegra SoCs Jon Hunter
2015-07-13 12:39 ` [PATCH V3 06/19] clk: tegra: remove TEGRA_PLL_USE_LOCK for PLLD/PLLD2 Jon Hunter
[not found] ` <1436791197-32358-7-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-07-13 13:41 ` Peter De Schrijver
2015-07-13 14:02 ` Jon Hunter
[not found] ` <55A3C50E.7060706-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-07-14 11:59 ` Jon Hunter
[not found] ` <55A4F985.7010503-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-07-15 8:16 ` Peter De Schrijver
2015-07-13 12:39 ` [PATCH V3 09/19] soc: tegra: pmc: Prepare for migrating to generic PM domains Jon Hunter
2015-07-13 12:39 ` [PATCH V3 10/19] drm/tegra: dc: Prepare for " Jon Hunter
[not found] ` <1436791197-32358-11-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-07-17 10:41 ` Thierry Reding
2015-07-28 8:30 ` Jon Hunter
[not found] ` <55B73D8C.103-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-07-28 11:20 ` Thierry Reding
[not found] ` <20150728112030.GA10949-AwZRO8vwLAwmlAP/+Wk3EA@public.gmane.org>
2015-07-28 15:30 ` Jon Hunter
2015-07-13 12:39 ` [PATCH V3 11/19] PCI: tegra: Add support " Jon Hunter
2015-07-17 10:45 ` Thierry Reding
2015-07-28 8:35 ` Jon Hunter
2015-07-13 12:39 ` [PATCH V3 12/19] ata: ahci_tegra: " Jon Hunter
2015-07-13 12:39 ` [PATCH V3 13/19] drm/tegra: gr3d: " Jon Hunter
2015-07-13 12:39 ` [PATCH V3 17/19] ARM: tegra: Add PM domain device nodes to Tegra124 DT Jon Hunter
[not found] ` <1436791197-32358-1-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-07-13 12:39 ` [PATCH V3 01/19] reset: add of_reset_control_get_by_index() Jon Hunter
[not found] ` <1436791197-32358-2-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-07-17 12:08 ` Philipp Zabel
2015-07-13 12:39 ` [PATCH V3 02/19] memory: tegra: Add MC flush support Jon Hunter
2015-07-17 9:57 ` Thierry Reding
2015-07-17 10:20 ` Peter De Schrijver
[not found] ` <20150717102049.GQ6287-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
2015-07-17 11:31 ` Thierry Reding
2015-07-20 8:46 ` Jon Hunter
2015-07-20 9:17 ` Thierry Reding
2015-07-20 9:59 ` Peter De Schrijver
[not found] ` <20150720095941.GZ6287-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
2015-07-20 13:14 ` Thierry Reding
2015-07-21 10:57 ` Peter De Schrijver
2015-07-13 12:39 ` [PATCH V3 03/19] memory: tegra: add flush operation for Tegra30 memory clients Jon Hunter
[not found] ` <1436791197-32358-4-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-07-17 10:03 ` Thierry Reding
2015-07-21 8:54 ` Jon Hunter
2015-07-13 12:39 ` [PATCH V3 04/19] memory: tegra: add flush operation for Tegra114 " Jon Hunter
[not found] ` <1436791197-32358-5-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-07-17 10:05 ` Thierry Reding
2015-07-13 12:39 ` [PATCH V3 05/19] memory: tegra: add flush operation for Tegra124 " Jon Hunter
2015-07-17 10:05 ` Thierry Reding
2015-07-13 12:39 ` [PATCH V3 07/19] soc: tegra: pmc: Wait for powergate state to change Jon Hunter
[not found] ` <1436791197-32358-8-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-07-17 10:17 ` Thierry Reding
2015-07-21 9:34 ` Jon Hunter
2015-07-13 12:39 ` [PATCH V3 08/19] soc: tegra: pmc: Clean-up PMC helper functions Jon Hunter
2015-07-17 10:25 ` Thierry Reding
2015-07-21 9:38 ` Jon Hunter [this message]
2015-07-13 12:39 ` [PATCH V3 14/19] Documentation: DT: bindings: Add power domain info for NVIDIA PMC Jon Hunter
[not found] ` <1436791197-32358-15-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-07-17 9:38 ` Thierry Reding
2015-07-13 12:39 ` [PATCH V3 15/19] soc: tegra: pmc: Add generic PM domain support Jon Hunter
[not found] ` <1436791197-32358-16-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-07-17 11:29 ` Thierry Reding
2015-07-13 12:39 ` [PATCH V3 16/19] soc: tegra: pmc: Remove the deprecated powergate APIs Jon Hunter
2015-07-13 12:39 ` [PATCH V3 18/19] ARM: tegra: add GPU power supply to Jetson TK1 DT Jon Hunter
[not found] ` <1436791197-32358-19-git-send-email-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-07-17 9:28 ` Thierry Reding
2015-07-13 12:39 ` [PATCH V3 19/19] ARM: tegra: select PM_GENERIC_DOMAINS Jon Hunter
2015-07-13 13:50 ` Peter De Schrijver
[not found] ` <20150713135047.GR6287-Rysk9IDjsxmJz7etNGeUX8VPkgjIgRvpAL8bYrjMMd8@public.gmane.org>
2015-07-13 14:03 ` Jon Hunter
2015-07-14 11:59 ` Jon Hunter
[not found] ` <55A4F9B6.1070904-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-07-15 8:17 ` Peter De Schrijver
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