[PATCH 0/2] cpufreq: rcar: Enable CPUFreq support

[PATCH 0/2] cpufreq: rcar: Enable CPUFreq support

[Khiem Nguyen]

This series enables CPUFreq support in available R-Car Gen3 SoC.

It depends on 2 series below:
    [PATCH 0/4] clk: renesas: cpg-mssr: Add support for R-Car M3-W
    [RFC 0/4] Add Z clock support

All comments are appreciated.

Khiem Nguyen (2):
   cpufreq: rcar: Add support for R8A7795 SoC
   cpufreq: rcar: Add support for R8A7796 SoC

  drivers/cpufreq/cpufreq-dt-platdev.c | 2 ++
  1 file changed, 2 insertions(+)

-- 
1.9.1

[PATCH 1/2] cpufreq: rcar: Add support for R8A7795 SoC

[Khiem Nguyen]

After the commit "a399dc9fc50 cpufreq: shmobile: Use generic platdev
driver", will use cpufreq-dt-platdev driver to enable cpufreq-dt support.
Hence, follow the implementation to support new R8A7795 SoC.

Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@rvc.renesas.com>
---
  drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
  1 file changed, 1 insertion(+)

diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c 
b/drivers/cpufreq/cpufreq-dt-platdev.c
index ac4a0ba..32f6dda 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -53,6 +53,7 @@ static const struct of_device_id machines[] 
__initconst = {
  	{ .compatible = "renesas,r8a7791", },
  	{ .compatible = "renesas,r8a7793", },
  	{ .compatible = "renesas,r8a7794", },
+	{ .compatible = "renesas,r8a7795", },
  	{ .compatible = "renesas,sh73a0", },

  	{ .compatible = "rockchip,rk2928", },
-- 
1.9.1

[PATCH 2/2] cpufreq: rcar: Add support for R8A7796 SoC

[Khiem Nguyen]

Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@rvc.renesas.com>
---
  drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
  1 file changed, 1 insertion(+)

diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c 
b/drivers/cpufreq/cpufreq-dt-platdev.c
index 32f6dda..7d038fd 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -54,6 +54,7 @@ static const struct of_device_id machines[] 
__initconst = {
  	{ .compatible = "renesas,r8a7793", },
  	{ .compatible = "renesas,r8a7794", },
  	{ .compatible = "renesas,r8a7795", },
+	{ .compatible = "renesas,r8a7796", },
  	{ .compatible = "renesas,sh73a0", },

  	{ .compatible = "rockchip,rk2928", },
-- 
1.9.1

Re: [PATCH 1/2] cpufreq: rcar: Add support for R8A7795 SoC

[Viresh Kumar]

On 10-05-16, 11:57, Khiem Nguyen wrote:
> After the commit "a399dc9fc50 cpufreq: shmobile: Use generic platdev
> driver", will use cpufreq-dt-platdev driver to enable cpufreq-dt support.
> Hence, follow the implementation to support new R8A7795 SoC.
> 
> Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@rvc.renesas.com>
> ---
>  drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>

-- 
viresh

Re: [PATCH 2/2] cpufreq: rcar: Add support for R8A7796 SoC

[Viresh Kumar]

On 10-05-16, 11:59, Khiem Nguyen wrote:
> Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@rvc.renesas.com>
> ---
>  drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c
> b/drivers/cpufreq/cpufreq-dt-platdev.c
> index 32f6dda..7d038fd 100644
> --- a/drivers/cpufreq/cpufreq-dt-platdev.c
> +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
> @@ -54,6 +54,7 @@ static const struct of_device_id machines[] __initconst =
> {
>  	{ .compatible = "renesas,r8a7793", },
>  	{ .compatible = "renesas,r8a7794", },
>  	{ .compatible = "renesas,r8a7795", },
> +	{ .compatible = "renesas,r8a7796", },
>  	{ .compatible = "renesas,sh73a0", },
> 
>  	{ .compatible = "rockchip,rk2928", },

Well, you could have done that in the same patch. But I don't mind two patches
now.

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>

-- 
viresh

Re: [PATCH 1/2] cpufreq: rcar: Add support for R8A7795 SoC

[Geert Uytterhoeven]

Hi Viresh,

On Tue, May 10, 2016 at 7:07 AM, Viresh Kumar <viresh.kumar@linaro.org> wrote:
> On 10-05-16, 11:57, Khiem Nguyen wrote:
>> After the commit "a399dc9fc50 cpufreq: shmobile: Use generic platdev
>> driver", will use cpufreq-dt-platdev driver to enable cpufreq-dt support.
>> Hence, follow the implementation to support new R8A7795 SoC.
>>
>> Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@rvc.renesas.com>
>> ---
>>  drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
>>  1 file changed, 1 insertion(+)
>
> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>

Quoting Viresh when this file was introduced:
| This is going to be done once per boot and this shouldn't hurt. And for new
| platforms we may do things differently as they are going to use
opp-v2 bindings.

As r8a7795/r8a7796 are not arm32 "shmobile", but arm64, perhaps we should
use this new "opp-v2" binding instead? Has it been finalized?

Thanks!

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 1/2] cpufreq: rcar: Add support for R8A7795 SoC

[Viresh Kumar]

On 10-05-16, 10:17, Geert Uytterhoeven wrote:
> Hi Viresh,
> 
> On Tue, May 10, 2016 at 7:07 AM, Viresh Kumar <viresh.kumar@linaro.org> wrote:
> > On 10-05-16, 11:57, Khiem Nguyen wrote:
> >> After the commit "a399dc9fc50 cpufreq: shmobile: Use generic platdev
> >> driver", will use cpufreq-dt-platdev driver to enable cpufreq-dt support.
> >> Hence, follow the implementation to support new R8A7795 SoC.
> >>
> >> Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@rvc.renesas.com>
> >> ---
> >>  drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
> >>  1 file changed, 1 insertion(+)
> >
> > Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
> 
> Quoting Viresh when this file was introduced:
> | This is going to be done once per boot and this shouldn't hurt. And for new
> | platforms we may do things differently as they are going to use
> opp-v2 bindings.
> 
> As r8a7795/r8a7796 are not arm32 "shmobile", but arm64, perhaps we should
> use this new "opp-v2" binding instead? Has it been finalized?

Yeah, that would be preferred.

-- 
viresh

Re: [RFC 4/4] arm64: dts: r8a7795: Add Z clock scaling support

[Geert Uytterhoeven]

On Tue, May 10, 2016 at 6:46 AM, Khiem Nguyen
<khiem.nguyen.xt@rvc.renesas.com> wrote:
> This patch adds Z clock scaling support for CA57 in R8A7795 SoC.
> An OPP table is created with the supported frequency scaling.
>
> Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@rvc.renesas.com>
> ---
>  arch/arm64/boot/dts/renesas/r8a7795.dtsi | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> index 7181db0..041d0f2 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> @@ -43,6 +43,8 @@
>                         power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
>                         next-level-cache = <&L2_CA57>;
>                         enable-method = "psci";
> +                       clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
> +                       operating-points-v2 = <&cluster0_opp_tb0>;
>                 };
>
>                 a57_1: cpu@1 {
> @@ -52,6 +54,7 @@
>                         power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
>                         next-level-cache = <&L2_CA57>;
>                         enable-method = "psci";
> +                       operating-points-v2 = <&cluster0_opp_tb0>;
>                 };
>                 a57_2: cpu@2 {
>                         compatible = "arm,cortex-a57","arm,armv8";
> @@ -60,6 +63,7 @@
>                         power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
>                         next-level-cache = <&L2_CA57>;
>                         enable-method = "psci";
> +                       operating-points-v2 = <&cluster0_opp_tb0>;
>                 };
>                 a57_3: cpu@3 {
>                         compatible = "arm,cortex-a57","arm,armv8";
> @@ -68,6 +72,28 @@
>                         power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
>                         next-level-cache = <&L2_CA57>;
>                         enable-method = "psci";
> +                       operating-points-v2 = <&cluster0_opp_tb0>;
> +               };
> +       };
> +
> +       cluster0_opp_tb0: opp_table0 {
> +               compatible = "operating-points-v2";
> +               opp-shared;
> +
> +               opp@500000000 {
> +                       opp-hz = /bits/ 64 <500000000>;
> +                       opp-microvolt = <820000>;
> +                       clock-latency-ns = <300000>;
> +               };
> +               opp@1000000000 {
> +                       opp-hz = /bits/ 64 <1000000000>;
> +                       opp-microvolt = <820000>;
> +                       clock-latency-ns = <300000>;
> +               };
> +               opp@1500000000 {
> +                       opp-hz = /bits/ 64 <1500000000>;
> +                       opp-microvolt = <820000>;
> +                       clock-latency-ns = <300000>;

With W=1:

Warning (unit_address_vs_reg): Node /opp_table0/opp@500000000 has a
unit name, but no reg property
Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a
unit name, but no reg property
Warning (unit_address_vs_reg): Node /opp_table0/opp@1500000000 has a
unit name, but no reg property

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds