* [PATCH v2 1/4] interconnect: qcom: Add support for mask-based BCMs
2023-06-23 12:50 [PATCH v2 0/4] interconnect: qcom: rpmh: sm8550: mask to send as vote neil.armstrong
@ 2023-06-23 12:50 ` neil.armstrong
2023-06-23 13:45 ` Konrad Dybcio
2023-06-23 12:50 ` [PATCH v2 2/4] interconnect: qcom: sm8450: add enable_mask for bcm nodes Neil Armstrong
` (4 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: neil.armstrong @ 2023-06-23 12:50 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Georgi Djakov
Cc: linux-arm-msm, linux-pm, linux-kernel, Neil Armstrong,
Mike Tipton
From: Mike Tipton <mdtipton@codeaurora.org>
Some BCMs aren't directly associated with the data path (i.e. ACV) and
therefore don't communicate using BW. Instead, they are simply
enabled/disabled with a simple bit mask. Add support for these.
Origin commit retrieved from:
https://git.codelinaro.org/clo/la/kernel/msm-5.15/-/commit/2d1573e0206998151b342e6b52a4c0f7234d7e36
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
[narmstrong: removed copyright change from original commit]
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
drivers/interconnect/qcom/bcm-voter.c | 5 +++++
drivers/interconnect/qcom/icc-rpmh.h | 2 ++
2 files changed, 7 insertions(+)
diff --git a/drivers/interconnect/qcom/bcm-voter.c b/drivers/interconnect/qcom/bcm-voter.c
index 8f385f9c2dd3..d5f2a6b5376b 100644
--- a/drivers/interconnect/qcom/bcm-voter.c
+++ b/drivers/interconnect/qcom/bcm-voter.c
@@ -83,6 +83,11 @@ static void bcm_aggregate(struct qcom_icc_bcm *bcm)
temp = agg_peak[bucket] * bcm->vote_scale;
bcm->vote_y[bucket] = bcm_div(temp, bcm->aux_data.unit);
+
+ if (bcm->enable_mask && (bcm->vote_x[bucket] || bcm->vote_y[bucket])) {
+ bcm->vote_x[bucket] = 0;
+ bcm->vote_y[bucket] = bcm->enable_mask;
+ }
}
if (bcm->keepalive && bcm->vote_x[QCOM_ICC_BUCKET_AMC] == 0 &&
diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qcom/icc-rpmh.h
index 04391c1ba465..7843d8864d6b 100644
--- a/drivers/interconnect/qcom/icc-rpmh.h
+++ b/drivers/interconnect/qcom/icc-rpmh.h
@@ -81,6 +81,7 @@ struct qcom_icc_node {
* @vote_x: aggregated threshold values, represents sum_bw when @type is bw bcm
* @vote_y: aggregated threshold values, represents peak_bw when @type is bw bcm
* @vote_scale: scaling factor for vote_x and vote_y
+ * @enable_mask: optional mask to send as vote instead of vote_x/vote_y
* @dirty: flag used to indicate whether the bcm needs to be committed
* @keepalive: flag used to indicate whether a keepalive is required
* @aux_data: auxiliary data used when calculating threshold values and
@@ -97,6 +98,7 @@ struct qcom_icc_bcm {
u64 vote_x[QCOM_ICC_NUM_BUCKETS];
u64 vote_y[QCOM_ICC_NUM_BUCKETS];
u64 vote_scale;
+ u32 enable_mask;
bool dirty;
bool keepalive;
struct bcm_db aux_data;
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v2 1/4] interconnect: qcom: Add support for mask-based BCMs
2023-06-23 12:50 ` [PATCH v2 1/4] interconnect: qcom: Add support for mask-based BCMs neil.armstrong
@ 2023-06-23 13:45 ` Konrad Dybcio
0 siblings, 0 replies; 13+ messages in thread
From: Konrad Dybcio @ 2023-06-23 13:45 UTC (permalink / raw)
To: neil.armstrong, Andy Gross, Bjorn Andersson, Georgi Djakov
Cc: linux-arm-msm, linux-pm, linux-kernel, Mike Tipton
On 23.06.2023 14:50, neil.armstrong@linaro.org wrote:
> From: Mike Tipton <mdtipton@codeaurora.org>
>
> Some BCMs aren't directly associated with the data path (i.e. ACV) and
> therefore don't communicate using BW. Instead, they are simply
> enabled/disabled with a simple bit mask. Add support for these.
>
> Origin commit retrieved from:
> https://git.codelinaro.org/clo/la/kernel/msm-5.15/-/commit/2d1573e0206998151b342e6b52a4c0f7234d7e36
>
> Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
> [narmstrong: removed copyright change from original commit]
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> drivers/interconnect/qcom/bcm-voter.c | 5 +++++
> drivers/interconnect/qcom/icc-rpmh.h | 2 ++
> 2 files changed, 7 insertions(+)
>
> diff --git a/drivers/interconnect/qcom/bcm-voter.c b/drivers/interconnect/qcom/bcm-voter.c
> index 8f385f9c2dd3..d5f2a6b5376b 100644
> --- a/drivers/interconnect/qcom/bcm-voter.c
> +++ b/drivers/interconnect/qcom/bcm-voter.c
> @@ -83,6 +83,11 @@ static void bcm_aggregate(struct qcom_icc_bcm *bcm)
>
> temp = agg_peak[bucket] * bcm->vote_scale;
> bcm->vote_y[bucket] = bcm_div(temp, bcm->aux_data.unit);
> +
> + if (bcm->enable_mask && (bcm->vote_x[bucket] || bcm->vote_y[bucket])) {
> + bcm->vote_x[bucket] = 0;
> + bcm->vote_y[bucket] = bcm->enable_mask;
> + }
> }
>
> if (bcm->keepalive && bcm->vote_x[QCOM_ICC_BUCKET_AMC] == 0 &&
> diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qcom/icc-rpmh.h
> index 04391c1ba465..7843d8864d6b 100644
> --- a/drivers/interconnect/qcom/icc-rpmh.h
> +++ b/drivers/interconnect/qcom/icc-rpmh.h
> @@ -81,6 +81,7 @@ struct qcom_icc_node {
> * @vote_x: aggregated threshold values, represents sum_bw when @type is bw bcm
> * @vote_y: aggregated threshold values, represents peak_bw when @type is bw bcm
> * @vote_scale: scaling factor for vote_x and vote_y
> + * @enable_mask: optional mask to send as vote instead of vote_x/vote_y
> * @dirty: flag used to indicate whether the bcm needs to be committed
> * @keepalive: flag used to indicate whether a keepalive is required
> * @aux_data: auxiliary data used when calculating threshold values and
> @@ -97,6 +98,7 @@ struct qcom_icc_bcm {
> u64 vote_x[QCOM_ICC_NUM_BUCKETS];
> u64 vote_y[QCOM_ICC_NUM_BUCKETS];
> u64 vote_scale;
> + u32 enable_mask;
> bool dirty;
> bool keepalive;
> struct bcm_db aux_data;
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 2/4] interconnect: qcom: sm8450: add enable_mask for bcm nodes
2023-06-23 12:50 [PATCH v2 0/4] interconnect: qcom: rpmh: sm8550: mask to send as vote neil.armstrong
2023-06-23 12:50 ` [PATCH v2 1/4] interconnect: qcom: Add support for mask-based BCMs neil.armstrong
@ 2023-06-23 12:50 ` Neil Armstrong
2023-06-23 13:46 ` Konrad Dybcio
2023-06-23 12:50 ` [PATCH v2 3/4] interconnect: qcom: sm8550: " Neil Armstrong
` (3 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Neil Armstrong @ 2023-06-23 12:50 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Georgi Djakov
Cc: linux-arm-msm, linux-pm, linux-kernel, Neil Armstrong
Set the proper enable_mask to nodes requiring such value
to be used instead of a bandwidth when voting.
The masks were copied from the downstream implementation at [1].
[1] https://git.codelinaro.org/clo/la/kernel/msm-5.10/-/blob/KERNEL.PLATFORM.1.0.r2-05600-WAIPIOLE.0/drivers/interconnect/qcom/waipio.c
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
drivers/interconnect/qcom/sm8450.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/interconnect/qcom/sm8450.c b/drivers/interconnect/qcom/sm8450.c
index 2d7a8e7b85ec..e64c214b4020 100644
--- a/drivers/interconnect/qcom/sm8450.c
+++ b/drivers/interconnect/qcom/sm8450.c
@@ -1337,6 +1337,7 @@ static struct qcom_icc_node qns_mem_noc_sf_disp = {
static struct qcom_icc_bcm bcm_acv = {
.name = "ACV",
+ .enable_mask = 0x8,
.num_nodes = 1,
.nodes = { &ebi },
};
@@ -1349,6 +1350,7 @@ static struct qcom_icc_bcm bcm_ce0 = {
static struct qcom_icc_bcm bcm_cn0 = {
.name = "CN0",
+ .enable_mask = 0x1,
.keepalive = true,
.num_nodes = 55,
.nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie,
@@ -1383,6 +1385,7 @@ static struct qcom_icc_bcm bcm_cn0 = {
static struct qcom_icc_bcm bcm_co0 = {
.name = "CO0",
+ .enable_mask = 0x1,
.num_nodes = 2,
.nodes = { &qxm_nsp, &qns_nsp_gemnoc },
};
@@ -1403,6 +1406,7 @@ static struct qcom_icc_bcm bcm_mm0 = {
static struct qcom_icc_bcm bcm_mm1 = {
.name = "MM1",
+ .enable_mask = 0x1,
.num_nodes = 12,
.nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp,
&qnm_camnoc_sf, &qnm_mdp,
@@ -1445,6 +1449,7 @@ static struct qcom_icc_bcm bcm_sh0 = {
static struct qcom_icc_bcm bcm_sh1 = {
.name = "SH1",
+ .enable_mask = 0x1,
.num_nodes = 7,
.nodes = { &alm_gpu_tcu, &alm_sys_tcu,
&qnm_nsp_gemnoc, &qnm_pcie,
@@ -1461,6 +1466,7 @@ static struct qcom_icc_bcm bcm_sn0 = {
static struct qcom_icc_bcm bcm_sn1 = {
.name = "SN1",
+ .enable_mask = 0x1,
.num_nodes = 4,
.nodes = { &qhm_gic, &qxm_pimem,
&xm_gic, &qns_gemnoc_gc },
@@ -1492,6 +1498,7 @@ static struct qcom_icc_bcm bcm_sn7 = {
static struct qcom_icc_bcm bcm_acv_disp = {
.name = "ACV",
+ .enable_mask = 0x1,
.num_nodes = 1,
.nodes = { &ebi_disp },
};
@@ -1510,6 +1517,7 @@ static struct qcom_icc_bcm bcm_mm0_disp = {
static struct qcom_icc_bcm bcm_mm1_disp = {
.name = "MM1",
+ .enable_mask = 0x1,
.num_nodes = 3,
.nodes = { &qnm_mdp_disp, &qnm_rot_disp,
&qns_mem_noc_sf_disp },
@@ -1523,6 +1531,7 @@ static struct qcom_icc_bcm bcm_sh0_disp = {
static struct qcom_icc_bcm bcm_sh1_disp = {
.name = "SH1",
+ .enable_mask = 0x1,
.num_nodes = 1,
.nodes = { &qnm_pcie_disp },
};
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v2 2/4] interconnect: qcom: sm8450: add enable_mask for bcm nodes
2023-06-23 12:50 ` [PATCH v2 2/4] interconnect: qcom: sm8450: add enable_mask for bcm nodes Neil Armstrong
@ 2023-06-23 13:46 ` Konrad Dybcio
0 siblings, 0 replies; 13+ messages in thread
From: Konrad Dybcio @ 2023-06-23 13:46 UTC (permalink / raw)
To: Neil Armstrong, Andy Gross, Bjorn Andersson, Georgi Djakov
Cc: linux-arm-msm, linux-pm, linux-kernel
On 23.06.2023 14:50, Neil Armstrong wrote:
> Set the proper enable_mask to nodes requiring such value
> to be used instead of a bandwidth when voting.
>
> The masks were copied from the downstream implementation at [1].
>
> [1] https://git.codelinaro.org/clo/la/kernel/msm-5.10/-/blob/KERNEL.PLATFORM.1.0.r2-05600-WAIPIOLE.0/drivers/interconnect/qcom/waipio.c
>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> drivers/interconnect/qcom/sm8450.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/interconnect/qcom/sm8450.c b/drivers/interconnect/qcom/sm8450.c
> index 2d7a8e7b85ec..e64c214b4020 100644
> --- a/drivers/interconnect/qcom/sm8450.c
> +++ b/drivers/interconnect/qcom/sm8450.c
> @@ -1337,6 +1337,7 @@ static struct qcom_icc_node qns_mem_noc_sf_disp = {
>
> static struct qcom_icc_bcm bcm_acv = {
> .name = "ACV",
> + .enable_mask = 0x8,
> .num_nodes = 1,
> .nodes = { &ebi },
> };
> @@ -1349,6 +1350,7 @@ static struct qcom_icc_bcm bcm_ce0 = {
>
> static struct qcom_icc_bcm bcm_cn0 = {
> .name = "CN0",
> + .enable_mask = 0x1,
> .keepalive = true,
> .num_nodes = 55,
> .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie,
> @@ -1383,6 +1385,7 @@ static struct qcom_icc_bcm bcm_cn0 = {
>
> static struct qcom_icc_bcm bcm_co0 = {
> .name = "CO0",
> + .enable_mask = 0x1,
> .num_nodes = 2,
> .nodes = { &qxm_nsp, &qns_nsp_gemnoc },
> };
> @@ -1403,6 +1406,7 @@ static struct qcom_icc_bcm bcm_mm0 = {
>
> static struct qcom_icc_bcm bcm_mm1 = {
> .name = "MM1",
> + .enable_mask = 0x1,
> .num_nodes = 12,
> .nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp,
> &qnm_camnoc_sf, &qnm_mdp,
> @@ -1445,6 +1449,7 @@ static struct qcom_icc_bcm bcm_sh0 = {
>
> static struct qcom_icc_bcm bcm_sh1 = {
> .name = "SH1",
> + .enable_mask = 0x1,
> .num_nodes = 7,
> .nodes = { &alm_gpu_tcu, &alm_sys_tcu,
> &qnm_nsp_gemnoc, &qnm_pcie,
> @@ -1461,6 +1466,7 @@ static struct qcom_icc_bcm bcm_sn0 = {
>
> static struct qcom_icc_bcm bcm_sn1 = {
> .name = "SN1",
> + .enable_mask = 0x1,
> .num_nodes = 4,
> .nodes = { &qhm_gic, &qxm_pimem,
> &xm_gic, &qns_gemnoc_gc },
> @@ -1492,6 +1498,7 @@ static struct qcom_icc_bcm bcm_sn7 = {
>
> static struct qcom_icc_bcm bcm_acv_disp = {
> .name = "ACV",
> + .enable_mask = 0x1,
> .num_nodes = 1,
> .nodes = { &ebi_disp },
> };
> @@ -1510,6 +1517,7 @@ static struct qcom_icc_bcm bcm_mm0_disp = {
>
> static struct qcom_icc_bcm bcm_mm1_disp = {
> .name = "MM1",
> + .enable_mask = 0x1,
> .num_nodes = 3,
> .nodes = { &qnm_mdp_disp, &qnm_rot_disp,
> &qns_mem_noc_sf_disp },
> @@ -1523,6 +1531,7 @@ static struct qcom_icc_bcm bcm_sh0_disp = {
>
> static struct qcom_icc_bcm bcm_sh1_disp = {
> .name = "SH1",
> + .enable_mask = 0x1,
> .num_nodes = 1,
> .nodes = { &qnm_pcie_disp },
> };
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 3/4] interconnect: qcom: sm8550: add enable_mask for bcm nodes
2023-06-23 12:50 [PATCH v2 0/4] interconnect: qcom: rpmh: sm8550: mask to send as vote neil.armstrong
2023-06-23 12:50 ` [PATCH v2 1/4] interconnect: qcom: Add support for mask-based BCMs neil.armstrong
2023-06-23 12:50 ` [PATCH v2 2/4] interconnect: qcom: sm8450: add enable_mask for bcm nodes Neil Armstrong
@ 2023-06-23 12:50 ` Neil Armstrong
2023-06-23 12:50 ` [PATCH v2 4/4] interconnect: qcom: sa8775p: " Neil Armstrong
` (2 subsequent siblings)
5 siblings, 0 replies; 13+ messages in thread
From: Neil Armstrong @ 2023-06-23 12:50 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Georgi Djakov
Cc: linux-arm-msm, linux-pm, linux-kernel, Neil Armstrong
Set the proper enable_mask to nodes requiring such value
to be used instead of a bandwidth when voting.
The masks were copied from the downstream implementation at [1].
[1] https://git.codelinaro.org/clo/la/kernel/msm-5.15/-/blob/kernel.lnx.5.15.r1-rel/drivers/interconnect/qcom/kalama.c
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
drivers/interconnect/qcom/sm8550.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/interconnect/qcom/sm8550.c b/drivers/interconnect/qcom/sm8550.c
index d823ba988ef6..0864ed285375 100644
--- a/drivers/interconnect/qcom/sm8550.c
+++ b/drivers/interconnect/qcom/sm8550.c
@@ -1473,6 +1473,7 @@ static struct qcom_icc_node qns_mem_noc_sf_cam_ife_2 = {
static struct qcom_icc_bcm bcm_acv = {
.name = "ACV",
+ .enable_mask = 0x8,
.num_nodes = 1,
.nodes = { &ebi },
};
@@ -1485,6 +1486,7 @@ static struct qcom_icc_bcm bcm_ce0 = {
static struct qcom_icc_bcm bcm_cn0 = {
.name = "CN0",
+ .enable_mask = 0x1,
.keepalive = true,
.num_nodes = 54,
.nodes = { &qsm_cfg, &qhs_ahb2phy0,
@@ -1524,6 +1526,7 @@ static struct qcom_icc_bcm bcm_cn1 = {
static struct qcom_icc_bcm bcm_co0 = {
.name = "CO0",
+ .enable_mask = 0x1,
.num_nodes = 2,
.nodes = { &qxm_nsp, &qns_nsp_gemnoc },
};
@@ -1549,6 +1552,7 @@ static struct qcom_icc_bcm bcm_mm0 = {
static struct qcom_icc_bcm bcm_mm1 = {
.name = "MM1",
+ .enable_mask = 0x1,
.num_nodes = 8,
.nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp,
&qnm_camnoc_sf, &qnm_vapss_hcp,
@@ -1589,6 +1593,7 @@ static struct qcom_icc_bcm bcm_sh0 = {
static struct qcom_icc_bcm bcm_sh1 = {
.name = "SH1",
+ .enable_mask = 0x1,
.num_nodes = 13,
.nodes = { &alm_gpu_tcu, &alm_sys_tcu,
&chm_apps, &qnm_gpu,
@@ -1608,6 +1613,7 @@ static struct qcom_icc_bcm bcm_sn0 = {
static struct qcom_icc_bcm bcm_sn1 = {
.name = "SN1",
+ .enable_mask = 0x1,
.num_nodes = 3,
.nodes = { &qhm_gic, &xm_gic,
&qns_gemnoc_gc },
@@ -1633,6 +1639,7 @@ static struct qcom_icc_bcm bcm_sn7 = {
static struct qcom_icc_bcm bcm_acv_disp = {
.name = "ACV",
+ .enable_mask = 0x1,
.num_nodes = 1,
.nodes = { &ebi_disp },
};
@@ -1657,12 +1664,14 @@ static struct qcom_icc_bcm bcm_sh0_disp = {
static struct qcom_icc_bcm bcm_sh1_disp = {
.name = "SH1",
+ .enable_mask = 0x1,
.num_nodes = 2,
.nodes = { &qnm_mnoc_hf_disp, &qnm_pcie_disp },
};
static struct qcom_icc_bcm bcm_acv_cam_ife_0 = {
.name = "ACV",
+ .enable_mask = 0x0,
.num_nodes = 1,
.nodes = { &ebi_cam_ife_0 },
};
@@ -1681,6 +1690,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_0 = {
static struct qcom_icc_bcm bcm_mm1_cam_ife_0 = {
.name = "MM1",
+ .enable_mask = 0x1,
.num_nodes = 4,
.nodes = { &qnm_camnoc_hf_cam_ife_0, &qnm_camnoc_icp_cam_ife_0,
&qnm_camnoc_sf_cam_ife_0, &qns_mem_noc_sf_cam_ife_0 },
@@ -1694,6 +1704,7 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_0 = {
static struct qcom_icc_bcm bcm_sh1_cam_ife_0 = {
.name = "SH1",
+ .enable_mask = 0x1,
.num_nodes = 3,
.nodes = { &qnm_mnoc_hf_cam_ife_0, &qnm_mnoc_sf_cam_ife_0,
&qnm_pcie_cam_ife_0 },
@@ -1701,6 +1712,7 @@ static struct qcom_icc_bcm bcm_sh1_cam_ife_0 = {
static struct qcom_icc_bcm bcm_acv_cam_ife_1 = {
.name = "ACV",
+ .enable_mask = 0x0,
.num_nodes = 1,
.nodes = { &ebi_cam_ife_1 },
};
@@ -1719,6 +1731,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_1 = {
static struct qcom_icc_bcm bcm_mm1_cam_ife_1 = {
.name = "MM1",
+ .enable_mask = 0x1,
.num_nodes = 4,
.nodes = { &qnm_camnoc_hf_cam_ife_1, &qnm_camnoc_icp_cam_ife_1,
&qnm_camnoc_sf_cam_ife_1, &qns_mem_noc_sf_cam_ife_1 },
@@ -1732,6 +1745,7 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_1 = {
static struct qcom_icc_bcm bcm_sh1_cam_ife_1 = {
.name = "SH1",
+ .enable_mask = 0x1,
.num_nodes = 3,
.nodes = { &qnm_mnoc_hf_cam_ife_1, &qnm_mnoc_sf_cam_ife_1,
&qnm_pcie_cam_ife_1 },
@@ -1739,6 +1753,7 @@ static struct qcom_icc_bcm bcm_sh1_cam_ife_1 = {
static struct qcom_icc_bcm bcm_acv_cam_ife_2 = {
.name = "ACV",
+ .enable_mask = 0x0,
.num_nodes = 1,
.nodes = { &ebi_cam_ife_2 },
};
@@ -1757,6 +1772,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_2 = {
static struct qcom_icc_bcm bcm_mm1_cam_ife_2 = {
.name = "MM1",
+ .enable_mask = 0x1,
.num_nodes = 4,
.nodes = { &qnm_camnoc_hf_cam_ife_2, &qnm_camnoc_icp_cam_ife_2,
&qnm_camnoc_sf_cam_ife_2, &qns_mem_noc_sf_cam_ife_2 },
@@ -1770,6 +1786,7 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_2 = {
static struct qcom_icc_bcm bcm_sh1_cam_ife_2 = {
.name = "SH1",
+ .enable_mask = 0x1,
.num_nodes = 3,
.nodes = { &qnm_mnoc_hf_cam_ife_2, &qnm_mnoc_sf_cam_ife_2,
&qnm_pcie_cam_ife_2 },
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v2 4/4] interconnect: qcom: sa8775p: add enable_mask for bcm nodes
2023-06-23 12:50 [PATCH v2 0/4] interconnect: qcom: rpmh: sm8550: mask to send as vote neil.armstrong
` (2 preceding siblings ...)
2023-06-23 12:50 ` [PATCH v2 3/4] interconnect: qcom: sm8550: " Neil Armstrong
@ 2023-06-23 12:50 ` Neil Armstrong
2023-06-23 13:47 ` Konrad Dybcio
2023-06-23 13:58 ` [PATCH v2 0/4] interconnect: qcom: rpmh: sm8550: mask to send as vote Konrad Dybcio
2023-08-09 19:23 ` Konrad Dybcio
5 siblings, 1 reply; 13+ messages in thread
From: Neil Armstrong @ 2023-06-23 12:50 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Georgi Djakov
Cc: linux-arm-msm, linux-pm, linux-kernel, Neil Armstrong
Set the proper enable_mask the ACV node requiring such value
to be used instead of a bandwidth when voting.
The masks was copied from the downstream implementation at [1].
[1] https://git.codelinaro.org/clo/la/kernel/msm-5.15/-/blob/kernel.lnx.5.15.r32-rel/drivers/interconnect/qcom/lemans.c
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
drivers/interconnect/qcom/sa8775p.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/interconnect/qcom/sa8775p.c b/drivers/interconnect/qcom/sa8775p.c
index da21cc31a580..f56538669de0 100644
--- a/drivers/interconnect/qcom/sa8775p.c
+++ b/drivers/interconnect/qcom/sa8775p.c
@@ -1873,6 +1873,7 @@ static struct qcom_icc_node srvc_snoc = {
static struct qcom_icc_bcm bcm_acv = {
.name = "ACV",
+ .enable_mask = 0x8,
.num_nodes = 1,
.nodes = { &ebi },
};
--
2.34.1
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v2 4/4] interconnect: qcom: sa8775p: add enable_mask for bcm nodes
2023-06-23 12:50 ` [PATCH v2 4/4] interconnect: qcom: sa8775p: " Neil Armstrong
@ 2023-06-23 13:47 ` Konrad Dybcio
0 siblings, 0 replies; 13+ messages in thread
From: Konrad Dybcio @ 2023-06-23 13:47 UTC (permalink / raw)
To: Neil Armstrong, Andy Gross, Bjorn Andersson, Georgi Djakov
Cc: linux-arm-msm, linux-pm, linux-kernel
On 23.06.2023 14:50, Neil Armstrong wrote:
> Set the proper enable_mask the ACV node requiring such value
> to be used instead of a bandwidth when voting.
>
> The masks was copied from the downstream implementation at [1].
>
> [1] https://git.codelinaro.org/clo/la/kernel/msm-5.15/-/blob/kernel.lnx.5.15.r32-rel/drivers/interconnect/qcom/lemans.c
>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> drivers/interconnect/qcom/sa8775p.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/interconnect/qcom/sa8775p.c b/drivers/interconnect/qcom/sa8775p.c
> index da21cc31a580..f56538669de0 100644
> --- a/drivers/interconnect/qcom/sa8775p.c
> +++ b/drivers/interconnect/qcom/sa8775p.c
> @@ -1873,6 +1873,7 @@ static struct qcom_icc_node srvc_snoc = {
>
> static struct qcom_icc_bcm bcm_acv = {
> .name = "ACV",
> + .enable_mask = 0x8,
> .num_nodes = 1,
> .nodes = { &ebi },
> };
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 0/4] interconnect: qcom: rpmh: sm8550: mask to send as vote
2023-06-23 12:50 [PATCH v2 0/4] interconnect: qcom: rpmh: sm8550: mask to send as vote neil.armstrong
` (3 preceding siblings ...)
2023-06-23 12:50 ` [PATCH v2 4/4] interconnect: qcom: sa8775p: " Neil Armstrong
@ 2023-06-23 13:58 ` Konrad Dybcio
2023-06-23 18:58 ` Bjorn Andersson
2023-08-09 19:23 ` Konrad Dybcio
5 siblings, 1 reply; 13+ messages in thread
From: Konrad Dybcio @ 2023-06-23 13:58 UTC (permalink / raw)
To: neil.armstrong, Andy Gross, Bjorn Andersson, Georgi Djakov
Cc: linux-arm-msm, linux-pm, linux-kernel, Mike Tipton
On 23.06.2023 14:50, neil.armstrong@linaro.org wrote:
> On the SM8550 SoC, some nodes requires a specific bit mark
> instead of a bandwidth when voting.
>
> Add an enable_mask variable to be used instead of bandwidth.
>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
After reviewing this patchset and taking a peek at older downstream,
it looks like ACV should be using 0x8 bmask on *all RPMh SoCs*.
It's worth noting however, that 8350's downstream (the first msm
kernel using the icc framework) did not incorporate that change.
Not sure if intentionally or not. Probably not. Might be worth to
poke Qcom to backport it in such case. If 8350 is still supported.
Probably not.
Check out these snippets:
https://git.codelinaro.org/clo/la/kernel/msm-4.19/-/blob/LA.UM.10.2.1.c25/drivers/soc/qcom/msm_bus/msm_bus_arb_rpmh.c#L556-567
https://git.codelinaro.org/clo/la/kernel/msm-4.19/-/blob/LA.UM.10.2.1.c25/drivers/soc/qcom/msm_bus/msm_bus_arb_rpmh.c#L475-495
Notice how acv is never updated beyond effectively setting =0 or =bmask,
perhaps Qualcomm never implemented something else..
Since this series is fine as-is, I'd be happy to see an incremental one.
Reported-by would be cool as well :D
Konrad
> Changes in v2:
> - Took downstream patch for patch 1
> - Added konrad's reviewed tag
> - Added changes for sm8450 and sa8775p
> - Link to v1: https://lore.kernel.org/r/20230619-topic-sm8550-upstream-interconnect-mask-vote-v1-0-66663c0aa592@linaro.org
>
> ---
> Mike Tipton (1):
> interconnect: qcom: Add support for mask-based BCMs
>
> Neil Armstrong (3):
> interconnect: qcom: sm8450: add enable_mask for bcm nodes
> interconnect: qcom: sm8550: add enable_mask for bcm nodes
> interconnect: qcom: sa8775p: add enable_mask for bcm nodes
>
> drivers/interconnect/qcom/bcm-voter.c | 5 +++++
> drivers/interconnect/qcom/icc-rpmh.h | 2 ++
> drivers/interconnect/qcom/sa8775p.c | 1 +
> drivers/interconnect/qcom/sm8450.c | 9 +++++++++
> drivers/interconnect/qcom/sm8550.c | 17 +++++++++++++++++
> 5 files changed, 34 insertions(+)
> ---
> base-commit: 47045630bc409ce6606d97b790895210dd1d517d
> change-id: 20230619-topic-sm8550-upstream-interconnect-mask-vote-96aa20355158
>
> Best regards,
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v2 0/4] interconnect: qcom: rpmh: sm8550: mask to send as vote
2023-06-23 13:58 ` [PATCH v2 0/4] interconnect: qcom: rpmh: sm8550: mask to send as vote Konrad Dybcio
@ 2023-06-23 18:58 ` Bjorn Andersson
2023-06-23 20:07 ` Mike Tipton
0 siblings, 1 reply; 13+ messages in thread
From: Bjorn Andersson @ 2023-06-23 18:58 UTC (permalink / raw)
To: Konrad Dybcio
Cc: neil.armstrong, Andy Gross, Bjorn Andersson, Georgi Djakov,
linux-arm-msm, linux-pm, linux-kernel, Mike Tipton, Mike Tipton
On Fri, Jun 23, 2023 at 03:58:09PM +0200, Konrad Dybcio wrote:
> On 23.06.2023 14:50, neil.armstrong@linaro.org wrote:
> > On the SM8550 SoC, some nodes requires a specific bit mark
> > instead of a bandwidth when voting.
> >
> > Add an enable_mask variable to be used instead of bandwidth.
> >
> > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> > ---
> After reviewing this patchset and taking a peek at older downstream,
> it looks like ACV should be using 0x8 bmask on *all RPMh SoCs*.
>
> It's worth noting however, that 8350's downstream (the first msm
> kernel using the icc framework) did not incorporate that change.
> Not sure if intentionally or not. Probably not. Might be worth to
> poke Qcom to backport it in such case. If 8350 is still supported.
> Probably not.
>
Your observation is correct.
But, note further that command db reports ACV to have data-width of 0,
resulting in the numerator, and thereby vote_x and vote_y always being
0.
This is downstream worked around by:
https://git.codelinaro.org/clo/la/kernel/msm-5.15/-/commit/4d2818084015df1e05274ebcc5a0d21e6d256f93
Which should cause vote_x and vote_y to be non-zero. However without
this series (and enable_mask defined for ACV on all platforms) the votes
placed in the BCM would then be garbage...
That said, unless I'm missing something the math involved here is
unnecessary.For BCMs with enable_mask, if for any node sum_avg[bucket]
or max_peak[bucket] is non-zero then the calculated vote_x and vote_y
comes out non-zero and we write the mask, otherwise 0.
Rewritten to avoid all the unnecessary multiplication and divisions, we
wouldn't care about the unit or width and thereby don't need above
referenced patch.
A further tangent here is that a BCM with enable_mask != BIT(0) but
keepalive set, a 0-bandwidth vote in AMC would result in an invalid
(undefined?) BCM value being written out in the snippet below the loop.
> Check out these snippets:
>
> https://git.codelinaro.org/clo/la/kernel/msm-4.19/-/blob/LA.UM.10.2.1.c25/drivers/soc/qcom/msm_bus/msm_bus_arb_rpmh.c#L556-567
>
> https://git.codelinaro.org/clo/la/kernel/msm-4.19/-/blob/LA.UM.10.2.1.c25/drivers/soc/qcom/msm_bus/msm_bus_arb_rpmh.c#L475-495
>
> Notice how acv is never updated beyond effectively setting =0 or =bmask,
> perhaps Qualcomm never implemented something else..
>
> Since this series is fine as-is, I'd be happy to see an incremental one.
> Reported-by would be cool as well :D
I agree, let's get this merged, backported to stable, and then fix ACV
handling in a follow up commit (which doesn't necessarily need to hit
stable).
You should have a Jira card for this one already, but I don't mind
sharing the Reported-by with you ;)
Regards,
Bjorn
>
> Konrad
> > Changes in v2:
> > - Took downstream patch for patch 1
> > - Added konrad's reviewed tag
> > - Added changes for sm8450 and sa8775p
> > - Link to v1: https://lore.kernel.org/r/20230619-topic-sm8550-upstream-interconnect-mask-vote-v1-0-66663c0aa592@linaro.org
> >
> > ---
> > Mike Tipton (1):
> > interconnect: qcom: Add support for mask-based BCMs
> >
> > Neil Armstrong (3):
> > interconnect: qcom: sm8450: add enable_mask for bcm nodes
> > interconnect: qcom: sm8550: add enable_mask for bcm nodes
> > interconnect: qcom: sa8775p: add enable_mask for bcm nodes
> >
> > drivers/interconnect/qcom/bcm-voter.c | 5 +++++
> > drivers/interconnect/qcom/icc-rpmh.h | 2 ++
> > drivers/interconnect/qcom/sa8775p.c | 1 +
> > drivers/interconnect/qcom/sm8450.c | 9 +++++++++
> > drivers/interconnect/qcom/sm8550.c | 17 +++++++++++++++++
> > 5 files changed, 34 insertions(+)
> > ---
> > base-commit: 47045630bc409ce6606d97b790895210dd1d517d
> > change-id: 20230619-topic-sm8550-upstream-interconnect-mask-vote-96aa20355158
> >
> > Best regards,
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 0/4] interconnect: qcom: rpmh: sm8550: mask to send as vote
2023-06-23 18:58 ` Bjorn Andersson
@ 2023-06-23 20:07 ` Mike Tipton
0 siblings, 0 replies; 13+ messages in thread
From: Mike Tipton @ 2023-06-23 20:07 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio
Cc: neil.armstrong, Andy Gross, Bjorn Andersson, Georgi Djakov,
linux-arm-msm, linux-pm, linux-kernel
On 6/23/2023 11:58 AM, Bjorn Andersson wrote:
> On Fri, Jun 23, 2023 at 03:58:09PM +0200, Konrad Dybcio wrote:
>> On 23.06.2023 14:50, neil.armstrong@linaro.org wrote:
>>> On the SM8550 SoC, some nodes requires a specific bit mark
>>> instead of a bandwidth when voting.
>>>
>>> Add an enable_mask variable to be used instead of bandwidth.
>>>
>>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>>> ---
>> After reviewing this patchset and taking a peek at older downstream,
>> it looks like ACV should be using 0x8 bmask on *all RPMh SoCs*.
>>
>> It's worth noting however, that 8350's downstream (the first msm
>> kernel using the icc framework) did not incorporate that change.
>> Not sure if intentionally or not. Probably not. Might be worth to
>> poke Qcom to backport it in such case. If 8350 is still supported.
>> Probably not.
>>
>
> Your observation is correct.
Mostly correct. Historically it's always been 0x8, but it's not
guaranteed. And it will be different on some upcoming SoCs.
>
> But, note further that command db reports ACV to have data-width of 0,
> resulting in the numerator, and thereby vote_x and vote_y always being
> 0.
>
> This is downstream worked around by:
> https://git.codelinaro.org/clo/la/kernel/msm-5.15/-/commit/4d2818084015df1e05274ebcc5a0d21e6d256f93
>
> Which should cause vote_x and vote_y to be non-zero. However without
> this series (and enable_mask defined for ACV on all platforms) the votes
> placed in the BCM would then be garbage...
>
>
>
> That said, unless I'm missing something the math involved here is
> unnecessary.For BCMs with enable_mask, if for any node sum_avg[bucket]
> or max_peak[bucket] is non-zero then the calculated vote_x and vote_y
> comes out non-zero and we write the mask, otherwise 0.
You're not missing anything. The full aggregation logic isn't necessary
for BCMs with an enable_mask. It was just a bit simpler to implement
this way. And the extra time spent in the aggregation logic should be
minimal. But, it could certainly be rewritten to have an entirely
separate, simpler "aggregation" loop than the full BCMs.
>
> Rewritten to avoid all the unnecessary multiplication and divisions, we
> wouldn't care about the unit or width and thereby don't need above
> referenced patch.
Yeah, the patch shouldn't be necessary anymore in that case. Though
keeping it would protect us against div-by-zero in case of something
unexpected in cmd_db.
>
>
> A further tangent here is that a BCM with enable_mask != BIT(0) but
> keepalive set, a 0-bandwidth vote in AMC would result in an invalid
> (undefined?) BCM value being written out in the snippet below the loop.
True, though in practice it should never be a problem. Currently, there
are only two use cases for enable_mask -- "on/off" BCMs and ACV. The
enable_mask for on/off BCMs is always 0x1. The only time enable_mask !=
0x1 is for ACV, but keepalive should never be set for ACV. I agree this
is a bit of a logical hole, though. And could break in the future for
as-yet undefined usage of enable_mask.
>
>> Check out these snippets:
>>
>> https://git.codelinaro.org/clo/la/kernel/msm-4.19/-/blob/LA.UM.10.2.1.c25/drivers/soc/qcom/msm_bus/msm_bus_arb_rpmh.c#L556-567
>>
>> https://git.codelinaro.org/clo/la/kernel/msm-4.19/-/blob/LA.UM.10.2.1.c25/drivers/soc/qcom/msm_bus/msm_bus_arb_rpmh.c#L475-495
>>
>> Notice how acv is never updated beyond effectively setting =0 or =bmask,
>> perhaps Qualcomm never implemented something else..
>>
>> Since this series is fine as-is, I'd be happy to see an incremental one.
>> Reported-by would be cool as well :D
>
> I agree, let's get this merged, backported to stable, and then fix ACV
> handling in a follow up commit (which doesn't necessarily need to hit
> stable).
>
> You should have a Jira card for this one already, but I don't mind
> sharing the Reported-by with you ;)
>
> Regards,
> Bjorn
>
>>
>> Konrad
>>> Changes in v2:
>>> - Took downstream patch for patch 1
>>> - Added konrad's reviewed tag
>>> - Added changes for sm8450 and sa8775p
>>> - Link to v1: https://lore.kernel.org/r/20230619-topic-sm8550-upstream-interconnect-mask-vote-v1-0-66663c0aa592@linaro.org
>>>
>>> ---
>>> Mike Tipton (1):
>>> interconnect: qcom: Add support for mask-based BCMs
>>>
>>> Neil Armstrong (3):
>>> interconnect: qcom: sm8450: add enable_mask for bcm nodes
>>> interconnect: qcom: sm8550: add enable_mask for bcm nodes
>>> interconnect: qcom: sa8775p: add enable_mask for bcm nodes
>>>
>>> drivers/interconnect/qcom/bcm-voter.c | 5 +++++
>>> drivers/interconnect/qcom/icc-rpmh.h | 2 ++
>>> drivers/interconnect/qcom/sa8775p.c | 1 +
>>> drivers/interconnect/qcom/sm8450.c | 9 +++++++++
>>> drivers/interconnect/qcom/sm8550.c | 17 +++++++++++++++++
>>> 5 files changed, 34 insertions(+)
>>> ---
>>> base-commit: 47045630bc409ce6606d97b790895210dd1d517d
>>> change-id: 20230619-topic-sm8550-upstream-interconnect-mask-vote-96aa20355158
>>>
>>> Best regards,
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 0/4] interconnect: qcom: rpmh: sm8550: mask to send as vote
2023-06-23 12:50 [PATCH v2 0/4] interconnect: qcom: rpmh: sm8550: mask to send as vote neil.armstrong
` (4 preceding siblings ...)
2023-06-23 13:58 ` [PATCH v2 0/4] interconnect: qcom: rpmh: sm8550: mask to send as vote Konrad Dybcio
@ 2023-08-09 19:23 ` Konrad Dybcio
2023-08-09 20:24 ` Georgi Djakov
5 siblings, 1 reply; 13+ messages in thread
From: Konrad Dybcio @ 2023-08-09 19:23 UTC (permalink / raw)
To: neil.armstrong, Andy Gross, Bjorn Andersson, Georgi Djakov
Cc: linux-arm-msm, linux-pm, linux-kernel, Mike Tipton
On 23.06.2023 14:50, neil.armstrong@linaro.org wrote:
> On the SM8550 SoC, some nodes requires a specific bit mark
> instead of a bandwidth when voting.
>
> Add an enable_mask variable to be used instead of bandwidth.
>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
Georgi,
please pick this up and I'll fix up the ACV situation mentioned
by Bjorn as an incremental change.
Konrad
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v2 0/4] interconnect: qcom: rpmh: sm8550: mask to send as vote
2023-08-09 19:23 ` Konrad Dybcio
@ 2023-08-09 20:24 ` Georgi Djakov
0 siblings, 0 replies; 13+ messages in thread
From: Georgi Djakov @ 2023-08-09 20:24 UTC (permalink / raw)
To: Konrad Dybcio, neil.armstrong, Andy Gross, Bjorn Andersson
Cc: linux-arm-msm, linux-pm, linux-kernel, Mike Tipton
On 9.08.23 22:23, Konrad Dybcio wrote:
> On 23.06.2023 14:50, neil.armstrong@linaro.org wrote:
>> On the SM8550 SoC, some nodes requires a specific bit mark
>> instead of a bandwidth when voting.
>>
>> Add an enable_mask variable to be used instead of bandwidth.
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>> ---
> Georgi,
>
> please pick this up and I'll fix up the ACV situation mentioned
> by Bjorn as an incremental change.
>
> Konrad
Thanks Konrad! I had sent it to Greg last week, so it will get into
Torvalds tree most likely this week.
BR,
Georgi
^ permalink raw reply [flat|nested] 13+ messages in thread