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Tue, 16 Sep 2025 07:28:28 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEXZ/OLgiEOc7ZsA33aPYfpDR5hJxcewlrm4+2ZHd+0WezSt0QCPDrGqDniIYPdLk4UlZzVgg== X-Received: by 2002:a17:903:230a:b0:267:e8a9:7e72 with SMTP id d9443c01a7336-267e8a98193mr20321365ad.12.1758032907504; Tue, 16 Sep 2025 07:28:27 -0700 (PDT) Received: from [10.217.217.28] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2651d2df15esm73585485ad.45.2025.09.16.07.28.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 16 Sep 2025 07:28:27 -0700 (PDT) Message-ID: <5d662148-408f-49e1-a769-2a5d61371cae@oss.qualcomm.com> Date: Tue, 16 Sep 2025 19:58:18 +0530 Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V7 3/5] dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC To: Krzysztof Kozlowski Cc: jic23@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, agross@kernel.org, andersson@kernel.org, lumag@kernel.org, dmitry.baryshkov@oss.qualcomm.com, konradybcio@kernel.org, daniel.lezcano@linaro.org, sboyd@kernel.org, amitk@kernel.org, thara.gopinath@gmail.com, lee@kernel.org, rafael@kernel.org, subbaraman.narayanamurthy@oss.qualcomm.com, david.collins@oss.qualcomm.com, anjelique.melendez@oss.qualcomm.com, kamal.wadhwa@oss.qualcomm.com, rui.zhang@intel.com, lukasz.luba@arm.com, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, cros-qcom-dts-watchers@chromium.org, quic_kotarake@quicinc.com, neil.armstrong@linaro.org, stephan.gerhold@linaro.org, Jonathan Cameron References: <20250826083657.4005727-1-jishnu.prakash@oss.qualcomm.com> <20250826083657.4005727-4-jishnu.prakash@oss.qualcomm.com> <20250829-classic-dynamic-clam-addbd8@kuoka> Content-Language: en-US From: Jishnu Prakash In-Reply-To: <20250829-classic-dynamic-clam-addbd8@kuoka> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: zqohaoXKch5ny-0DGPdTGAi8uEJbuUYK X-Proofpoint-ORIG-GUID: zqohaoXKch5ny-0DGPdTGAi8uEJbuUYK X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTE2MDAxMCBTYWx0ZWRfX6ZdoAdSBgkZ9 1EvyENScQFU4YTCbHnswsAzfMyTRGPIhdwWljlw+VX96CZlYC7hOVxSUK/xYbhXGZD7PPuZc89v V8Hud//ECqm4LgrDm0+6ry0SA9dM9BJwYiVh8h5CmEmuFTGtyIJLVqC+OYECcoxe+V5NmLUMfWx /i9ZmsuVLT1LuwSaBqSCpZIS5KCho0c7uB5m1K3V58bFVs5bgWTt5wSNahrxv/TNVaXdgXelPFO skzT2TFBZ0vCSDwV2ekTPTF1je4a8a68DmzVvP5GjMXEBXiV07iAa5iZ2bULNEic2ojL5453Rl2 ykBZLDCm9p+5B/qwjw65HyT+7UFXY5T/CiCxVwjeJVkfh+3ddS/YxGs2OPLjb8yoMpIvVP78fPz YbAFbjXq X-Authority-Analysis: v=2.4 cv=WpQrMcfv c=1 sm=1 tr=0 ts=68c9740d cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=i0EeH86SAAAA:8 a=EUspDBNiAAAA:8 a=NBYwllkvtaGzK6LsQGIA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-16_02,2025-09-12_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 adultscore=0 phishscore=0 bulkscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509160010 Hi Krzysztof, On 8/29/2025 12:49 PM, Krzysztof Kozlowski wrote: > On Tue, Aug 26, 2025 at 02:06:55PM +0530, Jishnu Prakash wrote: >> For the PMIC5-Gen3 type PMICs, ADC peripheral is present in HW for the >> following PMICs: PMK8550, PM8550, PM8550B and PM8550VX PMICs. >> >> It is similar to PMIC5-Gen2, with SW communication to ADCs on all PMICs >> going through PBS(Programmable Boot Sequence) firmware through a single >> register interface. This interface is implemented on SDAM (Shared >> Direct Access Memory) peripherals on the master PMIC PMK8550 rather >> than a dedicated ADC peripheral. >> >> Add documentation for PMIC5 Gen3 ADC and macro definitions for ADC >> channels and virtual channels (combination of ADC channel number and >> PMIC SID number) per PMIC, to be used by clients of this device. Also >> update SPMI PMIC bindings to allow ADC5 Gen3 as adc@ subnode. >> >> Acked-by: Jonathan Cameron >> Signed-off-by: Jishnu Prakash >> --- >> Changes since v6: >> - Updated SPMI PMIC bindings to allow ADC5 Gen3 as adc@ subnode and >> copyright license in newly added files. > > So you did not implement my requests/comments from v5? I did not request > above, I had many, many other comments. > > In my v6 patch, I had implemented all the changes you requested in my v5 patch, that is what I had meant by the last part ('addressed other reviewer comments'). I will update the below section when pushing my next patch series to list out all the changes explicitly. > >> >> Changes since v5: >> - Added more details in binding description explaining how number >> of SDAM peripherals used for ADC is allocated per SoC. >> - Renamed per-PMIC binding files listing ADC channel macro names >> and addressed other reviewer comments. >> >> Changes since v4: >> - Added ADC5 Gen3 documentation in a separate new file to avoid complicating >> existing VADC documentation file further to accomodate this device, as >> suggested by reviewer. >> >> Changes since v3: >> - Added ADC5 Gen3 documentation changes in existing qcom,spmi-vadc.yaml file >> instead of adding separate file and updated top-level constraints in documentation >> file based on discussion with reviewers. >> - Dropped default SID definitions. >> - Addressed other reviewer comments. >> >> Changes since v2: >> - Moved ADC5 Gen3 documentation into a separate new file. >> ... >> + >> + The interface is implemented on SDAM (Shared Direct Access Memory) peripherals >> + on the master PMIC rather than a dedicated ADC peripheral. The number of PMIC >> + SDAM peripherals allocated for ADC is not correlated with the PMIC used, it is >> + programmed in FW (PBS) and is fixed per SOC, based on the SOC requirements. >> + All boards using a particular (SOC + master PMIC) combination will have the >> + same number of ADC SDAMs supported on that PMIC. >> + >> +properties: >> + compatible: >> + const: qcom,spmi-adc5-gen3 >> + >> + reg: >> + items: >> + - description: SDAM0 base address in the SPMI PMIC register map >> + - description: SDAM1 base address >> + minItems: 1 >> + >> + '#address-cells': >> + const: 1 >> + >> + '#size-cells': >> + const: 0 >> + >> + '#io-channel-cells': >> + const: 1 >> + >> + "#thermal-sensor-cells": > > Nothing improved here, still mess with quotes. I will fix this and check for any other things to fix before pushing the next patch. > > I am not going to check the rest of comments, because: > 1. Your changelog is vague and claims you did not implement them, > 2. b4 diff does not work, base-commit is unknown. > 3. Main changelog is even more vague. > > You make it difficult for us to review your patches, fine. You will get: > > NAK (plus one more comment below) > >> diff --git a/include/dt-bindings/iio/adc/qcom,spmi-vadc.h b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h >> index ef07ecd4d585..b1b89e874316 100644 >> --- a/include/dt-bindings/iio/adc/qcom,spmi-vadc.h >> +++ b/include/dt-bindings/iio/adc/qcom,spmi-vadc.h >> @@ -300,4 +300,83 @@ >> #define ADC7_SBUx 0x94 >> #define ADC7_VBAT_2S_MID 0x96 >> >> +/* ADC channels for PMIC5 Gen3 */ >> + >> +#define ADC5_GEN3_REF_GND 0x00 >> +#define ADC5_GEN3_1P25VREF 0x01 >> +#define ADC5_GEN3_VREF_VADC 0x02 >> +#define ADC5_GEN3_DIE_TEMP 0x03 >> + >> +#define ADC5_GEN3_AMUX1_THM 0x04 >> +#define ADC5_GEN3_AMUX2_THM 0x05 >> +#define ADC5_GEN3_AMUX3_THM 0x06 >> +#define ADC5_GEN3_AMUX4_THM 0x07 >> +#define ADC5_GEN3_AMUX5_THM 0x08 >> +#define ADC5_GEN3_AMUX6_THM 0x09 >> +#define ADC5_GEN3_AMUX1_GPIO 0x0a >> +#define ADC5_GEN3_AMUX2_GPIO 0x0b >> +#define ADC5_GEN3_AMUX3_GPIO 0x0c >> +#define ADC5_GEN3_AMUX4_GPIO 0x0d >> + >> +#define ADC5_GEN3_CHG_TEMP 0x10 >> +#define ADC5_GEN3_USB_SNS_V_16 0x11 >> +#define ADC5_GEN3_VIN_DIV16_MUX 0x12 >> +#define ADC5_GEN3_VREF_BAT_THERM 0x15 > > You cannot have empty spaces in ID constants. These are abstract > numbers. > > Otherwise please point me to driver using this constant. These constants are for ADC channel numbers, which are fixed in HW. They are used in this driver: drivers/iio/adc/qcom-spmi-adc5-gen3.c, which is added in patch 4 of this series. They can be found in the array named adc5_gen3_chans_pmic[]. Thanks, Jishnu > > Best regards, > Krzysztof >