From: neil.armstrong@linaro.org
To: Mike Tipton <quic_mdtipton@quicinc.com>,
andersson@kernel.org, konrad.dybcio@linaro.org,
djakov@kernel.org
Cc: quic_rjendra@quicinc.com, quic_sibis@quicinc.com,
abel.vesa@linaro.org, linux-arm-msm@vger.kernel.org,
linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/2] interconnect: qcom: sm8650: Use correct ACV enable_mask
Date: Sat, 3 Feb 2024 15:49:21 +0100 [thread overview]
Message-ID: <6e9030cc-3431-45c5-a7a8-0da02bafab09@linaro.org> (raw)
In-Reply-To: <20240202014806.7876-2-quic_mdtipton@quicinc.com>
On 02/02/2024 02:48, Mike Tipton wrote:
> The ACV enable_mask is historically BIT(3), but it's BIT(0) on this
> target. Fix it.
>
> Fixes: c062bcab5924 ("interconnect: qcom: introduce RPMh Network-On-Chip Interconnect on SM8650 SoC")
> Signed-off-by: Mike Tipton <quic_mdtipton@quicinc.com>
> ---
> drivers/interconnect/qcom/sm8650.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/interconnect/qcom/sm8650.c b/drivers/interconnect/qcom/sm8650.c
> index b83de54577b6..b962e6c233ef 100644
> --- a/drivers/interconnect/qcom/sm8650.c
> +++ b/drivers/interconnect/qcom/sm8650.c
> @@ -1160,7 +1160,7 @@ static struct qcom_icc_node qns_gemnoc_sf = {
>
> static struct qcom_icc_bcm bcm_acv = {
> .name = "ACV",
> - .enable_mask = BIT(3),
> + .enable_mask = BIT(0),
> .num_nodes = 1,
> .nodes = { &ebi },
> };
Indeed it changed in the meantime
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
next prev parent reply other threads:[~2024-02-03 14:49 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-02 1:48 [PATCH 0/2] interconnect: qcom: ACV enable_mask fixes Mike Tipton
2024-02-02 1:48 ` [PATCH 1/2] interconnect: qcom: sm8650: Use correct ACV enable_mask Mike Tipton
2024-02-02 11:29 ` Konrad Dybcio
2024-02-03 14:49 ` neil.armstrong [this message]
2024-02-02 1:48 ` [PATCH 2/2] interconnect: qcom: x1e80100: Add missing " Mike Tipton
2024-02-02 11:30 ` Konrad Dybcio
2024-02-02 16:57 ` Abel Vesa
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