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Peter Anvin" , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , Peter Zijlstra , Sean Christopherson , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Tony Luck , Paolo Bonzini , Vitaly Kuznetsov , "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Steven Rostedt , Masami Hiramatsu , Mathieu Desnoyers , Brian Gerst , Andrew Cooper , "Kirill A . Shutemov" , Jacob Pan , Andi Kleen , Kai Huang , Nikolay Borisov , linux-perf-users@vger.kernel.org, linux-edac@vger.kernel.org, kvm@vger.kernel.org, linux-pm@vger.kernel.org, linux-trace-kernel@vger.kernel.org References: <20250507012145.2998143-1-sohil.mehta@intel.com> <20250507012145.2998143-9-sohil.mehta@intel.com> Content-Language: en-US From: Sandipan Das In-Reply-To: <20250507012145.2998143-9-sohil.mehta@intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-ClientProxiedBy: PN4P287CA0039.INDP287.PROD.OUTLOOK.COM (2603:1096:c01:271::13) To PH7PR12MB5712.namprd12.prod.outlook.com (2603:10b6:510:1e3::13) Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH7PR12MB5712:EE_|PH7PR12MB8178:EE_ X-MS-Office365-Filtering-Correlation-Id: 768430fa-11fe-4a71-167d-08dd8e225454 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|376014|7416014|7053199007; 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An NMI for the PMU would directly invoke the PMI handler > without polling other NMI handlers, resulting in reduced PMI delivery > latency. > > Co-developed-by: Zeng Guang > Signed-off-by: Zeng Guang > Signed-off-by: Jacob Pan > Signed-off-by: Sohil Mehta > Reviewed-by: Kan Liang > --- > v5: No significant change. > --- > arch/x86/events/core.c | 4 ++-- > arch/x86/events/intel/core.c | 6 +++--- > arch/x86/include/asm/apic.h | 1 + > 3 files changed, 6 insertions(+), 5 deletions(-) > > diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c > index 031e908f0d61..42b270526631 100644 > --- a/arch/x86/events/core.c > +++ b/arch/x86/events/core.c > @@ -1695,7 +1695,7 @@ int x86_pmu_handle_irq(struct pt_regs *regs) > * This generic handler doesn't seem to have any issues where the > * unmasking occurs so it was left at the top. > */ > - apic_write(APIC_LVTPC, APIC_DM_NMI); > + apic_write(APIC_LVTPC, PERF_NMI); > > for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { > if (!test_bit(idx, cpuc->active_mask)) > @@ -1737,7 +1737,7 @@ void perf_events_lapic_init(void) > /* > * Always use NMI for PMU > */ > - apic_write(APIC_LVTPC, APIC_DM_NMI); > + apic_write(APIC_LVTPC, PERF_NMI); > } > > static int > diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c > index 09d2d66c9f21..87c624686c58 100644 > --- a/arch/x86/events/intel/core.c > +++ b/arch/x86/events/intel/core.c > @@ -3202,7 +3202,7 @@ static int intel_pmu_handle_irq(struct pt_regs *regs) > * NMI handler. > */ > if (!late_ack && !mid_ack) > - apic_write(APIC_LVTPC, APIC_DM_NMI); > + apic_write(APIC_LVTPC, PERF_NMI); > intel_bts_disable_local(); > cpuc->enabled = 0; > __intel_pmu_disable_all(true); > @@ -3239,7 +3239,7 @@ static int intel_pmu_handle_irq(struct pt_regs *regs) > > done: > if (mid_ack) > - apic_write(APIC_LVTPC, APIC_DM_NMI); > + apic_write(APIC_LVTPC, PERF_NMI); > /* Only restore PMU state when it's active. See x86_pmu_disable(). */ > cpuc->enabled = pmu_enabled; > if (pmu_enabled) > @@ -3252,7 +3252,7 @@ static int intel_pmu_handle_irq(struct pt_regs *regs) > * Haswell CPUs. > */ > if (late_ack) > - apic_write(APIC_LVTPC, APIC_DM_NMI); > + apic_write(APIC_LVTPC, PERF_NMI); > return handled; > } > > diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h > index 9bade39b5feb..b2f864e77d84 100644 > --- a/arch/x86/include/asm/apic.h > +++ b/arch/x86/include/asm/apic.h > @@ -29,6 +29,7 @@ > #define BT_NMI (APIC_DM_NMI | NMIS_VECTOR_BT) > #define KGDB_NMI (APIC_DM_NMI | NMIS_VECTOR_KGDB) > #define MCE_NMI (APIC_DM_NMI | NMIS_VECTOR_MCE) > +#define PERF_NMI (APIC_DM_NMI | NMIS_VECTOR_PMI) > > /* > * Debugging macros For AMD processors that do not support NMI source reporting but use x86_pmu_handle_irq() and perf_events_lapic_init() Tested-by: Sandipan Das