From: Daniel Lezcano <daniel.lezcano@linaro.org>
To: Balsam CHIHI <bchihi@baylibre.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>
Cc: rafael@kernel.org, amitk@kernel.org, rui.zhang@intel.com,
linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org,
khilman@baylibre.com, linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, james.lo@mediatek.com,
rex-bc.chen@mediatek.com
Subject: Re: [PATCH v10 4/6] thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver
Date: Wed, 18 Jan 2023 15:30:34 +0100 [thread overview]
Message-ID: <71e5c68a-dbc7-caac-d6d4-5a8cd5b20d5e@linaro.org> (raw)
In-Reply-To: <CAGuA+ooxTf-j957gQ1zRe2-+u2kphaaLGvTDi1=kit5Q3bKOxA@mail.gmail.com>
Hi Balsam,
On 18/01/2023 14:58, Balsam CHIHI wrote:
[ ... ]
>> You're describing the register with nice words, but there's another way to do
>> the same that will be even more effective.
>>
>> /*
>> * LVTS MONINT: Interrupt Monitoring register
>> * Each bit describes the enable status of per-sensor interrupts.
>> */
>> #define LVTS_MONINT_THRES_COLD BIT(0) /* Cold threshold */
>> #define LVTS_MONINT_THRES_HOT BIT(1) /* Hot threshold */
>> #define LVTS_MONINT_OFFST_LOW BIT(2) /* Low offset */
>> #define LVTS_MONINT_OFFST_HIGH BIT(3) /* High offset */
>> #define LVTS_MONINT_OFFST_NTH BIT(4) /* Normal To Hot */
>> #define EVERYTHING_ELSE ........................
>>
>> #define LVTS_MONINT_SNS0_MASK GENMASK( ... )
>> #define LVTS_MONINT_SNS1_MASK GENMASK .....
>>
>> /* Find a better name for this one */
>> #define LVTS_MONINT_EN_IRQS ( LVTS_MONINT_THRES_COLD | LVTS_MONINT_THRES_HOT |
>> LVTS_MONINT_OFFST_LOW ..... etc etc)
>>
>
> Given the complexity of the controller and the number of registers,
> if we create a define per bits, we will end up with a huge list of
> defines (~300).
Yeah, that is too much for a little gain.
However, a few can be added for the interrupt only.
Instead of LVTS_MONINT_THRES ..., it could be LVTS_INT_THRES_... and
reused for LVTS_MONINTSTS and LVTS_MONINT setup as the bits position are
the same?
[ ... ]
>>> +static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_ctrl)
>>> +{
>>> + u32 period_unit = (118 * 1000) / (256 * 38);
>>
>> #define SOMETHING 118
>> #define SOMETHING_ELSE 1000
>> #define ....
>>
>> const u32 period_unit = (SOMETHING * SOMETHING_ELSE) / ....
>>
>
> Constifying "u32 period_unit" generates the following compilation warning :
> ./include/asm-generic/io.h:273:61: note: expected ‘volatile void *’
> but argument is of type ‘const void *’
> 273 | static inline void writel(u32 value, volatile void __iomem *addr)
> | ~~~~~~~~~~~~~~~~~~~~~~~^~~~
That is strange. period_unit is the 'value', not the 'addr'. Are you
sure about the warning?
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
next prev parent reply other threads:[~2023-01-18 14:40 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-12 15:28 [PATCH v10 0/6] Add LVTS thermal architecture bchihi
2023-01-12 15:28 ` [PATCH v10 1/6] thermal/drivers/mediatek: Relocate driver to mediatek folder bchihi
[not found] ` <202301130353.wbXPctIq-lkp@intel.com>
2023-01-13 10:47 ` Daniel Lezcano
2023-01-12 15:28 ` [PATCH v10 2/6] dt-bindings/thermal/mediatek: Add dt-binding document for LVTS thermal controllers bchihi
2023-01-13 8:11 ` Krzysztof Kozlowski
2023-01-13 11:54 ` Matthias Brugger
2023-01-13 14:30 ` Balsam CHIHI
2023-01-16 10:38 ` AngeloGioacchino Del Regno
2023-01-16 11:05 ` Balsam CHIHI
2023-01-12 15:28 ` [PATCH v10 3/6] arm64/dts/mt8195: Add efuse node to mt8195 bchihi
2023-01-13 11:45 ` Matthias Brugger
2023-01-16 10:38 ` AngeloGioacchino Del Regno
2023-01-12 15:28 ` [PATCH v10 4/6] thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver bchihi
2023-01-16 10:50 ` AngeloGioacchino Del Regno
2023-01-16 11:08 ` Daniel Lezcano
2023-01-16 11:52 ` AngeloGioacchino Del Regno
2023-01-18 13:58 ` Balsam CHIHI
2023-01-18 14:30 ` Daniel Lezcano [this message]
2023-01-18 14:52 ` Balsam CHIHI
2023-01-18 14:37 ` Balsam CHIHI
2023-01-12 15:28 ` [PATCH v10 5/6] arm64/dts/mt8195: Add thermal zones and thermal nodes bchihi
2023-01-12 15:28 ` [PATCH v10 6/6] arm64/dts/mt8195: Add temperature mitigation threshold bchihi
2023-01-13 11:49 ` Matthias Brugger
2023-01-13 14:24 ` Balsam CHIHI
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=71e5c68a-dbc7-caac-d6d4-5a8cd5b20d5e@linaro.org \
--to=daniel.lezcano@linaro.org \
--cc=amitk@kernel.org \
--cc=angelogioacchino.delregno@collabora.com \
--cc=bchihi@baylibre.com \
--cc=james.lo@mediatek.com \
--cc=khilman@baylibre.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=linux-pm@vger.kernel.org \
--cc=rafael@kernel.org \
--cc=rex-bc.chen@mediatek.com \
--cc=rui.zhang@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).