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[130.180.211.218]) by smtp.googlemail.com with ESMTPSA id l23-20020a05600c1d1700b003db0dbbea53sm2418963wms.30.2023.01.18.06.30.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 18 Jan 2023 06:30:35 -0800 (PST) Message-ID: <71e5c68a-dbc7-caac-d6d4-5a8cd5b20d5e@linaro.org> Date: Wed, 18 Jan 2023 15:30:34 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH v10 4/6] thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver Content-Language: en-US To: Balsam CHIHI , AngeloGioacchino Del Regno Cc: rafael@kernel.org, amitk@kernel.org, rui.zhang@intel.com, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, rex-bc.chen@mediatek.com References: <20230112152855.216072-1-bchihi@baylibre.com> <20230112152855.216072-5-bchihi@baylibre.com> From: Daniel Lezcano In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Hi Balsam, On 18/01/2023 14:58, Balsam CHIHI wrote: [ ... ] >> You're describing the register with nice words, but there's another way to do >> the same that will be even more effective. >> >> /* >> * LVTS MONINT: Interrupt Monitoring register >> * Each bit describes the enable status of per-sensor interrupts. >> */ >> #define LVTS_MONINT_THRES_COLD BIT(0) /* Cold threshold */ >> #define LVTS_MONINT_THRES_HOT BIT(1) /* Hot threshold */ >> #define LVTS_MONINT_OFFST_LOW BIT(2) /* Low offset */ >> #define LVTS_MONINT_OFFST_HIGH BIT(3) /* High offset */ >> #define LVTS_MONINT_OFFST_NTH BIT(4) /* Normal To Hot */ >> #define EVERYTHING_ELSE ........................ >> >> #define LVTS_MONINT_SNS0_MASK GENMASK( ... ) >> #define LVTS_MONINT_SNS1_MASK GENMASK ..... >> >> /* Find a better name for this one */ >> #define LVTS_MONINT_EN_IRQS ( LVTS_MONINT_THRES_COLD | LVTS_MONINT_THRES_HOT | >> LVTS_MONINT_OFFST_LOW ..... etc etc) >> > > Given the complexity of the controller and the number of registers, > if we create a define per bits, we will end up with a huge list of > defines (~300). Yeah, that is too much for a little gain. However, a few can be added for the interrupt only. Instead of LVTS_MONINT_THRES ..., it could be LVTS_INT_THRES_... and reused for LVTS_MONINTSTS and LVTS_MONINT setup as the bits position are the same? [ ... ] >>> +static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_ctrl) >>> +{ >>> + u32 period_unit = (118 * 1000) / (256 * 38); >> >> #define SOMETHING 118 >> #define SOMETHING_ELSE 1000 >> #define .... >> >> const u32 period_unit = (SOMETHING * SOMETHING_ELSE) / .... >> > > Constifying "u32 period_unit" generates the following compilation warning : > ./include/asm-generic/io.h:273:61: note: expected ‘volatile void *’ > but argument is of type ‘const void *’ > 273 | static inline void writel(u32 value, volatile void __iomem *addr) > | ~~~~~~~~~~~~~~~~~~~~~~~^~~~ That is strange. period_unit is the 'value', not the 'addr'. Are you sure about the warning? -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog