From: srinivas pandruvada <srinivas.pandruvada@linux.intel.com>
To: "Rafael J. Wysocki" <rafael@kernel.org>
Cc: daniel.lezcano@linaro.org, amitk@kernel.org, rui.zhang@intel.com,
linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org,
Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
Subject: Re: [PATCH RESEND 2/2] thermal: intel: Protect clearing of thermal status bits
Date: Fri, 18 Nov 2022 12:30:23 -0800 [thread overview]
Message-ID: <76cf2ce6e286d6226bda8b9b5f3e4b8df7ea5132.camel@linux.intel.com> (raw)
In-Reply-To: <CAJZ5v0j=LUkTtcQb3YVN0R3W4p7Cg-+wU8EAW75wz7bSTXhp4Q@mail.gmail.com>
On Fri, 2022-11-18 at 20:49 +0100, Rafael J. Wysocki wrote:
> On Fri, Nov 18, 2022 at 8:40 PM srinivas pandruvada
> <srinivas.pandruvada@linux.intel.com> wrote:
> >
> > On Fri, 2022-11-18 at 18:57 +0100, Rafael J. Wysocki wrote:
> > > On Wed, Nov 16, 2022 at 3:54 AM Srinivas Pandruvada
> > > <srinivas.pandruvada@linux.intel.com> wrote:
> > > >
> > > > The clearing of the package thermal status is done by Read-
> > > > Modify-
> > > > Write
> > > > operation. This may result in clearing of some new status bits
> > > > which are
> > > > being or about to be processed.
> > > >
> > > > For example, while clearing of HFI status, after read of thermal
> > > > status
> > > > register, a new thermal status bit is set by the hardware. But
> > > > during
> > > > write back, the newly generated status bit will be set to 0 or
> > > > cleared.
> > > > So, it is not safe to do read-modify-write.
> > > >
> > > > Since thermal status Read-Write bits can be set to only 0 not 1,
> > > > it
> > > > is
> > > > safe to set all other bits to 1 which are not getting cleared.
> > > >
> > > > Create a common interface for clearing package thermal status
> > > > bits.
> > > > Use
> > > > this interface to replace existing code to clear thermal package
> > > > status
> > > > bits.
> > > >
> > > > It is safe to call from different CPUs without protection as
> > > > there
> > > > is no
> > > > read-modify-write. Also wrmsrl results in just single
> > > > instruction.
> > > > For
> > > > example while CPU 0 and CPU 3 are clearing bit 1 and 3
> > > > respectively. If
> > > > CPU 3 wins the race, it will write 0x4000aa2, then CPU 1 will
> > > > write
> > > > 0x4000aa8. The bits which are not part of clear are set to 1. The
> > > > default
> > > > mask for bits, which can be written here is 0x4000aaa.
> > > >
> > > > Signed-off-by: Srinivas Pandruvada
> > > > <srinivas.pandruvada@linux.intel.com>
> > > > Reviewed-by: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
> > >
> > > How urgent is this? Would 6.2 be sufficient?
> > >
> > Not urgent. 6.2 should be enough.
>
> OK
>
> > > Also, do you want it to go into -stable?
> > Yes.
>
> Which series?
Cc: stable@vger.kernel.org # v5.18+
Thanks,
Srinivas
next prev parent reply other threads:[~2022-11-18 20:30 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-16 2:54 [PATCH RESEND 1/2] thermal: intel: Prevent accidental clearing of HFI status Srinivas Pandruvada
2022-11-16 2:54 ` [PATCH RESEND 2/2] thermal: intel: Protect clearing of thermal status bits Srinivas Pandruvada
2022-11-18 17:57 ` Rafael J. Wysocki
2022-11-18 19:39 ` srinivas pandruvada
2022-11-18 19:49 ` Rafael J. Wysocki
2022-11-18 20:30 ` srinivas pandruvada [this message]
2022-11-18 17:54 ` [PATCH RESEND 1/2] thermal: intel: Prevent accidental clearing of HFI status Rafael J. Wysocki
2022-11-18 19:35 ` srinivas pandruvada
2022-11-18 19:49 ` Rafael J. Wysocki
2022-11-23 19:10 ` Rafael J. Wysocki
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