From mboxrd@z Thu Jan 1 00:00:00 1970 From: Heiko Stuebner Subject: Re: [PATCH v3 4/5] arm64: dts: rk3399: Add dfi and dmc nodes. Date: Thu, 11 Apr 2019 15:20:53 +0200 Message-ID: <7786013.gjegOBUKu0@phil> References: <20190321231440.19031-1-gael.portay@collabora.com> <20190321231440.19031-5-gael.portay@collabora.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT Return-path: In-Reply-To: <20190321231440.19031-5-gael.portay@collabora.com> Sender: linux-kernel-owner@vger.kernel.org To: =?ISO-8859-1?Q?Ga=EBl?= PORTAY Cc: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring , Enric Balletbo i Serra , Lin Huang , Brian Norris , Douglas Anderson , Klaus Goger , Derek Basehore , Randy Li , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Mark Rutland List-Id: linux-pm@vger.kernel.org Hi Gaël, Am Freitag, 22. März 2019, 00:14:39 CEST schrieb Gaël PORTAY: > From: Lin Huang > > These are required to support DDR DVFS on rk3399 platform. The patch also > introduces a new file with default DRAM settings. > > Signed-off-by: Lin Huang > Signed-off-by: Enric Balletbo i Serra > Signed-off-by: Gaël PORTAY > + dmc: dmc { > + compatible = "rockchip,rk3399-dmc"; > + rockchip,pmu = <&pmugrf>; > + devfreq-events = <&dfi>; > + clocks = <&cru SCLK_DDRC>; > + clock-names = "dmc_clk"; > + status = "disabled"; > + rockchip,ddr3_speed_bin = <21>; > + rockchip,pd_idle = <0x40>; > + rockchip,sr_idle = <0x2>; > + rockchip,sr_mc_gate_idle = <0x3>; > + rockchip,srpd_lite_idle = <0x4>; > + rockchip,standby_idle = <0x2000>; > + rockchip,dram_dll_dis_freq = <300000000>; > + rockchip,phy_dll_dis_freq = <125000000>; > + rockchip,auto_pd_dis_freq = <666000000>; > + rockchip,ddr3_odt_dis_freq = <333000000>; > + rockchip,ddr3_drv = ; > + rockchip,ddr3_odt = ; > + rockchip,phy_ddr3_ca_drv = ; > + rockchip,phy_ddr3_dq_drv = ; > + rockchip,phy_ddr3_odt = ; > + rockchip,lpddr3_odt_dis_freq = <333000000>; > + rockchip,lpddr3_drv = ; > + rockchip,lpddr3_odt = ; > + rockchip,phy_lpddr3_ca_drv = ; > + rockchip,phy_lpddr3_dq_drv = ; > + rockchip,phy_lpddr3_odt = ; > + rockchip,lpddr4_odt_dis_freq = <333000000>; > + rockchip,lpddr4_drv = ; > + rockchip,lpddr4_dq_odt = ; > + rockchip,lpddr4_ca_odt = ; > + rockchip,phy_lpddr4_ca_drv = ; > + rockchip,phy_lpddr4_ck_cs_drv = ; > + rockchip,phy_lpddr4_dq_drv = ; > + rockchip,phy_lpddr4_odt = ; as Rob mentioned in his review, these values look board-specific, so should probably move over to the specific board you're using them on? Heiko From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCAD4C10F13 for ; Thu, 11 Apr 2019 13:21:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 93721206DF for ; Thu, 11 Apr 2019 13:21:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726517AbfDKNVL convert rfc822-to-8bit (ORCPT ); Thu, 11 Apr 2019 09:21:11 -0400 Received: from gloria.sntech.de ([185.11.138.130]:58476 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726264AbfDKNVL (ORCPT ); Thu, 11 Apr 2019 09:21:11 -0400 Received: from wf0380.dip.tu-dresden.de ([141.76.181.124] helo=phil.localnet) by gloria.sntech.de with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1hEZdO-00086a-Hc; Thu, 11 Apr 2019 15:20:54 +0200 From: Heiko Stuebner To: =?ISO-8859-1?Q?Ga=EBl?= PORTAY Cc: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring , Enric Balletbo i Serra , Lin Huang , Brian Norris , Douglas Anderson , Klaus Goger , Derek Basehore , Randy Li , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Mark Rutland Subject: Re: [PATCH v3 4/5] arm64: dts: rk3399: Add dfi and dmc nodes. Date: Thu, 11 Apr 2019 15:20:53 +0200 Message-ID: <7786013.gjegOBUKu0@phil> In-Reply-To: <20190321231440.19031-5-gael.portay@collabora.com> References: <20190321231440.19031-1-gael.portay@collabora.com> <20190321231440.19031-5-gael.portay@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8BIT Content-Type: text/plain; charset="UTF-8" Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Message-ID: <20190411132053.0SXnmUhArwkhqXuf5DbOtgsIWylOA49Dn8PAMiOa5nw@z> Hi Gaël, Am Freitag, 22. März 2019, 00:14:39 CEST schrieb Gaël PORTAY: > From: Lin Huang > > These are required to support DDR DVFS on rk3399 platform. The patch also > introduces a new file with default DRAM settings. > > Signed-off-by: Lin Huang > Signed-off-by: Enric Balletbo i Serra > Signed-off-by: Gaël PORTAY > + dmc: dmc { > + compatible = "rockchip,rk3399-dmc"; > + rockchip,pmu = <&pmugrf>; > + devfreq-events = <&dfi>; > + clocks = <&cru SCLK_DDRC>; > + clock-names = "dmc_clk"; > + status = "disabled"; > + rockchip,ddr3_speed_bin = <21>; > + rockchip,pd_idle = <0x40>; > + rockchip,sr_idle = <0x2>; > + rockchip,sr_mc_gate_idle = <0x3>; > + rockchip,srpd_lite_idle = <0x4>; > + rockchip,standby_idle = <0x2000>; > + rockchip,dram_dll_dis_freq = <300000000>; > + rockchip,phy_dll_dis_freq = <125000000>; > + rockchip,auto_pd_dis_freq = <666000000>; > + rockchip,ddr3_odt_dis_freq = <333000000>; > + rockchip,ddr3_drv = ; > + rockchip,ddr3_odt = ; > + rockchip,phy_ddr3_ca_drv = ; > + rockchip,phy_ddr3_dq_drv = ; > + rockchip,phy_ddr3_odt = ; > + rockchip,lpddr3_odt_dis_freq = <333000000>; > + rockchip,lpddr3_drv = ; > + rockchip,lpddr3_odt = ; > + rockchip,phy_lpddr3_ca_drv = ; > + rockchip,phy_lpddr3_dq_drv = ; > + rockchip,phy_lpddr3_odt = ; > + rockchip,lpddr4_odt_dis_freq = <333000000>; > + rockchip,lpddr4_drv = ; > + rockchip,lpddr4_dq_odt = ; > + rockchip,lpddr4_ca_odt = ; > + rockchip,phy_lpddr4_ca_drv = ; > + rockchip,phy_lpddr4_ck_cs_drv = ; > + rockchip,phy_lpddr4_dq_drv = ; > + rockchip,phy_lpddr4_odt = ; as Rob mentioned in his review, these values look board-specific, so should probably move over to the specific board you're using them on? Heiko